MIPS/GAS: Unify GP-relative percent-ops

For a reason that is unclear commit d6f1659387 ("Support for MIPS16
HI16/LO16 relocations"),
<https://sourceware.org/ml/binutils/2005-02/msg00332.html>, which has
added support for the R_MIPS16_GPREL relocation, has spelled its
corresponding MIPS16 percent-op as `%gprel', rather than `%gp_rel' which
is how its regular MIPS counterpart is spelled.  To make assembly code
sharing easier between the regular MIPS and the MIPS16 ISA make both
percent-op spellings acceptable in both kinds of code now.

Parts of this change by Matthew Fortune.

	gas/
	* config/tc-mips.c (mips_percent_op): Add "%gprel".
	(mips16_percent_op): Add "%gp_rel".
	* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
	* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
	* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
	* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
This commit is contained in:
Maciej W. Rozycki 2017-05-12 02:28:54 +01:00
parent a4f8991513
commit be3f100674
6 changed files with 38 additions and 1 deletions

View File

@ -1,3 +1,13 @@
2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
* config/tc-mips.c (mips_percent_op): Add "%gprel".
(mips16_percent_op): Add "%gp_rel".
* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.

View File

@ -14094,6 +14094,7 @@ static const struct percent_op_match mips_percent_op[] =
{"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
{"%got", BFD_RELOC_MIPS_GOT16},
{"%gp_rel", BFD_RELOC_GPREL16},
{"%gprel", BFD_RELOC_GPREL16},
{"%half", BFD_RELOC_16},
{"%highest", BFD_RELOC_MIPS_HIGHEST},
{"%higher", BFD_RELOC_MIPS_HIGHER},
@ -14113,6 +14114,7 @@ static const struct percent_op_match mips_percent_op[] =
static const struct percent_op_match mips16_percent_op[] =
{
{"%lo", BFD_RELOC_MIPS16_LO16},
{"%gp_rel", BFD_RELOC_MIPS16_GPREL},
{"%gprel", BFD_RELOC_MIPS16_GPREL},
{"%got", BFD_RELOC_MIPS16_GOT16},
{"%call16", BFD_RELOC_MIPS16_CALL16},

View File

@ -34,5 +34,11 @@ Disassembly of section \.text:
32: R_MIPS16_GPREL gvar
36: f000 4c00 addiu \$4,0
36: R_MIPS16_GPREL gvar
3a: 6500 nop
3a: f000 9a80 lw \$4,0\(\$2\)
3a: R_MIPS16_GPREL gvar
3e: f000 da80 sw \$4,0\(\$2\)
3e: R_MIPS16_GPREL gvar
42: f000 4c00 addiu \$4,0
42: R_MIPS16_GPREL gvar
46: 6500 nop
#pass

View File

@ -32,6 +32,13 @@ foo:
lw $4,%gprel(gvar)($2)
sw $4,%gprel(gvar)($2)
addiu $4,%gprel(gvar)
# Check the alternative form.
lw $4,%gp_rel(gvar)($2)
sw $4,%gp_rel(gvar)($2)
addiu $4,%gp_rel(gvar)
.align 6
.end foo

View File

@ -54,4 +54,10 @@ Disassembly of section \.text:
5c: R_MIPS_GPREL16 gvar
60: 27840000 addiu \$4,\$28,0
60: R_MIPS_GPREL16 gvar
64: 8f840000 lw \$4,0\(\$28\)
64: R_MIPS_GPREL16 gvar
68: af840000 sw \$4,0\(\$28\)
68: R_MIPS_GPREL16 gvar
6c: 27840000 addiu \$4,\$28,0
6c: R_MIPS_GPREL16 gvar
\.\.\.

View File

@ -46,6 +46,12 @@ foo:
sw $4,%gp_rel(gvar)($28)
addiu $4,$28,%gp_rel(gvar)
# Check the alternative form.
lw $4,%gprel(gvar)($28)
sw $4,%gprel(gvar)($28)
addiu $4,$28,%gprel(gvar)
.space 64
.end foo