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MIPS/GAS: Unify GP-relative percent-ops
For a reason that is unclear commit d6f1659387
("Support for MIPS16
HI16/LO16 relocations"),
<https://sourceware.org/ml/binutils/2005-02/msg00332.html>, which has
added support for the R_MIPS16_GPREL relocation, has spelled its
corresponding MIPS16 percent-op as `%gprel', rather than `%gp_rel' which
is how its regular MIPS counterpart is spelled. To make assembly code
sharing easier between the regular MIPS and the MIPS16 ISA make both
percent-op spellings acceptable in both kinds of code now.
Parts of this change by Matthew Fortune.
gas/
* config/tc-mips.c (mips_percent_op): Add "%gprel".
(mips16_percent_op): Add "%gp_rel".
* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
This commit is contained in:
parent
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commit
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@ -1,3 +1,13 @@
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2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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* config/tc-mips.c (mips_percent_op): Add "%gprel".
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(mips16_percent_op): Add "%gp_rel".
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* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
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* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
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* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
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* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
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2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
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@ -14094,6 +14094,7 @@ static const struct percent_op_match mips_percent_op[] =
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{"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
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{"%got", BFD_RELOC_MIPS_GOT16},
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{"%gp_rel", BFD_RELOC_GPREL16},
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{"%gprel", BFD_RELOC_GPREL16},
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{"%half", BFD_RELOC_16},
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{"%highest", BFD_RELOC_MIPS_HIGHEST},
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{"%higher", BFD_RELOC_MIPS_HIGHER},
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@ -14113,6 +14114,7 @@ static const struct percent_op_match mips_percent_op[] =
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static const struct percent_op_match mips16_percent_op[] =
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{
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{"%lo", BFD_RELOC_MIPS16_LO16},
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{"%gp_rel", BFD_RELOC_MIPS16_GPREL},
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{"%gprel", BFD_RELOC_MIPS16_GPREL},
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{"%got", BFD_RELOC_MIPS16_GOT16},
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{"%call16", BFD_RELOC_MIPS16_CALL16},
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@ -34,5 +34,11 @@ Disassembly of section \.text:
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32: R_MIPS16_GPREL gvar
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36: f000 4c00 addiu \$4,0
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36: R_MIPS16_GPREL gvar
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3a: 6500 nop
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3a: f000 9a80 lw \$4,0\(\$2\)
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3a: R_MIPS16_GPREL gvar
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3e: f000 da80 sw \$4,0\(\$2\)
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3e: R_MIPS16_GPREL gvar
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42: f000 4c00 addiu \$4,0
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42: R_MIPS16_GPREL gvar
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46: 6500 nop
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#pass
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@ -32,6 +32,13 @@ foo:
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lw $4,%gprel(gvar)($2)
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sw $4,%gprel(gvar)($2)
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addiu $4,%gprel(gvar)
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# Check the alternative form.
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lw $4,%gp_rel(gvar)($2)
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sw $4,%gp_rel(gvar)($2)
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addiu $4,%gp_rel(gvar)
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.align 6
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.end foo
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@ -54,4 +54,10 @@ Disassembly of section \.text:
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5c: R_MIPS_GPREL16 gvar
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60: 27840000 addiu \$4,\$28,0
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60: R_MIPS_GPREL16 gvar
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64: 8f840000 lw \$4,0\(\$28\)
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64: R_MIPS_GPREL16 gvar
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68: af840000 sw \$4,0\(\$28\)
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68: R_MIPS_GPREL16 gvar
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6c: 27840000 addiu \$4,\$28,0
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6c: R_MIPS_GPREL16 gvar
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\.\.\.
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@ -46,6 +46,12 @@ foo:
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sw $4,%gp_rel(gvar)($28)
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addiu $4,$28,%gp_rel(gvar)
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# Check the alternative form.
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lw $4,%gprel(gvar)($28)
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sw $4,%gprel(gvar)($28)
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addiu $4,$28,%gprel(gvar)
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.space 64
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.end foo
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