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RISC-V: Add reductions instructions for T-Head VECTOR vendor extension

Browse Source 
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds reductions instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	reductions instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
This commit is contained in:
Jin Ma 2023-11-18 15:08:12 +08:00 committed by Nelson Chu
parent 1ba39b6fe5
commit b4cf88da83
3 changed files with 84 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
gas/testsuite/gas/riscv/x-thead-vector.d
View File

@ -1560,3 +1560,35 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+88891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8,v0.t
[ ]+[0-9a-f]+:[ ]+88899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8,v0.t
[ ]+[0-9a-f]+:[ ]+888a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8,v0.t
[ ]+[0-9a-f]+:[ ]+02862257[ ]+th.vredsum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+1a842257[ ]+th.vredmaxu.vs[ ]+v4,v8,v8
[ ]+[0-9a-f]+:[ ]+1e842257[ ]+th.vredmax.vs[ ]+v4,v8,v8
[ ]+[0-9a-f]+:[ ]+12842257[ ]+th.vredminu.vs[ ]+v4,v8,v8
[ ]+[0-9a-f]+:[ ]+16842257[ ]+th.vredmin.vs[ ]+v4,v8,v8
[ ]+[0-9a-f]+:[ ]+06862257[ ]+th.vredand.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+0a862257[ ]+th.vredor.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+0e862257[ ]+th.vredxor.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+00862257[ ]+th.vredsum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+18842257[ ]+th.vredmaxu.vs[ ]+v4,v8,v8,v0.t
[ ]+[0-9a-f]+:[ ]+1c842257[ ]+th.vredmax.vs[ ]+v4,v8,v8,v0.t
[ ]+[0-9a-f]+:[ ]+10842257[ ]+th.vredminu.vs[ ]+v4,v8,v8,v0.t
[ ]+[0-9a-f]+:[ ]+14842257[ ]+th.vredmin.vs[ ]+v4,v8,v8,v0.t
[ ]+[0-9a-f]+:[ ]+04862257[ ]+th.vredand.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+08862257[ ]+th.vredor.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+0c862257[ ]+th.vredxor.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+c2860257[ ]+th.vwredsumu.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+c6860257[ ]+th.vwredsum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+c0860257[ ]+th.vwredsumu.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+c4860257[ ]+th.vwredsum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+0e861257[ ]+th.vfredosum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+06861257[ ]+th.vfredsum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+1e861257[ ]+th.vfredmax.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+16861257[ ]+th.vfredmin.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+0c861257[ ]+th.vfredosum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+04861257[ ]+th.vfredsum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+1c861257[ ]+th.vfredmax.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+14861257[ ]+th.vfredmin.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+ce861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+c6861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t

36
gas/testsuite/gas/riscv/x-thead-vector.s
View File

@ -1620,3 +1620,39 @@
th.vfncvt.f.xu.v v4, v8, v0.t
th.vfncvt.f.x.v v4, v8, v0.t
th.vfncvt.f.f.v v4, v8, v0.t
th.vredsum.vs v4, v8, v12
th.vredmaxu.vs v4, v8, v8
th.vredmax.vs v4, v8, v8
th.vredminu.vs v4, v8, v8
th.vredmin.vs v4, v8, v8
th.vredand.vs v4, v8, v12
th.vredor.vs v4, v8, v12
th.vredxor.vs v4, v8, v12
th.vredsum.vs v4, v8, v12, v0.t
th.vredmaxu.vs v4, v8, v8, v0.t
th.vredmax.vs v4, v8, v8, v0.t
th.vredminu.vs v4, v8, v8, v0.t
th.vredmin.vs v4, v8, v8, v0.t
th.vredand.vs v4, v8, v12, v0.t
th.vredor.vs v4, v8, v12, v0.t
th.vredxor.vs v4, v8, v12, v0.t
th.vwredsumu.vs v4, v8, v12
th.vwredsum.vs v4, v8, v12
th.vwredsumu.vs v4, v8, v12, v0.t
th.vwredsum.vs v4, v8, v12, v0.t
th.vfredosum.vs v4, v8, v12
th.vfredsum.vs v4, v8, v12
th.vfredmax.vs v4, v8, v12
th.vfredmin.vs v4, v8, v12
th.vfredosum.vs v4, v8, v12, v0.t
th.vfredsum.vs v4, v8, v12, v0.t
th.vfredmax.vs v4, v8, v12, v0.t
th.vfredmin.vs v4, v8, v12, v0.t
th.vfwredosum.vs v4, v8, v12
th.vfwredsum.vs v4, v8, v12
th.vfwredosum.vs v4, v8, v12, v0.t
th.vfwredsum.vs v4, v8, v12, v0.t

16
opcodes/riscv-opc.c
View File

@ -2844,6 +2844,22 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0},
{"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0},
{"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0},
{"th.vredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
{"th.vredmaxu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
{"th.vredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
{"th.vredminu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
{"th.vredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
{"th.vredand.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
{"th.vredor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
{"th.vredxor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
{"th.vwredsumu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
{"th.vwredsum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
{"th.vfredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
{"th.vfredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0},
{"th.vfredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
{"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
{"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
{"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },