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* config/tc-arm.c (thumb_opcode): Add "variants" field.

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(tinsns): Initialize variants field.
This commit is contained in:
Jeff Law 1999-10-28 02:53:42 +00:00
parent 90ca882f04
commit b49cfa5dae
2 changed files with 62 additions and 58 deletions
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7
gas/ChangeLog
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@ -1,7 +1,10 @@
Wed Oct 27 16:50:44 1999 Don Lindsay <dlindsay@cygnus.com>
* tc-arm.c (bad_args, bad_pc): Renamed to BAD_ARGS and BAD_PC
respectively.
* config/tc-arm.c (thumb_opcode): Add "variants" field.
(tinsns): Initialize variants field.
* config/tc-arm.c (bad_args, bad_pc): Renamed to BAD_ARGS and
BAD_PC respectively.
1999-10-27 Scott Bambrough <scottb@netwinder.org>

113
gas/config/tc-arm.c
View File

@ -770,68 +770,69 @@ struct thumb_opcode
CONST char * template; /* Basic string to match */
unsigned long value; /* Basic instruction code */
int size;
unsigned long variants; /* Which CPU variants this exists for */
void (* parms) PARAMS ((char *)); /* Function to call to parse args */
};
static CONST struct thumb_opcode tinsns[] =
{
{"adc", 0x4140, 2, do_t_arit},
{"add", 0x0000, 2, do_t_add},
{"and", 0x4000, 2, do_t_arit},
{"asr", 0x0000, 2, do_t_asr},
{"b", T_OPCODE_BRANCH, 2, do_t_branch12},
{"beq", 0xd0fe, 2, do_t_branch9},
{"bne", 0xd1fe, 2, do_t_branch9},
{"bcs", 0xd2fe, 2, do_t_branch9},
{"bhs", 0xd2fe, 2, do_t_branch9},
{"bcc", 0xd3fe, 2, do_t_branch9},
{"bul", 0xd3fe, 2, do_t_branch9},
{"blo", 0xd3fe, 2, do_t_branch9},
{"bmi", 0xd4fe, 2, do_t_branch9},
{"bpl", 0xd5fe, 2, do_t_branch9},
{"bvs", 0xd6fe, 2, do_t_branch9},
{"bvc", 0xd7fe, 2, do_t_branch9},
{"bhi", 0xd8fe, 2, do_t_branch9},
{"bls", 0xd9fe, 2, do_t_branch9},
{"bge", 0xdafe, 2, do_t_branch9},
{"blt", 0xdbfe, 2, do_t_branch9},
{"bgt", 0xdcfe, 2, do_t_branch9},
{"ble", 0xddfe, 2, do_t_branch9},
{"bic", 0x4380, 2, do_t_arit},
{"bl", 0xf7fffffe, 4, do_t_branch23},
{"bx", 0x4700, 2, do_t_bx},
{"cmn", T_OPCODE_CMN, 2, do_t_arit},
{"cmp", 0x0000, 2, do_t_compare},
{"eor", 0x4040, 2, do_t_arit},
{"ldmia", 0xc800, 2, do_t_ldmstm},
{"ldr", 0x0000, 2, do_t_ldr},
{"ldrb", 0x0000, 2, do_t_ldrb},
{"ldrh", 0x0000, 2, do_t_ldrh},
{"ldrsb", 0x5600, 2, do_t_lds},
{"ldrsh", 0x5e00, 2, do_t_lds},
{"ldsb", 0x5600, 2, do_t_lds},
{"ldsh", 0x5e00, 2, do_t_lds},
{"lsl", 0x0000, 2, do_t_lsl},
{"lsr", 0x0000, 2, do_t_lsr},
{"mov", 0x0000, 2, do_t_mov},
{"mul", T_OPCODE_MUL, 2, do_t_arit},
{"mvn", T_OPCODE_MVN, 2, do_t_arit},
{"neg", T_OPCODE_NEG, 2, do_t_arit},
{"orr", 0x4300, 2, do_t_arit},
{"pop", 0xbc00, 2, do_t_push_pop},
{"push", 0xb400, 2, do_t_push_pop},
{"ror", 0x41c0, 2, do_t_arit},
{"sbc", 0x4180, 2, do_t_arit},
{"stmia", 0xc000, 2, do_t_ldmstm},
{"str", 0x0000, 2, do_t_str},
{"strb", 0x0000, 2, do_t_strb},
{"strh", 0x0000, 2, do_t_strh},
{"swi", 0xdf00, 2, do_t_swi},
{"sub", 0x0000, 2, do_t_sub},
{"tst", T_OPCODE_TST, 2, do_t_arit},
{"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
{"add", 0x0000, 2, ARM_THUMB, do_t_add},
{"and", 0x4000, 2, ARM_THUMB, do_t_arit},
{"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
{"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
{"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
{"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
{"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
{"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
{"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
{"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
{"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
{"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
{"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
{"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
{"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
{"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
{"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
{"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
{"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
{"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
{"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
{"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
{"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
{"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
{"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
{"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
{"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
{"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
{"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
{"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
{"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
{"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
{"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
{"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
{"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
{"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
{"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
{"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
{"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
{"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
{"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
{"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
{"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
{"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
{"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
{"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
{"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
{"str", 0x0000, 2, ARM_THUMB, do_t_str},
{"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
{"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
{"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
{"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
{"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
/* Pseudo ops: */
{"adr", 0x0000, 2, do_t_adr},
{"nop", 0x46C0, 2, do_t_nop}, /* mov r8,r8 */
{"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
{"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
};
struct reg_entry