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gdb/arm: fix IPSR field test in arm_m_exception_cache ()
Arm v8-M Architecture Reference Manual, D1.2.141 IPSR, Interrupt Program Status Register reads "Exception, bits [8:0]" 9 bits, not 8! It is uncommon but true! Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
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@ -3441,7 +3441,7 @@ arm_m_exception_cache (frame_info_ptr this_frame)
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}
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ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
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if ((xpsr & 0xff) != 0)
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if ((xpsr & 0x1ff) != 0)
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/* Handler mode: This is the mode that exceptions are handled in. */
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arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
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else
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