mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-23 18:14:13 +08:00
2003-12-02 Alexandre Oliva <aoliva@redhat.com>
* sh-opc.h: Add support for sh4a and no-fpu variants. * sh-dis.c: Ditto.
This commit is contained in:
Michael Snyder
parent
88da98f3d4
commit
aeadede63f
126
opcodes/sh-dis.c
126
opcodes/sh-dis.c
@ -49,18 +49,28 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
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switch (op->arg[n])
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{
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case A_IND_N:
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case AX_IND_N:
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case AXY_IND_N:
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case AY_IND_N:
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case AYX_IND_N:
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fprintf_fn (stream, "@r%d", rn);
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break;
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case A_INC_N:
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case AX_INC_N:
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case AXY_INC_N:
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case AY_INC_N:
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case AYX_INC_N:
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fprintf_fn (stream, "@r%d+", rn);
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break;
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case A_PMOD_N:
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case AX_PMOD_N:
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case AXY_PMOD_N:
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fprintf_fn (stream, "@r%d+r8", rn);
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break;
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case A_PMODY_N:
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case AY_PMOD_N:
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case AYX_PMOD_N:
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fprintf_fn (stream, "@r%d+r9", rn);
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break;
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case DSP_REG_M:
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case DSP_REG_A_M:
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fprintf_fn (stream, "a%c", '0' + rm);
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break;
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case DSP_REG_X:
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@ -69,6 +79,26 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
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case DSP_REG_Y:
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fprintf_fn (stream, "y%c", '0' + rm);
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break;
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case DSP_REG_AX:
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fprintf_fn (stream, "%c%c",
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(rm & 1) ? 'x' : 'a',
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(rm & 2) ? '1' : '0');
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break;
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case DSP_REG_XY:
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fprintf_fn (stream, "%c%c",
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(rm & 1) ? 'y' : 'x',
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(rm & 2) ? '1' : '0');
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break;
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case DSP_REG_AY:
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fprintf_fn (stream, "%c%c",
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(rm & 2) ? 'y' : 'a',
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(rm & 1) ? '1' : '0');
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break;
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case DSP_REG_YX:
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fprintf_fn (stream, "%c%c",
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(rm & 2) ? 'x' : 'y',
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(rm & 1) ? '1' : '0');
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break;
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default:
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abort ();
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}
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@ -102,7 +132,41 @@ print_insn_ddt (insn, info)
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/* Check if either the x or y part is invalid. */
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if (((insn & 0xc) == 0 && (insn & 0x2a0))
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|| ((insn & 3) == 0 && (insn & 0x150)))
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fprintf_fn (stream, ".word 0x%x", insn);
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if (info->mach != bfd_mach_sh_dsp
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&& info->mach != bfd_mach_sh3_dsp)
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{
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static const sh_opcode_info *first_movx, *first_movy;
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const sh_opcode_info *op;
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int is_movy;
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if (! first_movx)
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{
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for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
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first_movx++;
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for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
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first_movy++;
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}
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is_movy = ((insn & 3) != 0);
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if (is_movy)
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op = first_movy;
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else
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op = first_movx;
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while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
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|| op->nibbles[3] != (unsigned) (insn & 0xf))
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op++;
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print_movxy (op,
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(4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
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+ 2 * is_movy
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+ 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
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(insn >> 6) & 3,
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fprintf_fn, stream);
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}
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else
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fprintf_fn (stream, ".word 0x%x", insn);
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else
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{
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static const sh_opcode_info *first_movx, *first_movy;
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@ -191,6 +255,7 @@ print_insn_ppi (field_b, info)
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fprintf_ftype fprintf_fn = info->fprintf_func;
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void *stream = info->stream;
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unsigned int nib1, nib2, nib3;
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unsigned int altnib1, nib4;
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char *dc = NULL;
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const sh_opcode_info *op;
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@ -217,6 +282,16 @@ print_insn_ppi (field_b, info)
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sy_tab[(field_b >> 4) & 3],
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du_tab[(field_b >> 0) & 3]);
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}
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else if ((field_b & 0xf0) == 0x10
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&& info->mach != bfd_mach_sh_dsp
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&& info->mach != bfd_mach_sh3_dsp)
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{
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fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
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}
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else if ((field_b & 0xf3) != 0)
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{
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fprintf_fn (stream, ".word 0x%x\t", field_b);
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}
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fprintf_fn (stream, "pmuls%c%s,%s,%s",
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field_b & 0x2000 ? ' ' : '\t',
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se_tab[(field_b >> 10) & 3],
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@ -228,6 +303,7 @@ print_insn_ppi (field_b, info)
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nib1 = PPIC;
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nib2 = field_b >> 12 & 0xf;
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nib3 = field_b >> 8 & 0xf;
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nib4 = field_b >> 4 & 0xf;
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switch (nib3 & 0x3)
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{
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case 0:
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@ -246,14 +322,41 @@ print_insn_ppi (field_b, info)
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nib3 -= 2;
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break;
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}
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if (nib1 == PPI3)
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altnib1 = PPI3NC;
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else
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altnib1 = nib1;
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for (op = sh_table; op->name; op++)
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{
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if (op->nibbles[1] == nib1
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if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
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&& op->nibbles[2] == nib2
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&& op->nibbles[3] == nib3)
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{
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int n;
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switch (op->nibbles[4])
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{
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case HEX_0:
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break;
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case HEX_XX00:
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if ((nib4 & 3) != 0)
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continue;
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break;
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case HEX_1:
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if ((nib4 & 3) != 1)
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continue;
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break;
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case HEX_00YY:
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if ((nib4 & 0xc) != 0)
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continue;
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break;
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case HEX_4:
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if ((nib4 & 0xc) != 4)
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continue;
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break;
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default:
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abort ();
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}
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fprintf_fn (stream, "%s%s\t", dc, op->name);
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for (n = 0; n < 3 && op->arg[n] != A_END; n++)
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{
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@ -331,8 +434,16 @@ print_insn_sh (memaddr, info)
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target_arch = arch_sh3e;
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break;
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case bfd_mach_sh4:
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case bfd_mach_sh4_nofpu:
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target_arch = arch_sh4;
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break;
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case bfd_mach_sh4a:
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case bfd_mach_sh4a_nofpu:
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target_arch = arch_sh4a;
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break;
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case bfd_mach_sh4al_dsp:
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target_arch = arch_sh4al_dsp;
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break;
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case bfd_mach_sh5:
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#ifdef INCLUDE_SHMEDIA
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status = print_insn_sh64 (memaddr, info);
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@ -514,18 +625,21 @@ print_insn_sh (memaddr, info)
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fprintf_fn (stream, "r%d", rn);
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break;
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case A_INC_N:
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case AS_INC_N:
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fprintf_fn (stream, "@r%d+", rn);
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break;
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case A_DEC_N:
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case AS_DEC_N:
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fprintf_fn (stream, "@-r%d", rn);
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break;
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case A_IND_N:
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case AS_IND_N:
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fprintf_fn (stream, "@r%d", rn);
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break;
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case A_DISP_REG_N:
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fprintf_fn (stream, "@(%d,r%d)", imm, rn);
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break;
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case A_PMOD_N:
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case AS_PMOD_N:
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fprintf_fn (stream, "@r%d+r8", rn);
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break;
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case A_REG_M:
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192
opcodes/sh-opc.h
192
opcodes/sh-opc.h
@ -34,6 +34,8 @@ typedef enum
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HEX_D,
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HEX_E,
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HEX_F,
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HEX_XX00,
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HEX_00YY,
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REG_N,
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REG_M,
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SDT_REG_N,
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@ -60,9 +62,12 @@ typedef enum
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NOPY,
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MOVX,
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MOVY,
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MOVX_NOPY,
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MOVY_NOPX,
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PSH,
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PMUL,
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PPI3,
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PPI3NC,
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PDC,
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PPIC,
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REPEAT
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@ -88,8 +93,6 @@ typedef enum
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A_INC_N,
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A_IND_M,
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A_IND_N,
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A_PMOD_N,
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A_PMODY_N,
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A_IND_R0_REG_M,
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A_IND_R0_REG_N,
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A_MACH,
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@ -113,6 +116,27 @@ typedef enum
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DSP_REG_E,
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DSP_REG_F,
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DSP_REG_G,
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DSP_REG_A_M,
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DSP_REG_AX,
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DSP_REG_XY,
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DSP_REG_AY,
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DSP_REG_YX,
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AX_INC_N,
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AY_INC_N,
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AXY_INC_N,
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AYX_INC_N,
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AX_IND_N,
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AY_IND_N,
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AXY_IND_N,
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AYX_IND_N,
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AX_PMOD_N,
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AXY_PMOD_N,
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AY_PMOD_N,
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AYX_PMOD_N,
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AS_DEC_N,
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AS_INC_N,
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AS_IND_N,
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AS_PMOD_N,
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A_A0,
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A_X0,
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A_X1,
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@ -156,24 +180,34 @@ sh_dsp_reg_nums;
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#define arch_sh3e 0x0008
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#define arch_sh4 0x0010
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#define arch_sh2e 0x0020
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#define arch_sh4a 0x0040
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#define arch_sh_dsp 0x0100
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#define arch_sh3_dsp 0x0200
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#define arch_sh4al_dsp 0x0400
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#define arch_sh4_nofpu 0x1000
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#define arch_sh4a_nofpu 0x2000
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#define arch_sh1_up (arch_sh1 | arch_sh2_up)
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#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
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#define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
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#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp)
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#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
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| arch_sh4_nofp_up)
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#define arch_sh3e_up (arch_sh3e | arch_sh4_up)
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#define arch_sh4_up arch_sh4
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#define arch_sh4_up (arch_sh4 | arch_sh4a_up)
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#define arch_sh4a_up (arch_sh4a)
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#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
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#define arch_sh3_dsp_up arch_sh3_dsp
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#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
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#define arch_sh4al_dsp_up (arch_sh4al_dsp)
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#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
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#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
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typedef struct
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{
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char *name;
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sh_arg_type arg[4];
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sh_nibble_type nibbles[4];
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sh_nibble_type nibbles[5];
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int arch;
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} sh_opcode_info;
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@ -211,6 +245,8 @@ const sh_opcode_info sh_table[] =
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/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
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/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
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/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up},
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/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up},
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@ -249,6 +285,8 @@ const sh_opcode_info sh_table[] =
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/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up},
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/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up},
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/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up},
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/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up},
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@ -269,7 +307,7 @@ const sh_opcode_info sh_table[] =
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/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up},
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/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_up},
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/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
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/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up},
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@ -289,10 +327,13 @@ const sh_opcode_info sh_table[] =
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/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up},
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/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_up},
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/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up},
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/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up},
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/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
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/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
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/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
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/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
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@ -414,11 +455,16 @@ const sh_opcode_info sh_table[] =
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/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
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/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
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/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up},
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/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up},
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/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
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/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
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/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up},
|
||||
|
||||
/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up},
|
||||
/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up},
|
||||
|
||||
/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
|
||||
/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
|
||||
|
||||
@ -434,11 +480,11 @@ const sh_opcode_info sh_table[] =
|
||||
/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
|
||||
|
||||
/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
|
||||
/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_up},
|
||||
/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up},
|
||||
|
||||
/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_up},
|
||||
/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up},
|
||||
|
||||
/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up},
|
||||
/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up},
|
||||
|
||||
|
||||
/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
|
||||
@ -447,7 +493,9 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
|
||||
|
||||
/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up},
|
||||
/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up},
|
||||
|
||||
/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
|
||||
|
||||
/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up},
|
||||
|
||||
@ -461,6 +509,9 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up},
|
||||
|
||||
/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up},
|
||||
/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up},
|
||||
|
||||
/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up},
|
||||
/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up},
|
||||
|
||||
@ -514,9 +565,9 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up},
|
||||
|
||||
/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_up},
|
||||
/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up},
|
||||
|
||||
/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_up},
|
||||
/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
|
||||
|
||||
/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up},
|
||||
|
||||
@ -536,9 +587,9 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
|
||||
|
||||
/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up},
|
||||
/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up},
|
||||
|
||||
/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_up},
|
||||
/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up},
|
||||
|
||||
/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up},
|
||||
|
||||
@ -596,6 +647,8 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up},
|
||||
|
||||
/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up},
|
||||
|
||||
/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
|
||||
|
||||
/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
|
||||
@ -634,7 +687,7 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
|
||||
/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
|
||||
|
||||
/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
|
||||
|
||||
@ -642,7 +695,7 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
|
||||
|
||||
/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
|
||||
/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
|
||||
|
||||
/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
|
||||
|
||||
@ -650,7 +703,7 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
|
||||
|
||||
/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
|
||||
/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
|
||||
|
||||
/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
|
||||
|
||||
@ -658,22 +711,51 @@ const sh_opcode_info sh_table[] =
|
||||
|
||||
/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
|
||||
|
||||
/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
|
||||
/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
|
||||
|
||||
/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
|
||||
/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
|
||||
/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{A_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
|
||||
/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{A_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
|
||||
/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{A_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
|
||||
/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_M,A_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
|
||||
/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_M,A_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
|
||||
/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_M,A_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
|
||||
/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{A_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
|
||||
/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{A_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
|
||||
/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{A_PMODY_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
|
||||
/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_M,A_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
|
||||
/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_M,A_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
|
||||
/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_M,A_PMODY_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
|
||||
/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
|
||||
/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
|
||||
/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
|
||||
/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
|
||||
/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
|
||||
/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
|
||||
|
||||
/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up},
|
||||
/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up},
|
||||
/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up},
|
||||
/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up},
|
||||
/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up},
|
||||
/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up},
|
||||
|
||||
/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up},
|
||||
/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up},
|
||||
/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up},
|
||||
/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up},
|
||||
/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up},
|
||||
/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up},
|
||||
|
||||
/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
|
||||
/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
|
||||
/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
|
||||
/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
|
||||
/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
|
||||
/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
|
||||
|
||||
/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up},
|
||||
/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up},
|
||||
/* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up},
|
||||
/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up},
|
||||
/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up},
|
||||
/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up},
|
||||
|
||||
/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up},
|
||||
/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up},
|
||||
/* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up},
|
||||
/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up},
|
||||
/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up},
|
||||
/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up},
|
||||
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||||
/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up},
|
||||
/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
||||
@ -687,13 +769,21 @@ const sh_opcode_info sh_table[] =
|
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/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
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{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
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||||
/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
|
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{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up},
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{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
|
||||
/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
|
||||
/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up},
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||||
{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
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||||
/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
|
||||
/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up},
|
||||
{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
|
||||
/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
|
||||
/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up},
|
||||
{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
|
||||
/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
|
||||
|
||||
{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
|
||||
{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
|
||||
@ -706,6 +796,8 @@ const sh_opcode_info sh_table[] =
|
||||
/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
|
||||
/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
|
||||
/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */
|
||||
{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
|
||||
/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
|
||||
/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
|
||||
@ -718,16 +810,16 @@ const sh_opcode_info sh_table[] =
|
||||
{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
|
||||
/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
|
||||
/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up},
|
||||
/* 10111001xxyynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up},
|
||||
/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
|
||||
/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
|
||||
/* 10001101xxyynnnn pclr <DSP_REG_N> */
|
||||
{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
|
||||
/* 10011101xxyynnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D}, arch_sh_dsp_up},
|
||||
/* 10111101xxyynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up},
|
||||
/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
|
||||
/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
|
||||
/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
|
||||
/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */
|
||||
@ -744,6 +836,10 @@ const sh_opcode_info sh_table[] =
|
||||
{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
|
||||
/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
|
||||
{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
|
||||
/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */
|
||||
{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
|
||||
/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */
|
||||
{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
|
||||
|
||||
/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
|
||||
/* 1111nnnn01011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up},
|
||||
@ -828,13 +924,19 @@ const sh_opcode_info sh_table[] =
|
||||
/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
|
||||
/* 1111nnnn01001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up},
|
||||
|
||||
/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
|
||||
|
||||
/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
|
||||
|
||||
/* 1111nnn011111101 fsca FPUL,<F_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_F,HEX_D}, arch_sh4a_up},
|
||||
|
||||
/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up},
|
||||
|
||||
/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up},
|
||||
/* 1111nnnn01101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up},
|
||||
|
||||
/* 1111nnnn01111101 fssra <F_REG_N> */{"fssra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4a_up},
|
||||
|
||||
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
|
||||
|
||||
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user