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or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts
Reported by Rich Felker when building on 32-bit hosts. Backwards jump negative offsets were not calculated correctly due to improper 32-bit to 64-bit zero-extension. The 64-bit fields are present because we are mixing 32-bit and 64-bit architectures in our cpu descriptions. Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture spec for 64-bit but no implementations or simulators. My thought is if we need them in the future we should do the proper work to support both 32-bit and 64-bit implementations co-existing then. cpu/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> PR 25184 * or1k.cpu (arch or1k): Remove or64 and or64nd machs. (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros. (cpu or1k64bf, mach or64, mach or64nd): Remove definitions. * or1kcommon.cpu (h-fdr): Remove hardware. * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions. (float-regreg-insn): Remove lf- mnemonic -d instruction pattern. (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern. (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern. (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
This commit is contained in:
Stafford Horne
parent
7e05773767
commit
ae440402f5
@ -1,3 +1,16 @@
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2020-05-19 Stafford Horne <shorne@gmail.com>
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PR 25184
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* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
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(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
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(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
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* or1kcommon.cpu (h-fdr): Remove hardware.
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* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
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(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
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(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
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(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
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(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
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2020-02-16 David Faust <david.faust@oracle.com>
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* bpf.cpu (define-cond-jump-insn): Renamed from djci.
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35
cpu/or1k.cpu
35
cpu/or1k.cpu
@ -31,7 +31,7 @@
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(comment "OpenRISC 1000")
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(default-alignment aligned)
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(insn-lsb0? #t)
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(machs or32 or32nd or64 or64nd)
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(machs or32 or32nd)
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(isas openrisc)
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)
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@ -44,10 +44,8 @@
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)
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(define-pmacro OR32-MACHS or32,or32nd)
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(define-pmacro OR64-MACHS or64,or64nd)
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(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
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(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
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(define-pmacro ORFPX64-MACHS or64,or64nd)
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(define-pmacro ORBIS-MACHS or32,or32nd)
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(define-pmacro ORFPX32-MACHS or32,or32nd)
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(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
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(define-attr
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@ -100,33 +98,6 @@
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)
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)
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(if (keep-mach? (or64 or64nd))
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(begin
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(define-cpu
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(name or1k64bf)
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(comment "OpenRISC 1000 64-bit CPU family")
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(insn-endian big)
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(data-endian big)
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(word-bitsize 64)
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(file-transform "64")
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)
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(define-mach
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(name or64)
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(comment "Generic OpenRISC 1000 64-bit CPU")
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(cpu or1k64bf)
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(bfd-name "or1k64")
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)
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(define-mach
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(name or64nd)
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(comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
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(cpu or1k64bf)
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(bfd-name "or1k64nd")
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)
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)
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)
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(include "or1kcommon.cpu")
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(include "or1korbis.cpu")
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(include "or1korfpx.cpu")
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@ -114,20 +114,6 @@
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(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
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)
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;
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; Hardware: virtual registerts for FPU (double precision)
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; mapped to GPRs
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;
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(define-hardware
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(name h-fdr)
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(comment "or64 floating point registers (double, virtual)")
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(attrs VIRTUAL (MACH ORFPX64-MACHS))
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(type register DF (32))
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(indices keyword "" REG-INDICES)
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(get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
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(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
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)
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;
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; Register pairs are offset by 2 for registers r16 and above. This is to
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; be able to allow registers to be call saved in GCC across function calls.
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@ -84,10 +84,6 @@
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(dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2)
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(dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3)
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(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
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(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2)
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(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3)
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(define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
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(begin
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(define-multi-ifield
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@ -152,14 +148,6 @@
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(set SF rDSF (mnemonic SF rASF rBSF))
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()
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)
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(dni (.sym lf- mnemonic -d)
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(.str "lf." mnemonic ".d reg/reg/reg")
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((MACH ORFPX64-MACHS))
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(.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
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(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
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(set DF rDDF (mnemonic DF rADF rBDF))
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()
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)
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(dni (.sym lf- mnemonic -d32)
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(.str "lf." mnemonic ".d regpair/regpair/regpair")
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((MACH ORFPX64A32-MACHS))
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@ -185,15 +173,6 @@
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()
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)
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(dni lf-rem-d
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"lf.rem.d reg/reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.rem.d $rDDF,$rADF,$rBDF"
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(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
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(set DF rDDF (rem DF rADF rBDF))
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()
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)
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(dni lf-rem-d32
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"lf.rem.d regpair/regpair/regpair"
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((MACH ORFPX64A32-MACHS))
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@ -221,15 +200,6 @@
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()
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)
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(dni lf-itof-d
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"lf.itof.d reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.itof.d $rDDF,$rA"
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(+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
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(set DF rDDF (float DF (get-rounding-mode) rA))
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()
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)
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(dni lf-itof-d32
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"lf.itof.d regpair/regpair"
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((MACH ORFPX64A32-MACHS))
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@ -248,15 +218,6 @@
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()
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)
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(dni lf-ftoi-d
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"lf.ftoi.d reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.ftoi.d $rD,$rADF"
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(+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
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(set WI rD (fix WI (get-rounding-mode) rADF))
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()
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)
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(dni lf-ftoi-d32
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"lf.ftoi.d regpair/regpair"
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((MACH ORFPX64A32-MACHS))
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@ -276,14 +237,6 @@
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(symantics rtx-mnemonic SF rASF rBSF)
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()
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)
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(dni (.sym lf-sf mnemonic -d)
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(.str "lf.sf" mnemonic ".d reg/reg")
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((MACH ORFPX64-MACHS))
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(.str "lf.sf" mnemonic ".d $rADF,$rBDF")
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(+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
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(symantics rtx-mnemonic DF rADF rBDF)
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()
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)
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(dni (.sym lf-sf mnemonic -d32)
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(.str "lf.sf" mnemonic ".d regpair/regpair")
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((MACH ORFPX64A32-MACHS))
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@ -336,15 +289,6 @@
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()
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)
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(dni lf-madd-d
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"lf.madd.d reg/reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.madd.d $rDDF,$rADF,$rBDF"
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(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
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(set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
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()
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)
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(dni lf-madd-d32
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"lf.madd.d regpair/regpair/regpair"
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((MACH ORFPX64A32-MACHS))
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@ -364,14 +308,6 @@
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(nop)
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()
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)
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(dni (.sym "lf-cust" cust-num "-d")
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(.str "lf.cust" cust-num ".d")
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((MACH ORFPX64-MACHS))
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(.str "lf.cust" cust-num ".d")
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(+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
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(nop)
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()
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)
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(dni (.sym "lf-cust" cust-num "-d32")
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(.str "lf.cust" cust-num ".d")
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((MACH ORFPX64A32-MACHS))
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