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Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."

Browse Source 
This reverts commit a914a7c958.
This commit is contained in:
Igor Tsimbalist 2018-04-27 14:34:13 +02:00
parent ffa389a396
commit aa17843739
21 changed files with 15097 additions and 15508 deletions
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18
gas/ChangeLog
View File

@ -1,21 +1,3 @@
2018-04-26 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New test.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
2018-04-26 Nick Clifton <nickc@redhat.com>
* as.c (flag_generate_build_notes): New variable.

40
gas/config/tc-i386.c
View File

@ -1029,10 +1029,6 @@ static const arch_entry cpu_arch[] =
CPU_WAITPKG_FLAGS, 0 },
{ STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
CPU_CLDEMOTE_FLAGS, 0 },
{ STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
CPU_MOVDIRI_FLAGS, 0 },
{ STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
CPU_MOVDIR64B_FLAGS, 0 },
};
static const noarch_entry cpu_noarch[] =
@ -1068,8 +1064,6 @@ static const noarch_entry cpu_noarch[] =
{ STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
{ STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
{ STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
{ STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
{ STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
};
#ifdef I386COFF
@ -6046,40 +6040,6 @@ process_suffix (void)
break;
}
if (i.tm.opcode_modifier.addrprefixopreg
&& i.reg_operands != 0
&& i.operands > 1)
{
/* Check invalid register operand when the address size override
prefix changes the size of register operands. */
unsigned int op;
enum { need_word, need_dword, need_qword } need;
if (flag_code == CODE_32BIT)
need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
else
{
if (i.prefix[ADDR_PREFIX])
need = need_dword;
else
need = flag_code == CODE_64BIT ? need_qword : need_word;
}
for (op = 0; op < i.operands; op++)
if (i.types[op].bitfield.reg
&& ((need == need_word
&& !i.op[op].regs->reg_type.bitfield.word)
|| (need == need_dword
&& !i.op[op].regs->reg_type.bitfield.dword)
|| (need == need_qword
&& !i.op[op].regs->reg_type.bitfield.qword)))
{
as_bad (_("invalid register operand size for `%s'"),
i.tm.name);
return 0;
}
}
return 1;
}

3
gas/doc/c-i386.texi
View File

@ -176,8 +176,6 @@ accept various extension mnemonics. For example,
@code{clflushopt},
@code{se1},
@code{clwb},
@code{movdiri},
@code{movdir64b},
@code{avx512f},
@code{avx512cd},
@code{avx512er},
@ -1278,7 +1276,6 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}

6
gas/testsuite/gas/i386/i386.exp
View File

@ -431,9 +431,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "waitpkg-intel"
run_dump_test "cldemote"
run_dump_test "cldemote-intel"
run_dump_test "movdir"
run_dump_test "movdir-intel"
run_list_test "movdir64b-reg"
run_list_test "avx512vl-1" "-al"
run_list_test "avx512vl-2" "-al"
run_list_test "avx512vl-plain" "-al"
@ -927,9 +924,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-waitpkg-intel"
run_dump_test "x86-64-cldemote"
run_dump_test "x86-64-cldemote-intel"
run_dump_test "x86-64-movdir"
run_dump_test "x86-64-movdir-intel"
run_list_test "x86-64-movdir64b-reg"
run_dump_test "x86-64-fence-as-lock-add-yes"
run_dump_test "x86-64-fence-as-lock-add-no"
run_dump_test "x86-64-pr20141"

18
gas/testsuite/gas/i386/movdir-intel.d
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@ -1,18 +0,0 @@
#as:
#objdump: -dw -Mintel
#name: i386 MOVDIR[I,64B] insns (Intel disassembly)
#source: movdir.s
.*: +file format .*
Disassembly of section \.text:
00000000 <_start>:
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri DWORD PTR \[ecx\],eax
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b eax,\[ecx\]
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 04[ ]*movdir64b ax,\[si\]
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri DWORD PTR \[ecx\],eax
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b eax,\[ecx\]
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 04[ ]*movdir64b ax,\[si\]
#pass

18
gas/testsuite/gas/i386/movdir.d
View File

@ -1,18 +0,0 @@
#as:
#objdump: -dw
#name: i386 MOVDIR[I,64B] insns
#source: movdir.s
.*: +file format .*
Disassembly of section \.text:
00000000 <_start>:
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri %eax,\(%ecx\)
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b \(%ecx\),%eax
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 04[ ]*movdir64b \(%si\),%ax
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri %eax,\(%ecx\)
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b \(%ecx\),%eax
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 04[ ]*movdir64b \(%si\),%ax
#pass

13
gas/testsuite/gas/i386/movdir.s
View File

@ -1,13 +0,0 @@
# Check MOVDIR[I,64B] 32-bit instructions
.allow_index_reg
.text
_start:
movdiri %eax, (%ecx)
movdir64b (%ecx),%eax
movdir64b (%si),%ax
.intel_syntax noprefix
movdiri [ecx], eax
movdir64b eax,[ecx]
movdir64b ax,[si]

5
gas/testsuite/gas/i386/movdir64b-reg.l
View File

@ -1,5 +0,0 @@
.*: Assembler messages:
.*:6: Error: invalid register operand size for `movdir64b'
.*:7: Error: invalid register operand size for `movdir64b'
.*:10: Error: invalid register operand size for `movdir64b'
.*:11: Error: invalid register operand size for `movdir64b'

11
gas/testsuite/gas/i386/movdir64b-reg.s
View File

@ -1,11 +0,0 @@
# Check error for MOVDIR64B 32-bit instructions
.allow_index_reg
.text
_start:
movdir64b (%si),%eax
movdir64b (%esi),%ax
.intel_syntax noprefix
movdir64b eax,[si]
movdir64b ax,[esi]

18
gas/testsuite/gas/i386/x86-64-movdir-intel.d
View File

@ -1,18 +0,0 @@
#as:
#objdump: -dw -Mintel
#name: x86_64 MOVDIR[I,64B] insns (Intel disassembly)
#source: x86-64-movdir.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*48 0f 38 f9 01[ ]*rex\.W movdiri QWORD PTR \[rcx\],rax
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b rax,\[rcx\]
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b eax,\[ecx]
[ ]*[a-f0-9]+:[ ]*48 0f 38 f9 01[ ]*rex\.W movdiri QWORD PTR \[rcx\],rax
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b rax,\[rcx\]
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b eax,\[ecx\]
#pass

18
gas/testsuite/gas/i386/x86-64-movdir.d
View File

@ -1,18 +0,0 @@
#as:
#objdump: -dw
#name: x86_64 MOVDIR[I,64B] insns
#source: x86-64-movdir.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*48 0f 38 f9 01[ ]*rex\.W movdiri %rax,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b \(%rcx\),%rax
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b \(%ecx\),%eax
[ ]*[a-f0-9]+:[ ]*48 0f 38 f9 01[ ]*rex\.W movdiri %rax,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b \(%rcx\),%rax
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b \(%ecx\),%eax
#pass

13
gas/testsuite/gas/i386/x86-64-movdir.s
View File

@ -1,13 +0,0 @@
# Check MOVDIR[I,64B] 64-bit instructions
.allow_index_reg
.text
_start:
movdiri %rax, (%rcx)
movdir64b (%rcx),%rax
movdir64b (%ecx),%eax
.intel_syntax noprefix
movdiri [rcx],rax
movdir64b rax,[rcx]
movdir64b eax,[ecx]

5
gas/testsuite/gas/i386/x86-64-movdir64b-reg.l
View File

@ -1,5 +0,0 @@
.*: Assembler messages:
.*:6: Error: invalid register operand size for `movdir64b'
.*:7: Error: invalid register operand size for `movdir64b'
.*:10: Error: invalid register operand size for `movdir64b'
.*:11: Error: invalid register operand size for `movdir64b'

11
gas/testsuite/gas/i386/x86-64-movdir64b-reg.s
View File

@ -1,11 +0,0 @@
# Check error for MOVDIR64B 32-bit instructions
.allow_index_reg
.text
_start:
movdir64b (%esi),%rax
movdir64b (%rsi),%eax
.intel_syntax noprefix
movdir64b rax,[esi]
movdir64b eax,[rsi]

18
opcodes/ChangeLog
View File

@ -1,21 +1,3 @@
2018-04-26 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
Add Gva macro and handle in OP_G.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Likewise.
(opcode_modifiers): Add AddrPrefixOpReg.
(i386_opcode_modifier): Likewise.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-04-26 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Fold various non-memory operand AVX512VL

54
opcodes/i386-dis.c
View File

@ -281,7 +281,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Gd { OP_G, d_mode }
#define Gdq { OP_G, dq_mode }
#define Gm { OP_G, m_mode }
#define Gva { OP_G, va_mode }
#define Gw { OP_G, w_mode }
#define Rd { OP_R, d_mode }
#define Rdq { OP_R, dq_mode }
@ -836,8 +835,6 @@ enum
MOD_0F382A_PREFIX_2,
MOD_0F38F5_PREFIX_2,
MOD_0F38F6_PREFIX_0,
MOD_0F38F8_PREFIX_2,
MOD_0F38F9_PREFIX_0,
MOD_62_32BIT,
MOD_C4_32BIT,
MOD_C5_32BIT,
@ -1084,8 +1081,6 @@ enum
PREFIX_0F38F1,
PREFIX_0F38F5,
PREFIX_0F38F6,
PREFIX_0F38F8,
PREFIX_0F38F9,
PREFIX_0F3A08,
PREFIX_0F3A09,
PREFIX_0F3A0A,
@ -4685,18 +4680,6 @@ static const struct dis386 prefix_table[][4] = {
{ Bad_Opcode },
},
/* PREFIX_0F38F8 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ MOD_TABLE (MOD_0F38F8_PREFIX_2) },
},
/* PREFIX_0F38F9 */
{
{ MOD_TABLE (MOD_0F38F9_PREFIX_0) },
},
/* PREFIX_0F3A08 */
{
{ Bad_Opcode },
@ -7461,8 +7444,8 @@ static const struct dis386 three_byte_table[][256] = {
{ PREFIX_TABLE (PREFIX_0F38F6) },
{ Bad_Opcode },
/* f8 */
{ PREFIX_TABLE (PREFIX_0F38F8) },
{ PREFIX_TABLE (PREFIX_0F38F9) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@ -11853,14 +11836,6 @@ static const struct dis386 mod_table[][2] = {
/* MOD_0F38F6_PREFIX_0 */
{ "wrssK", { M, Gdq }, PREFIX_OPCODE },
},
{
/* MOD_0F38F8_PREFIX_2 */
{ "movdir64b", { Gva, M }, PREFIX_OPCODE },
},
{
/* MOD_0F38F9_PREFIX_0 */
{ "movdiri", { Em, Gm }, PREFIX_OPCODE },
},
{
/* MOD_62_32BIT */
{ "bound{S|}", { Gv, Ma }, 0 },
@ -15177,10 +15152,8 @@ OP_E_register (int bytemode, int sizeflag)
names = (address_mode == mode_64bit
? names64 : names32);
if (!(prefixes & PREFIX_ADDR))
{
if (address_mode == mode_16bit)
names = names16;
}
names = (address_mode == mode_16bit
? names16 : names);
else
{
/* Remove "addr16/addr32". */
@ -15679,7 +15652,6 @@ static void
OP_G (int bytemode, int sizeflag)
{
int add = 0;
const char **names;
USED_REX (REX_R);
if (rex & REX_R)
add += 8;
@ -15728,24 +15700,6 @@ OP_G (int bytemode, int sizeflag)
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
case va_mode:
names = (address_mode == mode_64bit
? names64 : names32);
if (!(prefixes & PREFIX_ADDR))
{
if (address_mode == mode_16bit)
names = names16;
}
else
{
/* Remove "addr16/addr32". */
all_prefixes[last_addr_prefix] = 0;
names = (address_mode != mode_32bit
? names32 : names16);
used_prefixes |= PREFIX_ADDR;
}
oappend (names[modrm.reg + add]);
break;
case m_mode:
if (address_mode == mode_64bit)
oappend (names64[modrm.reg + add]);

16
opcodes/i386-gen.c
View File

@ -283,10 +283,6 @@ static initializer cpu_flag_init[] =
"CpuWAITPKG" },
{ "CPU_CLDEMOTE_FLAGS",
"CpuCLDEMOTE" },
{ "CPU_MOVDIRI_FLAGS",
"CpuMOVDIRI" },
{ "CPU_MOVDIR64B_FLAGS",
"CpuMOVDIR64B" },
{ "CPU_ANY_X87_FLAGS",
"CPU_ANY_287_FLAGS|Cpu8087" },
{ "CPU_ANY_287_FLAGS",
@ -347,10 +343,6 @@ static initializer cpu_flag_init[] =
"CpuAVX512_VNNI" },
{ "CPU_ANY_AVX512_BITALG_FLAGS",
"CpuAVX512_BITALG" },
{ "CPU_ANY_MOVDIRI_FLAGS",
"CpuMOVDIRI" },
{ "CPU_ANY_MOVDIR64B_FLAGS",
"CpuMOVDIR64B" },
};
static const initializer operand_type_shorthands[] =
@ -585,13 +577,6 @@ static bitfield cpu_flags[] =
BITFIELD (CpuPCONFIG),
BITFIELD (CpuWAITPKG),
BITFIELD (CpuCLDEMOTE),
BITFIELD (CpuMOVDIRI),
BITFIELD (CpuMOVDIR64B),
BITFIELD (CpuRegMMX),
BITFIELD (CpuRegXMM),
BITFIELD (CpuRegYMM),
BITFIELD (CpuRegZMM),
BITFIELD (CpuRegMask),
#ifdef CpuUnused
BITFIELD (CpuUnused),
#endif
@ -634,7 +619,6 @@ static bitfield opcode_modifiers[] =
BITFIELD (ToDword),
BITFIELD (ToQword),
BITFIELD (AddrPrefixOp0),
BITFIELD (AddrPrefixOpReg),
BITFIELD (IsPrefix),
BITFIELD (ImmExt),
BITFIELD (NoRex64),

334
opcodes/i386-init.h
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File diff suppressed because it is too large Load Diff

24
opcodes/i386-opc.h
View File

@ -231,20 +231,6 @@ enum
CpuWAITPKG,
/* CLDEMOTE instruction required */
CpuCLDEMOTE,
/* MOVDIRI instruction support required */
CpuMOVDIRI,
/* MOVDIRR64B instruction required */
CpuMOVDIR64B,
/* MMX register support required */
CpuRegMMX,
/* XMM register support required */
CpuRegXMM,
/* YMM register support required */
CpuRegYMM,
/* ZMM register support required */
CpuRegZMM,
/* Mask register support required */
CpuRegMask,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
@ -368,13 +354,6 @@ typedef union i386_cpu_flags
unsigned int cpupconfig:1;
unsigned int cpuwaitpkg:1;
unsigned int cpucldemote:1;
unsigned int cpumovdiri:1;
unsigned int cpumovdir64b:1;
unsigned int cpuregmmx:1;
unsigned int cpuregxmm:1;
unsigned int cpuregymm:1;
unsigned int cpuregzmm:1;
unsigned int cpuregmask:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
@ -468,8 +447,6 @@ enum
ToQword,
/* Address prefix changes operand 0 */
AddrPrefixOp0,
/* Address prefix changes register operand */
AddrPrefixOpReg,
/* opcode is a prefix */
IsPrefix,
/* instruction has extension in 8 bit imm */
@ -651,7 +628,6 @@ typedef struct i386_opcode_modifier
unsigned int todword:1;
unsigned int toqword:1;
unsigned int addrprefixop0:1;
unsigned int addrprefixopreg:1;
unsigned int isprefix:1;
unsigned int immext:1;
unsigned int norex64:1;

10
opcodes/i386-opc.tbl
View File

@ -5829,13 +5829,3 @@ umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
cldemote, 1, 0x0f1c, 0x0, 2, CpuCLDEMOTE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
// CLDEMOTE instructions end.
// MOVDIR[I,64B] instructions.
movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI|Cpu64, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Unspecified|ZMMword|BaseIndex|Disp8|Disp32|Disp32S, Reg16|Reg32 }
movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|ZMMword|BaseIndex|Disp8|Disp32|Disp32S, Reg32|Reg64 }
// MOVEDIR instructions end.

29952
opcodes/i386-tbl.h
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File diff suppressed because it is too large Load Diff