mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-25 11:04:18 +08:00
2010-02-10 Quentin Neill <quentin.neill@amd.com>
Sebastian Pop <sebastian.pop@amd.com>
gas:
* config/tc-i386.c (vec_imm4) New operand type.
(fits_in_imm4): New.
(VEX_check_operands): New.
(check_reverse): Call VEX_check_operands.
(build_modrm_byte): Reintroduce code for 5
operand insns. Fix whitespace.
gas/testsuite:
* gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
* gas/i386/x86-64-xop.s: Likewise.
* gas/i386/xop.d: Likewise.
* gas/i386/xop.s: Likewise.
opcodes:
* i386-dis.c (OP_EX_VexImmW): Reintroduced
function to handle 5th imm8 operand.
(PREFIX_VEX_3A48): Added.
(PREFIX_VEX_3A49): Added.
(VEX_W_3A48_P_2): Added.
(VEX_W_3A49_P_2): Added.
(prefix table): Added entries for PREFIX_VEX_3A48
and PREFIX_VEX_3A49.
(vex table): Added entries for VEX_W_3A48_P_2 and
and VEX_W_3A49_P_2.
* i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
for Vec_Imm4 operands.
* i386-opc.h (enum): Added Vec_Imm4.
(i386_operand_type): Added vec_imm4.
* i386-opc.tbl: Add entries for vpermilp[ds].
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
This commit is contained in:
Sebastian Pop
parent
e543c8cb70
commit
a683cc34e4
@ -1,3 +1,13 @@
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2010-02-10 Quentin Neill <quentin.neill@amd.com>
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Sebastian Pop <sebastian.pop@amd.com>
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* config/tc-i386.c (vec_imm4) New operand type.
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(fits_in_imm4): New.
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(VEX_check_operands): New.
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(check_reverse): Call VEX_check_operands.
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(build_modrm_byte): Reintroduce code for 5
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operand insns. Fix whitespace.
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2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
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* config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x,
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@ -1436,6 +1436,7 @@ static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
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static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
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static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
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static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
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static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
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enum operand_type
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{
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@ -1711,6 +1712,12 @@ fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
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#endif
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} /* fits_in_unsigned_long() */
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static INLINE int
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fits_in_imm4 (offsetT num)
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{
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return (num & 0xf) == num;
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}
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static i386_operand_type
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smallest_imm_type (offsetT num)
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{
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@ -3724,6 +3731,29 @@ optimize_disp (void)
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}
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}
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/* Check if operands are valid for the instrucrtion. Update VEX
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operand types. */
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static int
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VEX_check_operands (const insn_template *t)
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{
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if (!t->opcode_modifier.vex)
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return 0;
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/* Only check VEX_Imm4, which must be the first operand. */
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if (t->operand_types[0].bitfield.vec_imm4)
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{
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if (i.op[0].imms->X_op != O_constant
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|| !fits_in_imm4 (i.op[0].imms->X_add_number))
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return 1;
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/* Turn off Imm8 so that update_imm won't complain. */
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i.types[0] = vec_imm4;
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}
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return 0;
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}
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static const insn_template *
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match_template (void)
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{
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@ -4028,6 +4058,10 @@ check_reverse:
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continue;
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}
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/* Check if VEX operands are valid. */
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if (VEX_check_operands (t))
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continue;
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/* We've found a match; break out of loop. */
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break;
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}
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@ -4960,53 +4994,119 @@ build_modrm_byte (void)
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expressionS *exp;
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if (i.tm.opcode_modifier.veximmext
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&& i.tm.opcode_modifier.immext)
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{
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dest = i.operands - 2;
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gas_assert (dest == 3);
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}
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&& i.tm.opcode_modifier.immext)
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{
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dest = i.operands - 2;
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gas_assert (dest == 3);
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}
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else
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dest = i.operands - 1;
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dest = i.operands - 1;
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nds = dest - 1;
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/* This instruction must have 4 register operands
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or 3 register operands plus 1 memory operand.
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It must have VexNDS and VexImmExt. */
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/* There are 2 kinds of instructions:
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1. 5 operands: 4 register operands or 3 register operands
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plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
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VexW0 or VexW1. The destination must be either XMM or YMM
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register.
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2. 4 operands: 4 register operands or 3 register operands
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plus 1 memory operand, VexXDS, and VexImmExt */
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gas_assert ((i.reg_operands == 4
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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&& i.tm.opcode_modifier.vexvvvv == VEXXDS
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&& i.tm.opcode_modifier.veximmext
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&& (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[dest], ®ymm)));
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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&& i.tm.opcode_modifier.vexvvvv == VEXXDS
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&& (i.tm.opcode_modifier.veximmext
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|| (i.imm_operands == 1
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&& i.types[0].bitfield.vec_imm4
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&& (i.tm.opcode_modifier.vexw == VEXW0
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|| i.tm.opcode_modifier.vexw == VEXW1)
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&& (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[dest], ®ymm)))));
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/* Generate an 8bit immediate operand to encode the register
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operand. */
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exp = &im_expressions[i.imm_operands++];
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i.op[i.operands].imms = exp;
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i.types[i.operands] = imm8;
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i.operands++;
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/* If VexW1 is set, the first operand is the source and
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the second operand is encoded in the immediate operand. */
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if (i.tm.opcode_modifier.vexw == VEXW1)
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{
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source = 0;
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reg_slot = 1;
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}
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if (i.imm_operands == 0)
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{
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/* When there is no immediate operand, generate an 8bit
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immediate operand to encode the first operand. */
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exp = &im_expressions[i.imm_operands++];
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i.op[i.operands].imms = exp;
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i.types[i.operands] = imm8;
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i.operands++;
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/* If VexW1 is set, the first operand is the source and
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the second operand is encoded in the immediate operand. */
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if (i.tm.opcode_modifier.vexw == VEXW1)
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{
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source = 0;
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reg_slot = 1;
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}
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else
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{
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source = 1;
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reg_slot = 0;
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}
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/* FMA swaps REG and NDS. */
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if (i.tm.cpu_flags.bitfield.cpufma)
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{
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unsigned int tmp;
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tmp = reg_slot;
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reg_slot = nds;
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nds = tmp;
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}
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gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[reg_slot],
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®ymm));
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exp->X_op = O_constant;
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exp->X_add_number
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= ((i.op[reg_slot].regs->reg_num
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+ ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
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}
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else
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{
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source = 1;
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reg_slot = 0;
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}
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gas_assert ((operand_type_equal (&i.tm.operand_types[reg_slot], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[reg_slot],
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®ymm))
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&& (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[nds],
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®ymm)));
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exp->X_op = O_constant;
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exp->X_add_number
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= ((i.op[reg_slot].regs->reg_num
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+ ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
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{
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unsigned int imm_slot;
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if (i.tm.opcode_modifier.vexw == VEXW0)
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{
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/* If VexW0 is set, the third operand is the source and
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the second operand is encoded in the immediate
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operand. */
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source = 2;
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reg_slot = 1;
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}
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else
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{
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/* VexW1 is set, the second operand is the source and
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the third operand is encoded in the immediate
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operand. */
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source = 1;
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reg_slot = 2;
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}
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if (i.tm.opcode_modifier.immext)
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{
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/* When ImmExt is set, the immdiate byte is the last
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operand. */
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imm_slot = i.operands - 1;
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source--;
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reg_slot--;
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}
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else
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{
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imm_slot = 0;
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/* Turn on Imm8 so that output_imm will generate it. */
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i.types[imm_slot].bitfield.imm8 = 1;
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}
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gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[reg_slot],
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®ymm));
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i.op[imm_slot].imms->X_add_number
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|= ((i.op[reg_slot].regs->reg_num
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+ ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
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}
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gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
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|| operand_type_equal (&i.tm.operand_types[nds],
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®ymm));
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i.vex.register_specifier = i.op[nds].regs;
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}
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else
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@ -1,3 +1,11 @@
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2010-02-10 Quentin Neill <quentin.neill@amd.com>
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Sebastian Pop <sebastian.pop@amd.com>
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* gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
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* gas/i386/x86-64-xop.s: Likewise.
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* gas/i386/xop.d: Likewise.
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* gas/i386/xop.s: Likewise.
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2010-02-08 Christophe Lyon <christophe.lyon@st.com>
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* gas/arm/branch-reloc.s, gas/arm/branch-reloc.d,
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@ -294,6 +294,70 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 8f 68 78 cd f8 03[ ]+vpcomw \$0x3,%xmm0,%xmm0,%xmm15
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[ ]*[a-f0-9]+: 8f e8 20 cd 01 ff[ ]+vpcomw \$0xff,\(%rcx\),%xmm11,%xmm0
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[ ]*[a-f0-9]+: 8f e8 00 cd 0e 03[ ]+vpcomw \$0x3,\(%rsi\),%xmm15,%xmm1
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[ ]*[a-f0-9]+: c4 43 21 49 d5 e3[ ]+vpermil2pd \$0x3,%xmm14,%xmm13,%xmm11,%xmm10
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[ ]*[a-f0-9]+: c4 a3 71 49 04 07 f2[ ]+vpermil2pd \$0x2,%xmm15,\(%rdi,%r8,1\),%xmm1,%xmm0
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[ ]*[a-f0-9]+: c4 83 79 49 54 e4 23 01[ ]+vpermil2pd \$0x1,%xmm0,0x23\(%r12,%r12,8\),%xmm0,%xmm2
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[ ]*[a-f0-9]+: c4 c3 11 49 d7 30[ ]+vpermil2pd \$0x0,%xmm3,%xmm15,%xmm13,%xmm2
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[ ]*[a-f0-9]+: c4 c3 21 49 c6 32[ ]+vpermil2pd \$0x2,%xmm3,%xmm14,%xmm11,%xmm0
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[ ]*[a-f0-9]+: c4 e3 71 49 02 01[ ]+vpermil2pd \$0x1,%xmm0,\(%rdx\),%xmm1,%xmm0
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[ ]*[a-f0-9]+: c4 63 79 49 c8 33[ ]+vpermil2pd \$0x3,%xmm3,%xmm0,%xmm0,%xmm9
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[ ]*[a-f0-9]+: c4 83 79 49 5c e4 23 20[ ]+vpermil2pd \$0x0,%xmm2,0x23\(%r12,%r12,8\),%xmm0,%xmm3
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[ ]*[a-f0-9]+: c4 e3 21 49 c7 00[ ]+vpermil2pd \$0x0,%xmm0,%xmm7,%xmm11,%xmm0
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[ ]*[a-f0-9]+: c4 e3 01 49 c5 41[ ]+vpermil2pd \$0x1,%xmm4,%xmm5,%xmm15,%xmm0
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[ ]*[a-f0-9]+: c4 43 f9 49 54 9c 04 83[ ]+vpermil2pd \$0x3,0x4\(%r12,%rbx,4\),%xmm8,%xmm0,%xmm10
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[ ]*[a-f0-9]+: c4 e3 41 49 f0 12[ ]+vpermil2pd \$0x2,%xmm1,%xmm0,%xmm7,%xmm6
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[ ]*[a-f0-9]+: c4 43 c9 49 54 1d 00 c1[ ]+vpermil2pd \$0x1,0x0\(%r13,%rbx,1\),%xmm12,%xmm6,%xmm10
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[ ]*[a-f0-9]+: c4 63 79 49 ce 42[ ]+vpermil2pd \$0x2,%xmm4,%xmm6,%xmm0,%xmm9
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[ ]*[a-f0-9]+: c4 63 c9 49 1c db 80[ ]+vpermil2pd \$0x0,\(%rbx,%rbx,8\),%xmm8,%xmm6,%xmm11
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[ ]*[a-f0-9]+: c4 c3 49 49 c5 53[ ]+vpermil2pd \$0x3,%xmm5,%xmm13,%xmm6,%xmm0
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[ ]*[a-f0-9]+: c4 63 7d 49 ed 71[ ]+vpermil2pd \$0x1,%ymm7,%ymm5,%ymm0,%ymm13
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[ ]*[a-f0-9]+: c4 23 5d 49 24 49 70[ ]+vpermil2pd \$0x0,%ymm7,\(%rcx,%r9,2\),%ymm4,%ymm12
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[ ]*[a-f0-9]+: c4 03 7d 49 04 1e 33[ ]+vpermil2pd \$0x3,%ymm3,\(%r14,%r11,1\),%ymm0,%ymm8
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[ ]*[a-f0-9]+: c4 43 7d 49 8c 81 07 01 00 00 72[ ]+vpermil2pd \$0x2,%ymm7,0x107\(%r9,%rax,4\),%ymm0,%ymm9
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[ ]*[a-f0-9]+: c4 03 7d 49 04 1e 72[ ]+vpermil2pd \$0x2,%ymm7,\(%r14,%r11,1\),%ymm0,%ymm8
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[ ]*[a-f0-9]+: c4 a3 5d 49 04 49 03[ ]+vpermil2pd \$0x3,%ymm0,\(%rcx,%r9,2\),%ymm4,%ymm0
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[ ]*[a-f0-9]+: c4 83 25 49 2c 1e 81[ ]+vpermil2pd \$0x1,%ymm8,\(%r14,%r11,1\),%ymm11,%ymm5
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[ ]*[a-f0-9]+: c4 63 7d 49 2e 20[ ]+vpermil2pd \$0x0,%ymm2,\(%rsi\),%ymm0,%ymm13
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[ ]*[a-f0-9]+: c4 63 ad 49 3c 31 01[ ]+vpermil2pd \$0x1,\(%rcx,%rsi,1\),%ymm0,%ymm10,%ymm15
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[ ]*[a-f0-9]+: c4 c3 fd 49 01 c2[ ]+vpermil2pd \$0x2,\(%r9\),%ymm12,%ymm0,%ymm0
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[ ]*[a-f0-9]+: c4 a3 a5 49 a4 31 d9 d8 15 00 80[ ]+vpermil2pd \$0x0,0x15d8d9\(%rcx,%r14,1\),%ymm8,%ymm11,%ymm4
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[ ]*[a-f0-9]+: c4 c3 7d 49 c4 93[ ]+vpermil2pd \$0x3,%ymm9,%ymm12,%ymm0,%ymm0
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[ ]*[a-f0-9]+: c4 03 8d 49 44 1d 00 13[ ]+vpermil2pd \$0x3,0x0\(%r13,%r11,1\),%ymm1,%ymm14,%ymm8
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[ ]*[a-f0-9]+: c4 23 fd 49 9c 31 d9 d8 15 00 00[ ]+vpermil2pd \$0x0,0x15d8d9\(%rcx,%r14,1\),%ymm0,%ymm0,%ymm11
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[ ]*[a-f0-9]+: c4 83 85 49 44 1d 00 11[ ]+vpermil2pd \$0x1,0x0\(%r13,%r11,1\),%ymm1,%ymm15,%ymm0
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[ ]*[a-f0-9]+: c4 c3 25 49 ed 92[ ]+vpermil2pd \$0x2,%ymm9,%ymm13,%ymm11,%ymm5
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[ ]*[a-f0-9]+: c4 03 79 48 7c e4 23 02[ ]+vpermil2ps \$0x2,%xmm0,0x23\(%r12,%r12,8\),%xmm0,%xmm15
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[ ]*[a-f0-9]+: c4 03 61 48 4c e4 23 00[ ]+vpermil2ps \$0x0,%xmm0,0x23\(%r12,%r12,8\),%xmm3,%xmm9
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[ ]*[a-f0-9]+: c4 43 41 48 dc 03[ ]+vpermil2ps \$0x3,%xmm0,%xmm12,%xmm7,%xmm11
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[ ]*[a-f0-9]+: c4 e3 79 48 02 31[ ]+vpermil2ps \$0x1,%xmm3,\(%rdx\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 83 79 48 04 0e 32[ ]+vpermil2ps \$0x2,%xmm3,\(%r14,%r9,1\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 71 48 02 31[ ]+vpermil2ps \$0x1,%xmm3,\(%rdx\),%xmm1,%xmm0
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[ ]*[a-f0-9]+: c4 43 79 48 e0 30[ ]+vpermil2ps \$0x0,%xmm3,%xmm8,%xmm0,%xmm12
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[ ]*[a-f0-9]+: c4 83 71 48 14 0e 33[ ]+vpermil2ps \$0x3,%xmm3,\(%r14,%r9,1\),%xmm1,%xmm2
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[ ]*[a-f0-9]+: c4 43 f9 48 5c 05 00 01[ ]+vpermil2ps \$0x1,0x0\(%r13,%rax,1\),%xmm0,%xmm0,%xmm11
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[ ]*[a-f0-9]+: c4 63 c9 48 17 f3[ ]+vpermil2ps \$0x3,\(%rdi\),%xmm15,%xmm6,%xmm10
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[ ]*[a-f0-9]+: c4 c3 79 48 c5 02[ ]+vpermil2ps \$0x2,%xmm0,%xmm13,%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 63 09 48 d0 40[ ]+vpermil2ps \$0x0,%xmm4,%xmm0,%xmm14,%xmm10
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[ ]*[a-f0-9]+: c4 63 61 48 d8 01[ ]+vpermil2ps \$0x1,%xmm0,%xmm0,%xmm3,%xmm11
|
||||
[ ]*[a-f0-9]+: c4 63 c9 48 14 db b2[ ]+vpermil2ps \$0x2,\(%rbx,%rbx,8\),%xmm11,%xmm6,%xmm10
|
||||
[ ]*[a-f0-9]+: c4 63 49 48 fd 43[ ]+vpermil2ps \$0x3,%xmm4,%xmm5,%xmm6,%xmm15
|
||||
[ ]*[a-f0-9]+: c4 43 f9 48 54 9c 04 00[ ]+vpermil2ps \$0x0,0x4\(%r12,%rbx,4\),%xmm0,%xmm0,%xmm10
|
||||
[ ]*[a-f0-9]+: c4 e3 7d 48 06 01[ ]+vpermil2ps \$0x1,%ymm0,\(%rsi\),%ymm0,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 c3 25 48 84 81 07 01 00 00 f2[ ]+vpermil2ps \$0x2,%ymm15,0x107\(%r9,%rax,4\),%ymm11,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 5d 48 c0 70[ ]+vpermil2ps \$0x0,%ymm7,%ymm0,%ymm4,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 23 5d 48 3c 49 73[ ]+vpermil2ps \$0x3,%ymm7,\(%rcx,%r9,2\),%ymm4,%ymm15
|
||||
[ ]*[a-f0-9]+: c4 63 5d 48 f8 02[ ]+vpermil2ps \$0x2,%ymm0,%ymm0,%ymm4,%ymm15
|
||||
[ ]*[a-f0-9]+: c4 43 05 48 ac 81 07 01 00 00 03[ ]+vpermil2ps \$0x3,%ymm0,0x107\(%r9,%rax,4\),%ymm15,%ymm13
|
||||
[ ]*[a-f0-9]+: c4 43 0d 48 e8 70[ ]+vpermil2ps \$0x0,%ymm7,%ymm8,%ymm14,%ymm13
|
||||
[ ]*[a-f0-9]+: c4 43 5d 48 ef 71[ ]+vpermil2ps \$0x1,%ymm7,%ymm15,%ymm4,%ymm13
|
||||
[ ]*[a-f0-9]+: c4 23 fd 48 bc 31 d9 d8 15 00 00[ ]+vpermil2ps \$0x0,0x15d8d9\(%rcx,%r14,1\),%ymm0,%ymm0,%ymm15
|
||||
[ ]*[a-f0-9]+: c4 83 85 48 64 1d 00 c3[ ]+vpermil2ps \$0x3,0x0\(%r13,%r11,1\),%ymm12,%ymm15,%ymm4
|
||||
[ ]*[a-f0-9]+: c4 a3 fd 48 84 31 d9 d8 15 00 02[ ]+vpermil2ps \$0x2,0x15d8d9\(%rcx,%r14,1\),%ymm0,%ymm0,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 65 48 e2 01[ ]+vpermil2ps \$0x1,%ymm0,%ymm2,%ymm3,%ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 fd 48 24 31 c3[ ]+vpermil2ps \$0x3,\(%rcx,%rsi,1\),%ymm12,%ymm0,%ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 fd 48 24 31 12[ ]+vpermil2ps \$0x2,\(%rcx,%rsi,1\),%ymm1,%ymm0,%ymm4
|
||||
[ ]*[a-f0-9]+: c4 83 fd 48 64 1d 00 00[ ]+vpermil2ps \$0x0,0x0\(%r13,%r11,1\),%ymm0,%ymm0,%ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 5d 48 c7 81[ ]+vpermil2ps \$0x1,%ymm8,%ymm7,%ymm4,%ymm0
|
||||
[ ]*[a-f0-9]+: 8f 69 78 c2 fa[ ]+vphaddbd %xmm2,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 69 78 c2 e0[ ]+vphaddbd %xmm0,%xmm12
|
||||
[ ]*[a-f0-9]+: 8f c9 78 c2 04 24[ ]+vphaddbd \(%r12\),%xmm0
|
||||
|
||||
@ -310,6 +310,78 @@ _start:
|
||||
VPCOMW $0x3,%xmm0,%xmm0,%xmm15
|
||||
VPCOMW $0xFF,(%rcx),%xmm11,%xmm0
|
||||
VPCOMW $0x3,(%rsi),%xmm15,%xmm1
|
||||
# Testing VPERMIL2PD imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PD $0x3,%xmm14,%xmm13,%xmm11,%xmm10
|
||||
VPERMIL2PD $0x2,%xmm15,(%rdi,%r8),%xmm1,%xmm0
|
||||
VPERMIL2PD $0x1,%xmm0,0x23(%r12,%r12,8),%xmm0,%xmm2
|
||||
VPERMIL2PD $0x0,%xmm3,%xmm15,%xmm13,%xmm2
|
||||
VPERMIL2PD $0x2,%xmm3,%xmm14,%xmm11,%xmm0
|
||||
VPERMIL2PD $0x1,%xmm0,(%rdx),%xmm1,%xmm0
|
||||
VPERMIL2PD $0x3,%xmm3,%xmm0,%xmm0,%xmm9
|
||||
VPERMIL2PD $0x0,%xmm2,0x23(%r12,%r12,8),%xmm0,%xmm3
|
||||
# Testing VPERMIL2PD imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PD $0x0,%xmm0,%xmm7,%xmm11,%xmm0
|
||||
VPERMIL2PD $0x1,%xmm4,%xmm5,%xmm15,%xmm0
|
||||
VPERMIL2PD $0x3,0x4(%r12,%rbx,4),%xmm8,%xmm0,%xmm10
|
||||
VPERMIL2PD $0x2,%xmm1,%xmm0,%xmm7,%xmm6
|
||||
VPERMIL2PD $0x1,(%r13,%rbx),%xmm12,%xmm6,%xmm10
|
||||
VPERMIL2PD $0x2,%xmm4,%xmm6,%xmm0,%xmm9
|
||||
VPERMIL2PD $0x0,(%rbx,%rbx,8),%xmm8,%xmm6,%xmm11
|
||||
VPERMIL2PD $0x3,%xmm5,%xmm13,%xmm6,%xmm0
|
||||
# Testing VPERMIL2PD imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PD $0x1,%ymm7,%ymm5,%ymm0,%ymm13
|
||||
VPERMIL2PD $0x0,%ymm7,(%rcx,%r9,2),%ymm4,%ymm12
|
||||
VPERMIL2PD $0x3,%ymm3,(%r14,%r11),%ymm0,%ymm8
|
||||
VPERMIL2PD $0x2,%ymm7,0x107(%r9,%rax,4),%ymm0,%ymm9
|
||||
VPERMIL2PD $0x2,%ymm7,(%r14,%r11),%ymm0,%ymm8
|
||||
VPERMIL2PD $0x3,%ymm0,(%rcx,%r9,2),%ymm4,%ymm0
|
||||
VPERMIL2PD $0x1,%ymm8,(%r14,%r11),%ymm11,%ymm5
|
||||
VPERMIL2PD $0x0,%ymm2,(%rsi),%ymm0,%ymm13
|
||||
# Testing VPERMIL2PD imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PD $0x1,(%rcx,%rsi),%ymm0,%ymm10,%ymm15
|
||||
VPERMIL2PD $0x2,(%r9),%ymm12,%ymm0,%ymm0
|
||||
VPERMIL2PD $0x0,0x15D8D9(%rcx,%r14,1),%ymm8,%ymm11,%ymm4
|
||||
VPERMIL2PD $0x3,%ymm9,%ymm12,%ymm0,%ymm0
|
||||
VPERMIL2PD $0x3,(%r13,%r11,1),%ymm1,%ymm14,%ymm8
|
||||
VPERMIL2PD $0x0,0x15D8D9(%rcx,%r14,1),%ymm0,%ymm0,%ymm11
|
||||
VPERMIL2PD $0x1,(%r13,%r11,1),%ymm1,%ymm15,%ymm0
|
||||
VPERMIL2PD $0x2,%ymm9,%ymm13,%ymm11,%ymm5
|
||||
# Testing VPERMIL2PS imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PS $0x2,%xmm0,0x23(%r12,%r12,8),%xmm0,%xmm15
|
||||
VPERMIL2PS $0x0,%xmm0,0x23(%r12,%r12,8),%xmm3,%xmm9
|
||||
VPERMIL2PS $0x3,%xmm0,%xmm12,%xmm7,%xmm11
|
||||
VPERMIL2PS $0x1,%xmm3,(%rdx),%xmm0,%xmm0
|
||||
VPERMIL2PS $0x2,%xmm3,(%r14,%r9,1),%xmm0,%xmm0
|
||||
VPERMIL2PS $0x1,%xmm3,(%rdx),%xmm1,%xmm0
|
||||
VPERMIL2PS $0x0,%xmm3,%xmm8,%xmm0,%xmm12
|
||||
VPERMIL2PS $0x3,%xmm3,(%r14,%r9,1),%xmm1,%xmm2
|
||||
# Testing VPERMIL2PS imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PS $0x1,(%r13,%rax),%xmm0,%xmm0,%xmm11
|
||||
VPERMIL2PS $0x3,(%rdi),%xmm15,%xmm6,%xmm10
|
||||
VPERMIL2PS $0x2,%xmm0,%xmm13,%xmm0,%xmm0
|
||||
VPERMIL2PS $0x0,%xmm4,%xmm0,%xmm14,%xmm10
|
||||
VPERMIL2PS $0x1,%xmm0,%xmm0,%xmm3,%xmm11
|
||||
VPERMIL2PS $0x2,(%rbx,%rbx,8),%xmm11,%xmm6,%xmm10
|
||||
VPERMIL2PS $0x3,%xmm4,%xmm5,%xmm6,%xmm15
|
||||
VPERMIL2PS $0x0,0x4(%r12,%rbx,4),%xmm0,%xmm0,%xmm10
|
||||
# Testing VPERMIL2PS imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PS $0x1,%ymm0,(%rsi),%ymm0,%ymm0
|
||||
VPERMIL2PS $0x2,%ymm15,0x107(%r9,%rax,4),%ymm11,%ymm0
|
||||
VPERMIL2PS $0x0,%ymm7,%ymm0,%ymm4,%ymm0
|
||||
VPERMIL2PS $0x3,%ymm7,(%rcx,%r9,2),%ymm4,%ymm15
|
||||
VPERMIL2PS $0x2,%ymm0,%ymm0,%ymm4,%ymm15
|
||||
VPERMIL2PS $0x3,%ymm0,0x107(%r9,%rax,4),%ymm15,%ymm13
|
||||
VPERMIL2PS $0x0,%ymm7,%ymm8,%ymm14,%ymm13
|
||||
VPERMIL2PS $0x1,%ymm7,%ymm15,%ymm4,%ymm13
|
||||
# Testing VPERMIL2PS imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PS $0x0,0x15D8D9(%rcx,%r14,1),%ymm0,%ymm0,%ymm15
|
||||
VPERMIL2PS $0x3,(%r13,%r11,1),%ymm12,%ymm15,%ymm4
|
||||
VPERMIL2PS $0x2,0x15D8D9(%rcx,%r14,1),%ymm0,%ymm0,%ymm0
|
||||
VPERMIL2PS $0x1,%ymm0,%ymm2,%ymm3,%ymm4
|
||||
VPERMIL2PS $0x3,(%rcx,%rsi),%ymm12,%ymm0,%ymm4
|
||||
VPERMIL2PS $0x2,(%rcx,%rsi),%ymm1,%ymm0,%ymm4
|
||||
VPERMIL2PS $0x0,(%r13,%r11,1),%ymm0,%ymm0,%ymm4
|
||||
VPERMIL2PS $0x1,%ymm8,%ymm7,%ymm4,%ymm0
|
||||
# Tests for op VPHADDBD xmm2/mem128, xmm1 (at&t syntax)
|
||||
VPHADDBD %xmm2,%xmm15
|
||||
VPHADDBD %xmm0,%xmm12
|
||||
|
||||
@ -294,6 +294,70 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 8f e8 50 cd 08 03[ ]+vpcomw \$0x3,\(%eax\),%xmm5,%xmm1
|
||||
[ ]*[a-f0-9]+: 8f e8 78 cd f8 03[ ]+vpcomw \$0x3,%xmm0,%xmm0,%xmm7
|
||||
[ ]*[a-f0-9]+: 8f e8 50 cd c7 ff[ ]+vpcomw \$0xff,%xmm7,%xmm5,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 41 49 00 50[ ]+vpermil2pd \$0x0,%xmm5,\(%eax\),%xmm7,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 59 49 c2 11[ ]+vpermil2pd \$0x1,%xmm1,%xmm2,%xmm4,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 41 49 10 42[ ]+vpermil2pd \$0x2,%xmm4,\(%eax\),%xmm7,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 59 49 3c 83 33[ ]+vpermil2pd \$0x3,%xmm3,\(%ebx,%eax,4\),%xmm4,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 79 49 f7 30[ ]+vpermil2pd \$0x0,%xmm3,%xmm7,%xmm0,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 49 14 16 71[ ]+vpermil2pd \$0x1,%xmm7,\(%esi,%edx,1\),%xmm0,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 59 49 fd 32[ ]+vpermil2pd \$0x2,%xmm3,%xmm5,%xmm4,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 71 49 d0 33[ ]+vpermil2pd \$0x3,%xmm3,%xmm0,%xmm1,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 69 49 f1 72[ ]+vpermil2pd \$0x2,%xmm7,%xmm1,%xmm2,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 e9 49 bc 19 88 07 00 00 01[ ]+vpermil2pd \$0x1,0x788\(%ecx,%ebx,1\),%xmm0,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 79 49 f9 40[ ]+vpermil2pd \$0x0,%xmm4,%xmm1,%xmm0,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 49 c7 33[ ]+vpermil2pd \$0x3,%xmm3,%xmm7,%xmm4,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 f9 49 b4 59 88 07 00 00 73[ ]+vpermil2pd \$0x3,0x788\(%ecx,%ebx,2\),%xmm7,%xmm0,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 51 49 c7 31[ ]+vpermil2pd \$0x1,%xmm3,%xmm7,%xmm5,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 59 49 f1 22[ ]+vpermil2pd \$0x2,%xmm2,%xmm1,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 49 fb 03[ ]+vpermil2pd \$0x3,%xmm0,%xmm3,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 75 49 d7 63[ ]+vpermil2pd \$0x3,%ymm6,%ymm7,%ymm1,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 75 49 e7 61[ ]+vpermil2pd \$0x1,%ymm6,%ymm7,%ymm1,%ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 55 49 7c 87 05 02[ ]+vpermil2pd \$0x2,%ymm0,0x5\(%edi,%eax,4\),%ymm5,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 7d 49 d6 50[ ]+vpermil2pd \$0x0,%ymm5,%ymm6,%ymm0,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 65 49 c7 43[ ]+vpermil2pd \$0x3,%ymm4,%ymm7,%ymm3,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 49 c6 70[ ]+vpermil2pd \$0x0,%ymm7,%ymm6,%ymm2,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 75 49 3e 42[ ]+vpermil2pd \$0x2,%ymm4,\(%esi\),%ymm1,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 75 49 f8 61[ ]+vpermil2pd \$0x1,%ymm6,%ymm0,%ymm1,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 c5 49 01 51[ ]+vpermil2pd \$0x1,\(%ecx\),%ymm5,%ymm7,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 c5 49 04 46 43[ ]+vpermil2pd \$0x3,\(%esi,%eax,2\),%ymm4,%ymm7,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 e5 49 39 00[ ]+vpermil2pd \$0x0,\(%ecx\),%ymm0,%ymm3,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 49 3c 06 22[ ]+vpermil2pd \$0x2,\(%esi,%eax,1\),%ymm2,%ymm6,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 49 09 00[ ]+vpermil2pd \$0x0,\(%ecx\),%ymm0,%ymm6,%ymm1
|
||||
[ ]*[a-f0-9]+: c4 e3 45 49 c3 22[ ]+vpermil2pd \$0x2,%ymm2,%ymm3,%ymm7,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 45 49 ca 03[ ]+vpermil2pd \$0x3,%ymm0,%ymm2,%ymm7,%ymm1
|
||||
[ ]*[a-f0-9]+: c4 e3 5d 49 f8 51[ ]+vpermil2pd \$0x1,%ymm5,%ymm0,%ymm4,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 79 48 fc 33[ ]+vpermil2ps \$0x3,%xmm3,%xmm4,%xmm0,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 59 48 38 01[ ]+vpermil2ps \$0x1,%xmm0,\(%eax\),%xmm4,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 41 48 38 32[ ]+vpermil2ps \$0x2,%xmm3,\(%eax\),%xmm7,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 41 48 14 c3 73[ ]+vpermil2ps \$0x3,%xmm7,\(%ebx,%eax,8\),%xmm7,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 41 48 f8 72[ ]+vpermil2ps \$0x2,%xmm7,%xmm0,%xmm7,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 79 48 3c 16 73[ ]+vpermil2ps \$0x3,%xmm7,\(%esi,%edx,1\),%xmm0,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 41 48 fc 71[ ]+vpermil2ps \$0x1,%xmm7,%xmm4,%xmm7,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 41 48 10 30[ ]+vpermil2ps \$0x0,%xmm3,\(%eax\),%xmm7,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 c1 48 33 72[ ]+vpermil2ps \$0x2,\(%ebx\),%xmm7,%xmm7,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 48 04 1b 73[ ]+vpermil2ps \$0x3,\(%ebx,%ebx,1\),%xmm7,%xmm5,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 c1 48 34 1b 10[ ]+vpermil2ps \$0x0,\(%ebx,%ebx,1\),%xmm1,%xmm7,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 48 f9 02[ ]+vpermil2ps \$0x2,%xmm0,%xmm1,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 e9 48 34 1b 72[ ]+vpermil2ps \$0x2,\(%ebx,%ebx,1\),%xmm7,%xmm2,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 c1 48 34 1b 13[ ]+vpermil2ps \$0x3,\(%ebx,%ebx,1\),%xmm1,%xmm7,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 e9 48 3c 1b 70[ ]+vpermil2ps \$0x0,\(%ebx,%ebx,1\),%xmm7,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 41 48 f9 71[ ]+vpermil2ps \$0x1,%xmm7,%xmm1,%xmm7,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 75 48 d7 61[ ]+vpermil2ps \$0x1,%ymm6,%ymm7,%ymm1,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 45 48 c6 73[ ]+vpermil2ps \$0x3,%ymm7,%ymm6,%ymm7,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 45 48 d6 52[ ]+vpermil2ps \$0x2,%ymm5,%ymm6,%ymm7,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 45 48 f8 20[ ]+vpermil2ps \$0x0,%ymm2,%ymm0,%ymm7,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 45 48 04 cf 63[ ]+vpermil2ps \$0x3,%ymm6,\(%edi,%ecx,8\),%ymm7,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 45 48 c7 62[ ]+vpermil2ps \$0x2,%ymm6,%ymm7,%ymm7,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 75 48 d6 70[ ]+vpermil2ps \$0x0,%ymm7,%ymm6,%ymm1,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 75 48 06 61[ ]+vpermil2ps \$0x1,%ymm6,\(%esi\),%ymm1,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 fd 48 7c 43 0c 42[ ]+vpermil2ps \$0x2,0xc\(%ebx,%eax,2\),%ymm4,%ymm0,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 48 c6 51[ ]+vpermil2ps \$0x1,%ymm5,%ymm6,%ymm2,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 48 3c 06 43[ ]+vpermil2ps \$0x3,\(%esi,%eax,1\),%ymm4,%ymm6,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 cd 48 04 de 31[ ]+vpermil2ps \$0x1,\(%esi,%ebx,8\),%ymm3,%ymm6,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 fd 48 0c 48 70[ ]+vpermil2ps \$0x0,\(%eax,%ecx,2\),%ymm7,%ymm0,%ymm1
|
||||
[ ]*[a-f0-9]+: c4 e3 45 48 ff 62[ ]+vpermil2ps \$0x2,%ymm6,%ymm7,%ymm7,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 48 c3 43[ ]+vpermil2ps \$0x3,%ymm4,%ymm3,%ymm2,%ymm0
|
||||
[ ]*[a-f0-9]+: c4 e3 45 48 fe 00[ ]+vpermil2ps \$0x0,%ymm0,%ymm6,%ymm7,%ymm7
|
||||
[ ]*[a-f0-9]+: 8f e9 78 c2 ff[ ]+vphaddbd %xmm7,%xmm7
|
||||
[ ]*[a-f0-9]+: 8f e9 78 c2 f0[ ]+vphaddbd %xmm0,%xmm6
|
||||
[ ]*[a-f0-9]+: 8f e9 78 c2 03[ ]+vphaddbd \(%ebx\),%xmm0
|
||||
|
||||
@ -310,6 +310,78 @@ _start:
|
||||
VPCOMW $0x3,(%eax),%xmm5,%xmm1
|
||||
VPCOMW $0x3,%xmm0,%xmm0,%xmm7
|
||||
VPCOMW $0xFF,%xmm7,%xmm5,%xmm0
|
||||
# Testing VPERMIL2PD imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PD $0x0,%xmm5,(%eax),%xmm7,%xmm0
|
||||
VPERMIL2PD $0x1,%xmm1,%xmm2,%xmm4,%xmm0
|
||||
VPERMIL2PD $0x2,%xmm4,(%eax),%xmm7,%xmm2
|
||||
VPERMIL2PD $0x3,%xmm3,(%ebx,%eax,4),%xmm4,%xmm7
|
||||
VPERMIL2PD $0x0,%xmm3,%xmm7,%xmm0,%xmm6
|
||||
VPERMIL2PD $0x1,%xmm7,(%esi,%edx),%xmm0,%xmm2
|
||||
VPERMIL2PD $0x2,%xmm3,%xmm5,%xmm4,%xmm7
|
||||
VPERMIL2PD $0x3,%xmm3,%xmm0,%xmm1,%xmm2
|
||||
# Testing VPERMIL2PD imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PD $0x2,%xmm7,%xmm1,%xmm2,%xmm6
|
||||
VPERMIL2PD $0x1,0x788(%ecx,%ebx,1),%xmm0,%xmm2,%xmm7
|
||||
VPERMIL2PD $0x0,%xmm4,%xmm1,%xmm0,%xmm7
|
||||
VPERMIL2PD $0x3,%xmm3,%xmm7,%xmm4,%xmm0
|
||||
VPERMIL2PD $0x3,0x788(%ecx,%ebx,2),%xmm7,%xmm0,%xmm6
|
||||
VPERMIL2PD $0x1,%xmm3,%xmm7,%xmm5,%xmm0
|
||||
VPERMIL2PD $0x2,%xmm2,%xmm1,%xmm4,%xmm6
|
||||
VPERMIL2PD $0x3,%xmm0,%xmm3,%xmm2,%xmm7
|
||||
# Testing VPERMIL2PD imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PD $0x3,%ymm6,%ymm7,%ymm1,%ymm2
|
||||
VPERMIL2PD $0x1,%ymm6,%ymm7,%ymm1,%ymm4
|
||||
VPERMIL2PD $0x2,%ymm0,0x5(%edi,%eax,4),%ymm5,%ymm7
|
||||
VPERMIL2PD $0x0,%ymm5,%ymm6,%ymm0,%ymm2
|
||||
VPERMIL2PD $0x3,%ymm4,%ymm7,%ymm3,%ymm0
|
||||
VPERMIL2PD $0x0,%ymm7,%ymm6,%ymm2,%ymm0
|
||||
VPERMIL2PD $0x2,%ymm4,(%esi),%ymm1,%ymm7
|
||||
VPERMIL2PD $0x1,%ymm6,%ymm0,%ymm1,%ymm7
|
||||
# Testing VPERMIL2PD imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PD $0x1,(%ecx),%ymm5,%ymm7,%ymm0
|
||||
VPERMIL2PD $0x3,(%esi,%eax,2),%ymm4,%ymm7,%ymm0
|
||||
VPERMIL2PD $0x0,(%ecx),%ymm0,%ymm3,%ymm7
|
||||
VPERMIL2PD $0x2,(%esi,%eax,1),%ymm2,%ymm6,%ymm7
|
||||
VPERMIL2PD $0x0,(%ecx),%ymm0,%ymm6,%ymm1
|
||||
VPERMIL2PD $0x2,%ymm2,%ymm3,%ymm7,%ymm0
|
||||
VPERMIL2PD $0x3,%ymm0,%ymm2,%ymm7,%ymm1
|
||||
VPERMIL2PD $0x1,%ymm5,%ymm0,%ymm4,%ymm7
|
||||
# Testing VPERMIL2PS imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PS $0x3,%xmm3,%xmm4,%xmm0,%xmm7
|
||||
VPERMIL2PS $0x1,%xmm0,(%eax),%xmm4,%xmm7
|
||||
VPERMIL2PS $0x2,%xmm3,(%eax),%xmm7,%xmm7
|
||||
VPERMIL2PS $0x3,%xmm7,(%ebx,%eax,8),%xmm7,%xmm2
|
||||
VPERMIL2PS $0x2,%xmm7,%xmm0,%xmm7,%xmm7
|
||||
VPERMIL2PS $0x3,%xmm7,(%esi,%edx),%xmm0,%xmm7
|
||||
VPERMIL2PS $0x1,%xmm7,%xmm4,%xmm7,%xmm7
|
||||
VPERMIL2PS $0x0,%xmm3,(%eax),%xmm7,%xmm2
|
||||
# Testing VPERMIL2PS imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
|
||||
VPERMIL2PS $0x2,(%ebx),%xmm7,%xmm7,%xmm6
|
||||
VPERMIL2PS $0x3,(%ebx,%ebx),%xmm7,%xmm5,%xmm0
|
||||
VPERMIL2PS $0x0,(%ebx,%ebx),%xmm1,%xmm7,%xmm6
|
||||
VPERMIL2PS $0x2,%xmm0,%xmm1,%xmm2,%xmm7
|
||||
VPERMIL2PS $0x2,(%ebx,%ebx),%xmm7,%xmm2,%xmm6
|
||||
VPERMIL2PS $0x3,(%ebx,%ebx),%xmm1,%xmm7,%xmm6
|
||||
VPERMIL2PS $0x0,(%ebx,%ebx),%xmm7,%xmm2,%xmm7
|
||||
VPERMIL2PS $0x1,%xmm7,%xmm1,%xmm7,%xmm7
|
||||
# Testing VPERMIL2PS imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PS $0x1,%ymm6,%ymm7,%ymm1,%ymm2
|
||||
VPERMIL2PS $0x3,%ymm7,%ymm6,%ymm7,%ymm0
|
||||
VPERMIL2PS $0x2,%ymm5,%ymm6,%ymm7,%ymm2
|
||||
VPERMIL2PS $0x0,%ymm2,%ymm0,%ymm7,%ymm7
|
||||
VPERMIL2PS $0x3,%ymm6,(%edi,%ecx,8),%ymm7,%ymm0
|
||||
VPERMIL2PS $0x2,%ymm6,%ymm7,%ymm7,%ymm0
|
||||
VPERMIL2PS $0x0,%ymm7,%ymm6,%ymm1,%ymm2
|
||||
VPERMIL2PS $0x1,%ymm6,(%esi),%ymm1,%ymm0
|
||||
# Testing VPERMIL2PS imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
|
||||
VPERMIL2PS $0x2,0xC(%ebx,%eax,2),%ymm4,%ymm0,%ymm7
|
||||
VPERMIL2PS $0x1,%ymm5,%ymm6,%ymm2,%ymm0
|
||||
VPERMIL2PS $0x3,(%esi,%eax,1),%ymm4,%ymm6,%ymm7
|
||||
VPERMIL2PS $0x1,(%esi,%ebx,8),%ymm3,%ymm6,%ymm0
|
||||
VPERMIL2PS $0x0,(%eax,%ecx,2),%ymm7,%ymm0,%ymm1
|
||||
VPERMIL2PS $0x2,%ymm6,%ymm7,%ymm7,%ymm7
|
||||
VPERMIL2PS $0x3,%ymm4,%ymm3,%ymm2,%ymm0
|
||||
VPERMIL2PS $0x0,%ymm0,%ymm6,%ymm7,%ymm7
|
||||
# Tests for op VPHADDBD xmm2/mem128, xmm1 (at&t syntax)
|
||||
VPHADDBD %xmm7,%xmm7
|
||||
VPHADDBD %xmm0,%xmm6
|
||||
|
||||
@ -1,3 +1,24 @@
|
||||
2010-02-10 Quentin Neill <quentin.neill@amd.com>
|
||||
Sebastian Pop <sebastian.pop@amd.com>
|
||||
|
||||
* i386-dis.c (OP_EX_VexImmW): Reintroduced
|
||||
function to handle 5th imm8 operand.
|
||||
(PREFIX_VEX_3A48): Added.
|
||||
(PREFIX_VEX_3A49): Added.
|
||||
(VEX_W_3A48_P_2): Added.
|
||||
(VEX_W_3A49_P_2): Added.
|
||||
(prefix table): Added entries for PREFIX_VEX_3A48
|
||||
and PREFIX_VEX_3A49.
|
||||
(vex table): Added entries for VEX_W_3A48_P_2 and
|
||||
and VEX_W_3A49_P_2.
|
||||
* i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
|
||||
for Vec_Imm4 operands.
|
||||
* i386-opc.h (enum): Added Vec_Imm4.
|
||||
(i386_operand_type): Added vec_imm4.
|
||||
* i386-opc.tbl: Add entries for vpermilp[ds].
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Regenerated.
|
||||
|
||||
2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
|
||||
|
||||
* ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
|
||||
|
||||
@ -91,6 +91,7 @@ static void OP_M (int, int);
|
||||
static void OP_VEX (int, int);
|
||||
static void OP_EX_Vex (int, int);
|
||||
static void OP_EX_VexW (int, int);
|
||||
static void OP_EX_VexImmW (int, int);
|
||||
static void OP_XMM_Vex (int, int);
|
||||
static void OP_XMM_VexW (int, int);
|
||||
static void OP_REG_VexI4 (int, int);
|
||||
@ -380,6 +381,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
||||
#define EXVexW { OP_EX_VexW, x_mode }
|
||||
#define EXdVexW { OP_EX_VexW, d_mode }
|
||||
#define EXqVexW { OP_EX_VexW, q_mode }
|
||||
#define EXVexImmW { OP_EX_VexImmW, x_mode }
|
||||
#define XMVex { OP_XMM_Vex, 0 }
|
||||
#define XMVexScalar { OP_XMM_Vex, scalar_mode }
|
||||
#define XMVexW { OP_XMM_VexW, 0 }
|
||||
@ -1032,6 +1034,8 @@ enum
|
||||
PREFIX_VEX_3A41,
|
||||
PREFIX_VEX_3A42,
|
||||
PREFIX_VEX_3A44,
|
||||
PREFIX_VEX_3A48,
|
||||
PREFIX_VEX_3A49,
|
||||
PREFIX_VEX_3A4A,
|
||||
PREFIX_VEX_3A4B,
|
||||
PREFIX_VEX_3A4C,
|
||||
@ -1570,6 +1574,8 @@ enum
|
||||
VEX_W_3A41_P_2,
|
||||
VEX_W_3A42_P_2,
|
||||
VEX_W_3A44_P_2,
|
||||
VEX_W_3A48_P_2,
|
||||
VEX_W_3A49_P_2,
|
||||
VEX_W_3A4A_P_2,
|
||||
VEX_W_3A4B_P_2,
|
||||
VEX_W_3A4C_P_2,
|
||||
@ -5087,6 +5093,20 @@ static const struct dis386 prefix_table[][4] = {
|
||||
{ VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A48 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (VEX_W_3A48_P_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A49 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (VEX_W_3A49_P_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_3A4A */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
@ -7858,8 +7878,8 @@ static const struct dis386 vex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 48 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A48) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A49) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A4A) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A4B) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_3A4C) },
|
||||
@ -10117,6 +10137,16 @@ static const struct dis386 vex_w_table[][2] = {
|
||||
/* VEX_W_3A44_P_2 */
|
||||
{ "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
|
||||
},
|
||||
{
|
||||
/* VEX_W_3A48_P_2 */
|
||||
{ "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
|
||||
{ "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
|
||||
},
|
||||
{
|
||||
/* VEX_W_3A49_P_2 */
|
||||
{ "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
|
||||
{ "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
|
||||
},
|
||||
{
|
||||
/* VEX_W_3A4A_P_2 */
|
||||
{ "vblendvps", { XM, Vex, EXx, XMVexI4 } },
|
||||
@ -14580,6 +14610,47 @@ OP_EX_VexReg (int bytemode, int sizeflag, int reg)
|
||||
oappend (names[reg]);
|
||||
}
|
||||
|
||||
static void
|
||||
OP_EX_VexImmW (int bytemode, int sizeflag)
|
||||
{
|
||||
int reg = -1;
|
||||
static unsigned char vex_imm8;
|
||||
|
||||
if (vex_w_done == 0)
|
||||
{
|
||||
vex_w_done = 1;
|
||||
|
||||
/* Skip mod/rm byte. */
|
||||
MODRM_CHECK;
|
||||
codep++;
|
||||
|
||||
vex_imm8 = get_vex_imm8 (sizeflag, 0);
|
||||
|
||||
if (vex.w)
|
||||
reg = vex_imm8 >> 4;
|
||||
|
||||
OP_EX_VexReg (bytemode, sizeflag, reg);
|
||||
}
|
||||
else if (vex_w_done == 1)
|
||||
{
|
||||
vex_w_done = 2;
|
||||
|
||||
if (!vex.w)
|
||||
reg = vex_imm8 >> 4;
|
||||
|
||||
OP_EX_VexReg (bytemode, sizeflag, reg);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Output the imm8 directly. */
|
||||
scratchbuf[0] = '$';
|
||||
print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
|
||||
oappend (scratchbuf + intel_syntax);
|
||||
scratchbuf[0] = '\0';
|
||||
codep++;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
OP_Vex_2src (int bytemode, int sizeflag)
|
||||
{
|
||||
|
||||
@ -254,6 +254,8 @@ static initializer operand_type_init[] =
|
||||
"Imm32|Imm32S|Imm64|Disp32" },
|
||||
{ "OPERAND_TYPE_IMM32_32S_64_DISP32_64",
|
||||
"Imm32|Imm32S|Imm64|Disp32|Disp64" },
|
||||
{ "OPERAND_TYPE_VEC_IMM4",
|
||||
"Vec_Imm4" },
|
||||
};
|
||||
|
||||
typedef struct bitfield
|
||||
@ -414,6 +416,7 @@ static bitfield operand_types[] =
|
||||
BITFIELD (Ymmword),
|
||||
BITFIELD (Unspecified),
|
||||
BITFIELD (Anysize),
|
||||
BITFIELD (Vec_Imm4),
|
||||
#ifdef OTUnused
|
||||
BITFIELD (OTUnused),
|
||||
#endif
|
||||
|
||||
@ -313,229 +313,234 @@
|
||||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG2 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGYMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16_INOUTPORTREG \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_VEC_IMM4 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0 } }
|
||||
|
||||
@ -500,6 +500,9 @@ enum
|
||||
/* Any memory size. */
|
||||
Anysize,
|
||||
|
||||
/* Vector 4 bit immediate. */
|
||||
Vec_Imm4,
|
||||
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
OTMax
|
||||
};
|
||||
@ -561,6 +564,7 @@ typedef union i386_operand_type
|
||||
unsigned int ymmword:1;
|
||||
unsigned int unspecified:1;
|
||||
unsigned int anysize:1;
|
||||
unsigned int vec_imm4:1;
|
||||
#ifdef OTUnused
|
||||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||||
#endif
|
||||
|
||||
@ -2553,6 +2553,8 @@ vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|V
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// XOP instructions
|
||||
// We add Imm8 to Vex_Imm4. We use Imm8 to indicate that the operand
|
||||
// is an immediate. We will check if its value will fit 4 bits.
|
||||
|
||||
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
|
||||
@ -2572,6 +2574,14 @@ vpcomud, 4, 0xee, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreS
|
||||
vpcomuq, 4, 0xef, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomuw, 4, 0xed, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomw, 4, 0xcd, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
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vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
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vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
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vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
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vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
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vpcomltb, 3, 0xcc, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
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vpcomltd, 3, 0xce, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
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vpcomltq, 3, 0xcf, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
|
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11262
opcodes/i386-tbl.h
11262
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user