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x86: Add Intel ENCLV to assembler and disassembler

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gas/

	* testsuite/gas/i386/se1.s: Add enclv.
	* testsuite/gas/i386/x86-64-se1.s: Likewise.
	* testsuite/gas/i386/se1.d: Updated.
	* testsuite/gas/i386/x86-64-se1.d: Likewise.

opcodes/

	* i386-dis.c (rm_table): Add enclv.
	* i386-opc.tbl: Add enclv.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu 2018-10-05 11:56:42 -07:00
parent f8740dc531
commit a4e78aa5fe
9 changed files with 33 additions and 1 deletions
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7
gas/ChangeLog
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@ -1,3 +1,10 @@
2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/se1.s: Add enclv.
* testsuite/gas/i386/x86-64-se1.s: Likewise.
* testsuite/gas/i386/se1.d: Updated.
* testsuite/gas/i386/x86-64-se1.d: Likewise.
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_ext_predres): New.

1
gas/testsuite/gas/i386/se1.d
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@ -10,4 +10,5 @@ Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f 01 cf encls
[ ]*[a-f0-9]+: 0f 01 d7 enclu
[ ]*[a-f0-9]+: 0f 01 c0 enclv
#pass

1
gas/testsuite/gas/i386/se1.s
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@ -5,3 +5,4 @@ _start:
encls
enclu
enclv

1
gas/testsuite/gas/i386/x86-64-se1.d
View File

@ -10,4 +10,5 @@ Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f 01 cf encls
[ ]*[a-f0-9]+: 0f 01 d7 enclu
[ ]*[a-f0-9]+: 0f 01 c0 enclv
#pass

1
gas/testsuite/gas/i386/x86-64-se1.s
View File

@ -5,3 +5,4 @@ _start:
encls
enclu
enclv

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (rm_table): Add enclv.
* i386-opc.tbl: Add enclv.
* i386-tbl.h: Regenerated.
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (arm_opcodes): Add sb.

2
opcodes/i386-dis.c
View File

@ -11027,7 +11027,7 @@ static const struct dis386 rm_table[][8] = {
},
{
/* RM_0F01_REG_0 */
{ Bad_Opcode },
{ "enclv", { Skip_MODRM }, 0 },
{ "vmcall", { Skip_MODRM }, 0 },
{ "vmlaunch", { Skip_MODRM }, 0 },
{ "vmresume", { Skip_MODRM }, 0 },

1
opcodes/i386-opc.tbl
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@ -3992,6 +3992,7 @@ xsavec64, 1, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS
encls, 0, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
enclu, 0, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
enclv, 0, 0xf01c0, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
// SGX instructions end.

14
opcodes/i386-tbl.h
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@ -66539,6 +66539,20 @@ const insn_template i386_optab[] =
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 } } } },
{ "enclv", 0, 0xf01c0, None, 3,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 } } } },
{ "vcvtpd2udqx", 2, 0x79, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0,