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[PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (struct asm_opcode): Make avalue a full int. (BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors. (enum operand_parse_code): Handle new operands. (parse_operands): Likewise. (M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx, M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx, M_MNEM_vmlsdavax): Define new encodings. (NEON_SHAPE_DEF): Add new shape. (neon_check_type): Use BAD_SIMD_TYPE. (mve_encode_rqq): New encoding helper function. (do_mve_vabav, do_mve_vmladav): New encoding functions. (mCEF): New MACRO. * testsuite/gas/arm/mve-vabav-bad.d: New test. * testsuite/gas/arm/mve-vabav-bad.l: New test. * testsuite/gas/arm/mve-vabav-bad.s: New test. * testsuite/gas/arm/mve-vmladav-bad.d: New test. * testsuite/gas/arm/mve-vmladav-bad.l: New test. * testsuite/gas/arm/mve-vmladav-bad.s: New test. * testsuite/gas/arm/mve-vmlav-bad.d: New test. * testsuite/gas/arm/mve-vmlav-bad.l: New test. * testsuite/gas/arm/mve-vmlav-bad.s: New test. * testsuite/gas/arm/mve-vmlsdav-bad.d: New test. * testsuite/gas/arm/mve-vmlsdav-bad.l: New test. * testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
485dee97c6
commit
a302e57418
@ -1,3 +1,30 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (struct asm_opcode): Make avalue a full int.
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(BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors.
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(enum operand_parse_code): Handle new operands.
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(parse_operands): Likewise.
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(M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx,
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M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx,
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M_MNEM_vmlsdavax): Define new encodings.
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(NEON_SHAPE_DEF): Add new shape.
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(neon_check_type): Use BAD_SIMD_TYPE.
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(mve_encode_rqq): New encoding helper function.
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(do_mve_vabav, do_mve_vmladav): New encoding functions.
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(mCEF): New MACRO.
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* testsuite/gas/arm/mve-vabav-bad.d: New test.
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* testsuite/gas/arm/mve-vabav-bad.l: New test.
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* testsuite/gas/arm/mve-vabav-bad.s: New test.
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* testsuite/gas/arm/mve-vmladav-bad.d: New test.
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* testsuite/gas/arm/mve-vmladav-bad.l: New test.
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* testsuite/gas/arm/mve-vmladav-bad.s: New test.
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* testsuite/gas/arm/mve-vmlav-bad.d: New test.
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* testsuite/gas/arm/mve-vmlav-bad.l: New test.
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* testsuite/gas/arm/mve-vmlav-bad.s: New test.
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* testsuite/gas/arm/mve-vmlsdav-bad.d: New test.
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* testsuite/gas/arm/mve-vmlsdav-bad.l: New test.
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* testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
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@ -708,7 +708,7 @@ struct asm_opcode
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unsigned int tag : 4;
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/* Basic instruction code. */
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unsigned int avalue : 28;
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unsigned int avalue;
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/* Thumb-format instruction code. */
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unsigned int tvalue;
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@ -851,6 +851,8 @@ struct asm_opcode
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#define BAD_ARGS _("bad arguments to instruction")
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#define BAD_SP _("r13 not allowed here")
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#define BAD_PC _("r15 not allowed here")
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#define BAD_ODD _("Odd register not allowed here")
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#define BAD_EVEN _("Even register not allowed here")
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#define BAD_COND _("instruction cannot be conditional")
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#define BAD_OVERLAP _("registers may not be the same")
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#define BAD_HIREG _("lo register required")
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@ -884,6 +886,7 @@ struct asm_opcode
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" operand")
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#define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
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" operand")
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#define BAD_SIMD_TYPE _("bad type in SIMD instruction")
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static struct hash_control * arm_ops_hsh;
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static struct hash_control * arm_cond_hsh;
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@ -6714,8 +6717,12 @@ enum operand_parse_code
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*/
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OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
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GPR (no SP/SP) */
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OP_RMQ, /* MVE vector register. */
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/* New operands for Armv8.1-M Mainline. */
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OP_LR, /* ARM LR register */
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OP_RRe, /* ARM register, only even numbered. */
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OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
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OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
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OP_REGLST, /* ARM register list */
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@ -6973,6 +6980,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_RRnpc:
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case OP_RRnpcsp:
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case OP_oRR:
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case OP_RRe:
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case OP_RRo:
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case OP_LR:
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case OP_oLR:
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case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
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@ -7037,6 +7046,9 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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po_reg_or_fail (REG_TYPE_NSDQ);
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inst.error = 0;
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break;
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case OP_RMQ:
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po_reg_or_fail (REG_TYPE_MQ);
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break;
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/* Neon scalar. Using an element size of 8 means that some invalid
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scalars are accepted here, so deal with those in later code. */
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case OP_RNSC: po_scalar_or_goto (8, failure); break;
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@ -7557,6 +7569,24 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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inst.error = _("operand must be LR register");
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break;
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case OP_RRe:
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if (inst.operands[i].isreg
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&& (inst.operands[i].reg & 0x00000001) != 0)
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inst.error = BAD_ODD;
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break;
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case OP_RRo:
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if (inst.operands[i].isreg)
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{
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if ((inst.operands[i].reg & 0x00000001) != 1)
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inst.error = BAD_EVEN;
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else if (inst.operands[i].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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else if (inst.operands[i].reg == REG_PC)
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inst.error = BAD_PC;
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}
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break;
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default:
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break;
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}
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@ -13793,6 +13823,17 @@ do_t_loloop (void)
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}
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}
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/* MVE instruction encoder helpers. */
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#define M_MNEM_vabav 0xee800f01
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#define M_MNEM_vmladav 0xeef00e00
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#define M_MNEM_vmladava 0xeef00e20
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#define M_MNEM_vmladavx 0xeef01e00
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#define M_MNEM_vmladavax 0xeef01e20
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#define M_MNEM_vmlsdav 0xeef00e01
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#define M_MNEM_vmlsdava 0xeef00e21
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#define M_MNEM_vmlsdavx 0xeef01e01
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#define M_MNEM_vmlsdavax 0xeef01e21
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/* Neon instruction encoder helpers. */
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/* Encodings for the different types for various Neon opcodes. */
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@ -13956,6 +13997,7 @@ NEON_ENC_TAB
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- a table used to drive neon_select_shape. */
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#define NEON_SHAPE_DEF \
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X(3, (R, Q, Q), QUAD), \
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X(3, (D, D, D), DOUBLE), \
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X(3, (Q, Q, Q), QUAD), \
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X(3, (D, D, I), DOUBLE), \
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@ -14683,7 +14725,7 @@ neon_check_type (unsigned els, enum neon_shape ns, ...)
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if ((given_type & types_allowed) == 0)
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{
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first_error (_("bad type in SIMD instruction"));
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first_error (BAD_SIMD_TYPE);
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return badtype;
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}
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}
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@ -15165,6 +15207,19 @@ mve_encode_qqr (int size, int fp)
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inst.is_neon = 1;
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}
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static void
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mve_encode_rqq (unsigned bit28, unsigned size)
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{
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inst.instruction |= bit28 << 28;
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inst.instruction |= neon_logbits (size) << 20;
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inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 7;
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inst.instruction |= HI1 (inst.operands[2].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[2].reg);
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inst.is_neon = 1;
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}
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/* Encode insns with bit pattern:
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|28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
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@ -15883,6 +15938,65 @@ do_neon_qdmulh (void)
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}
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}
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static void
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do_mve_vabav (void)
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{
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enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
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if (rs == NS_NULL)
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return;
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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return;
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struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
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| N_S16 | N_S32 | N_U8 | N_U16
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| N_U32);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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mve_encode_rqq (et.type == NT_unsigned, et.size);
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}
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static void
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do_mve_vmladav (void)
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{
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enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_SU_MVE | N_KEY);
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if (et.type == NT_unsigned
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&& (inst.instruction == M_MNEM_vmladavx
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|| inst.instruction == M_MNEM_vmladavax
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|| inst.instruction == M_MNEM_vmlsdav
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|| inst.instruction == M_MNEM_vmlsdava
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|| inst.instruction == M_MNEM_vmlsdavx
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|| inst.instruction == M_MNEM_vmlsdavax))
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first_error (BAD_SIMD_TYPE);
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constraint (inst.operands[2].reg > 14,
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_("MVE vector register in the range [Q0..Q7] expected"));
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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if (inst.instruction == M_MNEM_vmlsdav
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|| inst.instruction == M_MNEM_vmlsdava
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|| inst.instruction == M_MNEM_vmlsdavx
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|| inst.instruction == M_MNEM_vmlsdavax)
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inst.instruction |= (et.size == 8) << 28;
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else
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inst.instruction |= (et.size == 8) << 8;
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mve_encode_rqq (et.type == NT_unsigned, 64);
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inst.instruction |= (et.size == 32) << 16;
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}
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static void
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do_neon_qrdmlah (void)
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{
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@ -20573,7 +20687,7 @@ static struct asm_barrier_opt barrier_opt_names[] =
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/* */
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#define mCEF(mnem, op, nops, ops, enc) \
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{ #mnem, OPS##nops ops, OT_csuffixF, 0, M_MNEM##op, \
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{ #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
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ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
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@ -22633,6 +22747,19 @@ static const struct asm_opcode insns[] =
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ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
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ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
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/* MVE and MVE FP only. */
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mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
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mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_vfp_ext_v1xd
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#undef THUMB_VARIANT
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6
gas/testsuite/gas/arm/mve-vabav-bad.d
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6
gas/testsuite/gas/arm/mve-vabav-bad.d
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@ -0,0 +1,6 @@
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#name: bad MVE VABAV instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vabav-bad.l
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.*: +file format .*arm.*
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18
gas/testsuite/gas/arm/mve-vabav-bad.l
Normal file
18
gas/testsuite/gas/arm/mve-vabav-bad.l
Normal file
@ -0,0 +1,18 @@
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[^:]*: Assembler messages:
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[^:]*:13: Error: bad type in SIMD instruction -- `vabav.s64 r0,q0,q1'
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[^:]*:14: Error: bad type in SIMD instruction -- `vabav.f16 r0,q0,q1'
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[^:]*:15: Error: bad type in SIMD instruction -- `vabav.f32 r0,q0,q1'
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[^:]*:16: Error: bad type in SIMD instruction -- `vabav.p8 r0,q0,q1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vabav.p16 r0,q0,q1'
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[^:]*:18: Error: r13 not allowed here -- `vabav.s32 r13,q0,q1'
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[^:]*:19: Error: r15 not allowed here -- `vabav.s32 r15,q0,q1'
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Error: syntax error -- `vabaveq.s32 r0,q0,q1'
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[^:]*:23: Error: syntax error -- `vabaveq.s32 r0,q0,q1'
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[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1'
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[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1'
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26
gas/testsuite/gas/arm/mve-vabav-bad.s
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26
gas/testsuite/gas/arm/mve-vabav-bad.s
Normal file
@ -0,0 +1,26 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s32 r0, q0, q1
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.endr
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.endm
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.syntax unified
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.text
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.thumb
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vabav.s64 r0, q0, q1
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vabav.f16 r0, q0, q1
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vabav.f32 r0, q0, q1
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vabav.p8 r0, q0, q1
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vabav.p16 r0, q0, q1
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vabav.s32 r13, q0, q1
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vabav.s32 r15, q0, q1
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cond vabav
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vpst
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vabaveq.s32 r0, q0, q1
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vabaveq.s32 r0, q0, q1
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it eq
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vabavt.s32 r0, q0, q1
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vabavt.s32 r0, q0, q1
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5
gas/testsuite/gas/arm/mve-vmladav-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmladav-bad.d
Normal file
@ -0,0 +1,5 @@
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#name: Bad MVE VMLADAV instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vmladav-bad.l
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.*: +file format .*arm.*
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55
gas/testsuite/gas/arm/mve-vmladav-bad.l
Normal file
55
gas/testsuite/gas/arm/mve-vmladav-bad.l
Normal file
@ -0,0 +1,55 @@
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[^:]*: Assembler messages:
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Error: bad type in SIMD instruction -- `vmladav.s64 r0,q1,q2'
|
||||
[^:]*:15: Error: bad type in SIMD instruction -- `vmladav.f32 r0,q1,q2'
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vmladava.s64 r0,q1,q2'
|
||||
[^:]*:17: Error: bad type in SIMD instruction -- `vmladava.f32 r0,q1,q2'
|
||||
[^:]*:18: Error: bad type in SIMD instruction -- `vmladavx.s64 r0,q1,q2'
|
||||
[^:]*:19: Error: bad type in SIMD instruction -- `vmladavx.f32 r0,q1,q2'
|
||||
[^:]*:20: Error: bad type in SIMD instruction -- `vmladavax.s64 r0,q1,q2'
|
||||
[^:]*:21: Error: bad type in SIMD instruction -- `vmladavax.f32 r0,q1,q2'
|
||||
[^:]*:22: Error: bad type in SIMD instruction -- `vmladavx.u32 r0,q1,q2'
|
||||
[^:]*:23: Error: bad type in SIMD instruction -- `vmladavax.u16 r0,q1,q2'
|
||||
[^:]*:25: Error: syntax error -- `vmladaveq.s32 r0,q1,q2'
|
||||
[^:]*:26: Error: syntax error -- `vmladaveq.s32 r0,q1,q2'
|
||||
[^:]*:28: Error: syntax error -- `vmladaveq.s32 r0,q1,q2'
|
||||
[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavt.s32 r0,q1,q2'
|
||||
[^:]*:31: Error: instruction missing MVE vector predication code -- `vmladav.s32 r0,q1,q2'
|
||||
[^:]*:33: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2'
|
||||
[^:]*:34: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2'
|
||||
[^:]*:36: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2'
|
||||
[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavat.s32 r0,q1,q2'
|
||||
[^:]*:39: Error: instruction missing MVE vector predication code -- `vmladava.s32 r0,q1,q2'
|
||||
[^:]*:41: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2'
|
||||
[^:]*:42: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2'
|
||||
[^:]*:44: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2'
|
||||
[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavxt.s32 r0,q1,q2'
|
||||
[^:]*:47: Error: instruction missing MVE vector predication code -- `vmladavx.s32 r0,q1,q2'
|
||||
[^:]*:49: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2'
|
||||
[^:]*:50: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2'
|
||||
[^:]*:52: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2'
|
||||
[^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavaxt.s32 r0,q1,q2'
|
||||
[^:]*:55: Error: instruction missing MVE vector predication code -- `vmladavax.s32 r0,q1,q2'
|
||||
55
gas/testsuite/gas/arm/mve-vmladav-bad.s
Normal file
55
gas/testsuite/gas/arm/mve-vmladav-bad.s
Normal file
@ -0,0 +1,55 @@
|
||||
.macro cond, op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s16 r0, q1, q2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
cond vmladav
|
||||
cond vmladava
|
||||
cond vmladavx
|
||||
cond vmladavax
|
||||
vmladav.s64 r0, q1, q2
|
||||
vmladav.f32 r0, q1, q2
|
||||
vmladava.s64 r0, q1, q2
|
||||
vmladava.f32 r0, q1, q2
|
||||
vmladavx.s64 r0, q1, q2
|
||||
vmladavx.f32 r0, q1, q2
|
||||
vmladavax.s64 r0, q1, q2
|
||||
vmladavax.f32 r0, q1, q2
|
||||
vmladavx.u32 r0, q1, q2
|
||||
vmladavax.u16 r0, q1, q2
|
||||
it eq
|
||||
vmladaveq.s32 r0, q1, q2
|
||||
vmladaveq.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladaveq.s32 r0, q1, q2
|
||||
vmladavt.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladav.s32 r0, q1, q2
|
||||
it eq
|
||||
vmladavaeq.s32 r0, q1, q2
|
||||
vmladavaeq.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladavaeq.s32 r0, q1, q2
|
||||
vmladavat.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladava.s32 r0, q1, q2
|
||||
it eq
|
||||
vmladavxeq.s32 r0, q1, q2
|
||||
vmladavxeq.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladavxeq.s32 r0, q1, q2
|
||||
vmladavxt.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladavx.s32 r0, q1, q2
|
||||
it eq
|
||||
vmladavaxeq.s32 r0, q1, q2
|
||||
vmladavaxeq.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladavaxeq.s32 r0, q1, q2
|
||||
vmladavaxt.s32 r0, q1, q2
|
||||
vpst
|
||||
vmladavax.s32 r0, q1, q2
|
||||
5
gas/testsuite/gas/arm/mve-vmlav-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmlav-bad.d
Normal file
@ -0,0 +1,5 @@
|
||||
#name: Bad MVE VMLAV instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vmlav-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
29
gas/testsuite/gas/arm/mve-vmlav-bad.l
Normal file
29
gas/testsuite/gas/arm/mve-vmlav-bad.l
Normal file
@ -0,0 +1,29 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vmlav.s64 r0,q1,q2'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vmlav.f32 r0,q1,q2'
|
||||
[^:]*:14: Error: bad type in SIMD instruction -- `vmlava.s64 r0,q1,q2'
|
||||
[^:]*:15: Error: bad type in SIMD instruction -- `vmlava.f32 r0,q1,q2'
|
||||
[^:]*:16: Error: bad instruction `vmlavx.s32 r0,q1,q2'
|
||||
[^:]*:17: Error: bad instruction `vmlavax.s32 r0,q1,q2'
|
||||
[^:]*:19: Error: syntax error -- `vmlaveq.s32 r0,q1,q2'
|
||||
[^:]*:20: Error: syntax error -- `vmlaveq.s32 r0,q1,q2'
|
||||
[^:]*:22: Error: syntax error -- `vmlaveq.s32 r0,q1,q2'
|
||||
[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmlavt.s32 r0,q1,q2'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vmlav.s32 r0,q1,q2'
|
||||
[^:]*:27: Error: syntax error -- `vmlavaeq.s32 r0,q1,q2'
|
||||
[^:]*:28: Error: syntax error -- `vmlavaeq.s32 r0,q1,q2'
|
||||
[^:]*:30: Error: syntax error -- `vmlavaeq.s32 r0,q1,q2'
|
||||
[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmlavat.s32 r0,q1,q2'
|
||||
[^:]*:33: Error: instruction missing MVE vector predication code -- `vmlava.s32 r0,q1,q2'
|
||||
33
gas/testsuite/gas/arm/mve-vmlav-bad.s
Normal file
33
gas/testsuite/gas/arm/mve-vmlav-bad.s
Normal file
@ -0,0 +1,33 @@
|
||||
.macro cond, op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s16 r0, q1, q2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
cond vmlav
|
||||
cond vmlava
|
||||
vmlav.s64 r0, q1, q2
|
||||
vmlav.f32 r0, q1, q2
|
||||
vmlava.s64 r0, q1, q2
|
||||
vmlava.f32 r0, q1, q2
|
||||
vmlavx.s32 r0, q1, q2
|
||||
vmlavax.s32 r0, q1, q2
|
||||
it eq
|
||||
vmlaveq.s32 r0, q1, q2
|
||||
vmlaveq.s32 r0, q1, q2
|
||||
vpst
|
||||
vmlaveq.s32 r0, q1, q2
|
||||
vmlavt.s32 r0, q1, q2
|
||||
vpst
|
||||
vmlav.s32 r0, q1, q2
|
||||
it eq
|
||||
vmlavaeq.s32 r0, q1, q2
|
||||
vmlavaeq.s32 r0, q1, q2
|
||||
vpst
|
||||
vmlavaeq.s32 r0, q1, q2
|
||||
vmlavat.s32 r0, q1, q2
|
||||
vpst
|
||||
vmlava.s32 r0, q1, q2
|
||||
5
gas/testsuite/gas/arm/mve-vmlsdav-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmlsdav-bad.d
Normal file
@ -0,0 +1,5 @@
|
||||
#name: Bad MVE VMLSDAV instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vmlsdav-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
47
gas/testsuite/gas/arm/mve-vmlsdav-bad.l
Normal file
47
gas/testsuite/gas/arm/mve-vmlsdav-bad.l
Normal file
@ -0,0 +1,47 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: Odd register not allowed here -- `vmlsdav.s16 r1,q1,q2'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vmlsdav.u16 r0,q1,q2'
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2'
|
||||
[^:]*:18: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2'
|
||||
[^:]*:20: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2'
|
||||
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavt.s16 r0,q1,q2'
|
||||
[^:]*:23: Error: instruction missing MVE vector predication code -- `vmlsdav.s16 r0,q1,q2'
|
||||
[^:]*:25: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2'
|
||||
[^:]*:26: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2'
|
||||
[^:]*:28: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2'
|
||||
[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavat.s16 r0,q1,q2'
|
||||
[^:]*:31: Error: instruction missing MVE vector predication code -- `vmlsdava.s16 r0,q1,q2'
|
||||
[^:]*:33: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2'
|
||||
[^:]*:34: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2'
|
||||
[^:]*:36: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2'
|
||||
[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavxt.s16 r0,q1,q2'
|
||||
[^:]*:39: Error: instruction missing MVE vector predication code -- `vmlsdavx.s16 r0,q1,q2'
|
||||
[^:]*:41: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2'
|
||||
[^:]*:42: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2'
|
||||
[^:]*:44: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2'
|
||||
[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavaxt.s16 r0,q1,q2'
|
||||
[^:]*:47: Error: instruction missing MVE vector predication code -- `vmlsdavax.s16 r0,q1,q2'
|
||||
47
gas/testsuite/gas/arm/mve-vmlsdav-bad.s
Normal file
47
gas/testsuite/gas/arm/mve-vmlsdav-bad.s
Normal file
@ -0,0 +1,47 @@
|
||||
.macro cond, op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s16 r0, q1, q2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vmlsdav.s16 r1, q1, q2
|
||||
vmlsdav.u16 r0, q1, q2
|
||||
cond vmlsdav
|
||||
cond vmlsdava
|
||||
cond vmlsdavx
|
||||
cond vmlsdavax
|
||||
it eq
|
||||
vmlsdaveq.s16 r0, q1, q2
|
||||
vmlsdaveq.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdaveq.s16 r0, q1, q2
|
||||
vmlsdavt.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdav.s16 r0, q1, q2
|
||||
it eq
|
||||
vmlsdavaeq.s16 r0, q1, q2
|
||||
vmlsdavaeq.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdavaeq.s16 r0, q1, q2
|
||||
vmlsdavat.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdava.s16 r0, q1, q2
|
||||
it eq
|
||||
vmlsdavxeq.s16 r0, q1, q2
|
||||
vmlsdavxeq.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdavxeq.s16 r0, q1, q2
|
||||
vmlsdavxt.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdavx.s16 r0, q1, q2
|
||||
it eq
|
||||
vmlsdavaxeq.s16 r0, q1, q2
|
||||
vmlsdavaxeq.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdavaxeq.s16 r0, q1, q2
|
||||
vmlsdavaxt.s16 r0, q1, q2
|
||||
vpst
|
||||
vmlsdavax.s16 r0, q1, q2
|
||||
Loading…
Reference in New Issue
Block a user