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x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL

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For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to
add CheckRegSize to check if broadcast matches the destination register
size.

gas/

	PR gas/24625
	* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
	instructions with invalid broadcast.
	* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
	* testsuite/gas/i386/inval-avx512f.l: Updated.
	* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.

opcodes/

	PR gas/24625
	* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
	Disp8ShiftVL.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu 2019-05-28 10:05:28 -07:00
parent c0e70c624f
commit a2f4b66c9e
8 changed files with 38 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24625
* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
instructions with invalid broadcast.
* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
* testsuite/gas/i386/inval-avx512f.l: Updated.
* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
2019-05-27 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (is_ppc64_target): New function.

5
gas/testsuite/gas/i386/inval-avx512f.l
View File

@ -211,6 +211,8 @@
.*:304: Error: .*masking.*vscatterpf1dps.*
.*:305: Error: .*masking.*vscatterpf1qpd.*
.*:306: Error: .*masking.*vscatterpf1qps.*
.*:308: Error: .*unsupported broadcast for `vdpbf16ps'
.*:309: Error: .*unsupported broadcast for `vcvtne2ps2bf16'
GAS LISTING .*
@ -546,3 +548,6 @@ GAS LISTING .*
[ ]*304[ ]+vscatterpf1dps \(%eax,%zmm1\)\{%k1\}\{z\}
[ ]*305[ ]+vscatterpf1qpd \(%eax,%zmm1\)\{%k1\}\{z\}
[ ]*306[ ]+vscatterpf1qps \(%eax,%zmm1\)\{%k1\}\{z\}
[ ]*307[ ]*
[ ]*308[ ]+vdpbf16ps 8\(%eax\)\{1to8\}, %zmm2, %zmm2
[ ]*309[ ]+vcvtne2ps2bf16 8\(%eax\)\{1to8\}, %zmm2, %zmm2

3
gas/testsuite/gas/i386/inval-avx512f.s
View File

@ -304,3 +304,6 @@ _start:
vscatterpf1dps (%eax,%zmm1){%k1}{z}
vscatterpf1qpd (%eax,%zmm1){%k1}{z}
vscatterpf1qps (%eax,%zmm1){%k1}{z}
vdpbf16ps 8(%eax){1to8}, %zmm2, %zmm2
vcvtne2ps2bf16 8(%eax){1to8}, %zmm2, %zmm2

6
gas/testsuite/gas/i386/x86-64-inval-avx512f.l
View File

@ -39,6 +39,8 @@
.*:55: Error: .*
.*:56: Error: .*
.*:58: Error: .*
.*:61: Error: .*unsupported broadcast for `vdpbf16ps'
.*:62: Error: .*unsupported broadcast for `vcvtne2ps2bf16'
GAS LISTING .*
@ -101,3 +103,7 @@ GAS LISTING .*
[ ]*57[ ]*
GAS LISTING .*
[ ]*58[ ]+vcvtps2qq xmm0, DWORD PTR \[rax\]
[ ]*59[ ]*
[ ]*60[ ]+\.att_syntax prefix
[ ]*61[ ]+vdpbf16ps 8\(%rax\)\{1to8\}, %zmm2, %zmm2
[ ]*62[ ]+vcvtne2ps2bf16 8\(%rax\)\{1to8\}, %zmm2, %zmm2

4
gas/testsuite/gas/i386/x86-64-inval-avx512f.s
View File

@ -56,3 +56,7 @@ _start:
vaddps zmm2{z}, zmm1, zmm0
vcvtps2qq xmm0, DWORD PTR [rax]
.att_syntax prefix
vdpbf16ps 8(%rax){1to8}, %zmm2, %zmm2
vcvtne2ps2bf16 8(%rax){1to8}, %zmm2, %zmm2

7
opcodes/ChangeLog
View File

@ -1,3 +1,10 @@
2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24625
* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
Disp8ShiftVL.
* i386-tbl.h: Regenerated.
2019-05-24 Alan Modra <amodra@gmail.com>
* po/POTFILES.in: Regenerate.

4
opcodes/i386-opc.tbl
View File

@ -4713,7 +4713,7 @@ movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|Cpu64, Modrm|No_bSuf|No_wSuf|No_
// AVX512_BF16 instructions.
vcvtne2ps2bf16, 3, 0xf272, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vcvtne2ps2bf16, 3, 0xf272, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex128|Masking=3|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|BaseIndex, RegXMM }
vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex256|Masking=3|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|BaseIndex, RegXMM }
@ -4722,6 +4722,6 @@ vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|EVex512|Maski
vcvtneps2bf16x, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex128|Masking=3|VexW0|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex, RegXMM }
vcvtneps2bf16y, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex256|Masking=3|VexW0|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex, RegXMM }
vdpbf16ps, 3, 0xf352, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vdpbf16ps, 3, 0xf352, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
// AVX512_BF16 instructions end.

4
opcodes/i386-tbl.h
View File

@ -67651,7 +67651,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
@ -67750,7 +67750,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,