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RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor extension

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T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds configuration-setting instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: New test.
	* testsuite/gas/riscv/x-thead-vector.s: New test.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise..
This commit is contained in:
Jin Ma 2023-11-18 15:04:01 +08:00 committed by Nelson Chu
parent 6fdd02bb1f
commit 9aa5dde64d
3 changed files with 19 additions and 0 deletions
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12
gas/testsuite/gas/riscv/x-thead-vector.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32if_xtheadvector
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu
[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047

3
gas/testsuite/gas/riscv/x-thead-vector.s
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@ -0,0 +1,3 @@
th.vsetvl a0, a1, a2
th.vsetvli a0, a1, 0
th.vsetvli a0, a1, 0x7ff

4
opcodes/riscv-opc.c
View File

@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0},
{"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadVector instructions. */
{"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
{"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
{"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },