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* cgen-dis.in: Include libiberty.h.

Browse Source 
* fr30-desc.c: Regenerate.
	* fr30-dis.c: Regenerate.
	* frv-desc.c: Regenerate.
	* frv-dis.c: Regenerate.
	* ip2k-asm.c: Regenerate.
	* ip2k-desc.c: Regenerate.
	* ip2k-dis.c: Regenerate.
	* ip2k-opc.c: Regenerate.
	* ip2k-opc.h: Regenerate.
	* m32r-desc.c: Regenerate.
	* m32r-dis.c: Regenerate.
	* openrisc-desc.c: Regenerate.
	* openrisc-dis.c: Regenerate.
	* xstormy16-asm.c: Regenerate.
	* xstormy16-desc.c: Regenerate.
	* xstormy16-dis.c: Regenerate.
This commit is contained in:
Alan Modra 2002-12-02 21:58:19 +00:00
parent 4fdf0a751a
commit 98f70fc4f0
17 changed files with 592 additions and 515 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
opcodes/cgen-dis.in
View File

@ -4,7 +4,8 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "@prefix@-desc.h"
#include "@prefix@-opc.h"
#include "opintl.h"

116
opcodes/fr30-desc.c
View File

@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "fr30-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
@ -356,9 +357,9 @@ const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
{
{ 0, &(fr30_cgen_ifld_table[23]) },
{ 0, &(fr30_cgen_ifld_table[24]) },
{0,0}
{ 0, { (const PTR) &fr30_cgen_ifld_table[23] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[24] } },
{ 0, { (const PTR) 0 } }
};
/* The operand table. */
@ -378,201 +379,204 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, &(fr30_cgen_ifld_table[0]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[0] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
{ 0, &(fr30_cgen_ifld_table[10]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[10] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
{ 0, &(fr30_cgen_ifld_table[9]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[9] } },
{ 0, { (1<<MACH_BASE) } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
{ 0, &(fr30_cgen_ifld_table[14]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[14] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
{ 0, &(fr30_cgen_ifld_table[13]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[13] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
{ 0, &(fr30_cgen_ifld_table[16]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[16] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
{ 0, &(fr30_cgen_ifld_table[15]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[15] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
{ 0, &(fr30_cgen_ifld_table[11]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[11] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
{ 0, &(fr30_cgen_ifld_table[12]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[12] } },
{ 0, { (1<<MACH_BASE) } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* R14: General Register 14 */
{ "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* R15: General Register 15 */
{ "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* ps: Program Status register */
{ "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
{ 0, &(fr30_cgen_ifld_table[17]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[17] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
{ 0, &(fr30_cgen_ifld_table[18]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[18] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[21]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[21] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
{ 0, &(fr30_cgen_ifld_table[22]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[22] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
{ 0, &(fr30_cgen_ifld_table[26]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[26] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
{ 0, &(fr30_cgen_ifld_table[27]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[27] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
{ 0, &(fr30_cgen_ifld_table[28]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[28] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
{ 0, &(fr30_cgen_ifld_table[29]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[29] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[30]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[30] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[31]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[31] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
{ 0, &(fr30_cgen_ifld_table[25]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[25] } },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
{ 0, &(fr30_cgen_ifld_table[20]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[20] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
{ 2, &(FR30_F_I20_MULTI_IFIELD[0]) },
{ 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[33]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[33] } },
{ 0, { (1<<MACH_BASE) } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[34]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[34] } },
{ 0, { (1<<MACH_BASE) } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[35]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[35] } },
{ 0, { (1<<MACH_BASE) } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
{ 0, &(fr30_cgen_ifld_table[32]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[32] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
{ 0, &(fr30_cgen_ifld_table[36]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[36] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[40]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[40] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[39]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[39] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[38]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[38] } },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
{ 0, &(fr30_cgen_ifld_table[37]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[37] } },
{ 0, { (1<<MACH_BASE) } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
{ 0, &(fr30_cgen_ifld_table[7]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[7] } },
{ 0, { (1<<MACH_BASE) } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
{ 0, &(fr30_cgen_ifld_table[8]) },
{ 0, { (const PTR) &fr30_cgen_ifld_table[8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* vbit: overflow bit */
{ "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* zbit: zero bit */
{ "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* cbit: carry bit */
{ "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* ibit: interrupt bit */
{ "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sbit: stack bit */
{ "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* tbit: trace trap bit */
{ "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* d0bit: division 0 bit */
{ "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* d1bit: division 1 bit */
{ "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* ccr: condition code bits */
{ "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* scr: system condition bits */
{ "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* ilm: interrupt level mask */
{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
@ -1748,7 +1752,7 @@ fr30_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
@ -1756,7 +1760,7 @@ fr30_cgen_cpu_close (cd)
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}
@ -1766,7 +1770,7 @@ fr30_cgen_cpu_close (cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}

4
opcodes/fr30-dis.c
View File

@ -4,7 +4,8 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "fr30-desc.h"
#include "fr30-opc.h"
#include "opintl.h"

184
opcodes/frv-desc.c
View File

@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "frv-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
@ -1889,21 +1890,21 @@ const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
{
{ 0, &(frv_cgen_ifld_table[46]) },
{ 0, &(frv_cgen_ifld_table[47]) },
{0,0}
{ 0, { (const PTR) &frv_cgen_ifld_table[46] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[47] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
{
{ 0, &(frv_cgen_ifld_table[58]) },
{ 0, &(frv_cgen_ifld_table[59]) },
{0,0}
{ 0, { (const PTR) &frv_cgen_ifld_table[58] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[59] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
{
{ 0, &(frv_cgen_ifld_table[61]) },
{ 0, &(frv_cgen_ifld_table[62]) },
{0,0}
{ 0, { (const PTR) &frv_cgen_ifld_table[61] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[62] } },
{ 0, { (const PTR) 0 } }
};
/* The operand table. */
@ -1923,313 +1924,316 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, &(frv_cgen_ifld_table[0]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[0] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* pack: packing bit */
{ "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
{ 0, &(frv_cgen_ifld_table[2]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[2] } },
{ 0, { (1<<MACH_BASE) } } },
/* GRi: source register 1 */
{ "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
{ 0, &(frv_cgen_ifld_table[8]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[8] } },
{ 0, { (1<<MACH_BASE) } } },
/* GRj: source register 2 */
{ "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
{ 0, &(frv_cgen_ifld_table[9]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[9] } },
{ 0, { (1<<MACH_BASE) } } },
/* GRk: destination register */
{ "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
{ 0, &(frv_cgen_ifld_table[10]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[10] } },
{ 0, { (1<<MACH_BASE) } } },
/* GRkhi: destination register */
{ "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
{ 0, &(frv_cgen_ifld_table[10]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[10] } },
{ 0, { (1<<MACH_BASE) } } },
/* GRklo: destination register */
{ "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
{ 0, &(frv_cgen_ifld_table[10]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[10] } },
{ 0, { (1<<MACH_BASE) } } },
/* GRdoublek: destination register */
{ "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
{ 0, &(frv_cgen_ifld_table[10]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[10] } },
{ 0, { (1<<MACH_BASE) } } },
/* ACC40Si: signed accumulator */
{ "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
{ 0, &(frv_cgen_ifld_table[19]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[19] } },
{ 0, { (1<<MACH_BASE) } } },
/* ACC40Ui: unsigned accumulator */
{ "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
{ 0, &(frv_cgen_ifld_table[20]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[20] } },
{ 0, { (1<<MACH_BASE) } } },
/* ACC40Sk: target accumulator */
{ "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
{ 0, &(frv_cgen_ifld_table[21]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[21] } },
{ 0, { (1<<MACH_BASE) } } },
/* ACC40Uk: target accumulator */
{ "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
{ 0, &(frv_cgen_ifld_table[22]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[22] } },
{ 0, { (1<<MACH_BASE) } } },
/* ACCGi: source register */
{ "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
{ 0, &(frv_cgen_ifld_table[17]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[17] } },
{ 0, { (1<<MACH_BASE) } } },
/* ACCGk: target register */
{ "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
{ 0, &(frv_cgen_ifld_table[18]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[18] } },
{ 0, { (1<<MACH_BASE) } } },
/* CPRi: source register */
{ "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
{ 0, &(frv_cgen_ifld_table[14]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[14] } },
{ 0, { (1<<MACH_FRV) } } },
/* CPRj: source register */
{ "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
{ 0, &(frv_cgen_ifld_table[15]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[15] } },
{ 0, { (1<<MACH_FRV) } } },
/* CPRk: destination register */
{ "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
{ 0, &(frv_cgen_ifld_table[16]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[16] } },
{ 0, { (1<<MACH_FRV) } } },
/* CPRdoublek: destination register */
{ "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
{ 0, &(frv_cgen_ifld_table[16]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[16] } },
{ 0, { (1<<MACH_FRV) } } },
/* FRinti: source register 1 */
{ "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
{ 0, &(frv_cgen_ifld_table[11]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[11] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRintj: source register 2 */
{ "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
{ 0, &(frv_cgen_ifld_table[12]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[12] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRintk: target register */
{ "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
{ 0, &(frv_cgen_ifld_table[13]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[13] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRi: source register 1 */
{ "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
{ 0, &(frv_cgen_ifld_table[11]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[11] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRj: source register 2 */
{ "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
{ 0, &(frv_cgen_ifld_table[12]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[12] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRk: destination register */
{ "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
{ 0, &(frv_cgen_ifld_table[13]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[13] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRkhi: destination register */
{ "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
{ 0, &(frv_cgen_ifld_table[13]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[13] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRklo: destination register */
{ "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
{ 0, &(frv_cgen_ifld_table[13]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[13] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRdoublei: source register 1 */
{ "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
{ 0, &(frv_cgen_ifld_table[11]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[11] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRdoublej: source register 2 */
{ "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
{ 0, &(frv_cgen_ifld_table[12]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[12] } },
{ 0, { (1<<MACH_BASE) } } },
/* FRdoublek: target register */
{ "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
{ 0, &(frv_cgen_ifld_table[13]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[13] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRi: source register 1 */
{ "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
{ 0, &(frv_cgen_ifld_table[23]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[23] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRj: source register 2 */
{ "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
{ 0, &(frv_cgen_ifld_table[24]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[24] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRj_int: destination register */
{ "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
{ 0, &(frv_cgen_ifld_table[27]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[27] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRj_float: destination register */
{ "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
{ 0, &(frv_cgen_ifld_table[28]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[28] } },
{ 0, { (1<<MACH_BASE) } } },
/* CRk: destination register */
{ "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
{ 0, &(frv_cgen_ifld_table[25]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[25] } },
{ 0, { (1<<MACH_BASE) } } },
/* CCi: condition register */
{ "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
{ 0, &(frv_cgen_ifld_table[26]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[26] } },
{ 0, { (1<<MACH_BASE) } } },
/* ICCi_1: condition register */
{ "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
{ 0, &(frv_cgen_ifld_table[29]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[29] } },
{ 0, { (1<<MACH_BASE) } } },
/* ICCi_2: condition register */
{ "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
{ 0, &(frv_cgen_ifld_table[30]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[30] } },
{ 0, { (1<<MACH_BASE) } } },
/* ICCi_3: condition register */
{ "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
{ 0, &(frv_cgen_ifld_table[31]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[31] } },
{ 0, { (1<<MACH_BASE) } } },
/* FCCi_1: condition register */
{ "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
{ 0, &(frv_cgen_ifld_table[32]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[32] } },
{ 0, { (1<<MACH_BASE) } } },
/* FCCi_2: condition register */
{ "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
{ 0, &(frv_cgen_ifld_table[33]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[33] } },
{ 0, { (1<<MACH_BASE) } } },
/* FCCi_3: condition register */
{ "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
{ 0, &(frv_cgen_ifld_table[34]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[34] } },
{ 0, { (1<<MACH_BASE) } } },
/* FCCk: condition register */
{ "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
{ 0, &(frv_cgen_ifld_table[35]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[35] } },
{ 0, { (1<<MACH_BASE) } } },
/* eir: exception insn reg */
{ "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
{ 0, &(frv_cgen_ifld_table[36]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[36] } },
{ 0, { (1<<MACH_BASE) } } },
/* s10: 10 bit signed immediate */
{ "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
{ 0, &(frv_cgen_ifld_table[37]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[37] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u16: 16 bit unsigned immediate */
{ "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
{ 0, &(frv_cgen_ifld_table[40]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[40] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s16: 16 bit signed immediate */
{ "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
{ 0, &(frv_cgen_ifld_table[41]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[41] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s6: 6 bit signed immediate */
{ "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
{ 0, &(frv_cgen_ifld_table[42]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[42] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s6_1: 6 bit signed immediate */
{ "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
{ 0, &(frv_cgen_ifld_table[43]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[43] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u6: 6 bit unsigned immediate */
{ "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
{ 0, &(frv_cgen_ifld_table[44]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[44] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s5: 5 bit signed immediate */
{ "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
{ 0, &(frv_cgen_ifld_table[45]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[45] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* cond: conditional arithmetic */
{ "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
{ 0, &(frv_cgen_ifld_table[50]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[50] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* ccond: lr branch condition */
{ "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
{ 0, &(frv_cgen_ifld_table[51]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[51] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* hint: 2 bit branch predictor */
{ "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
{ 0, &(frv_cgen_ifld_table[52]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[52] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* hint_taken: 2 bit branch predictor */
{ "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
{ 0, &(frv_cgen_ifld_table[52]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[52] } },
{ 0, { (1<<MACH_BASE) } } },
/* hint_not_taken: 2 bit branch predictor */
{ "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
{ 0, &(frv_cgen_ifld_table[52]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[52] } },
{ 0, { (1<<MACH_BASE) } } },
/* LI: link indicator */
{ "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
{ 0, &(frv_cgen_ifld_table[53]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[53] } },
{ 0, { (1<<MACH_BASE) } } },
/* lock: cache lock indicator */
{ "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
{ 0, &(frv_cgen_ifld_table[54]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[54] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* debug: debug mode indicator */
{ "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
{ 0, &(frv_cgen_ifld_table[55]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[55] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* A: all accumulator indicator */
{ "A", FRV_OPERAND_A, HW_H_UINT, 17, 1,
{ 0, &(frv_cgen_ifld_table[56]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[56] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* ae: all entries indicator */
{ "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
{ 0, &(frv_cgen_ifld_table[57]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[57] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* label16: 18 bit pc relative address */
{ "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
{ 0, &(frv_cgen_ifld_table[60]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[60] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* label24: 26 bit pc relative address */
{ "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
{ 2, &(FRV_F_LABEL24_MULTI_IFIELD[0]) },
{ 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* d12: 12 bit signed immediate */
{ "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
{ 0, &(frv_cgen_ifld_table[39]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[39] } },
{ 0, { (1<<MACH_BASE) } } },
/* s12: 12 bit signed immediate */
{ "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
{ 0, &(frv_cgen_ifld_table[39]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[39] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u12: 12 bit signed immediate */
{ "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
{ 2, &(FRV_F_U12_MULTI_IFIELD[0]) },
{ 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* spr: special purpose register */
{ "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
{ 2, &(FRV_F_SPR_MULTI_IFIELD[0]) },
{ 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* ulo16: 16 bit unsigned immediate, for #lo() */
{ "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
{ 0, &(frv_cgen_ifld_table[40]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[40] } },
{ 0, { (1<<MACH_BASE) } } },
/* slo16: 16 bit unsigned immediate, for #lo() */
{ "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
{ 0, &(frv_cgen_ifld_table[41]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[41] } },
{ 0, { (1<<MACH_BASE) } } },
/* uhi16: 16 bit unsigned immediate, for #hi() */
{ "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
{ 0, &(frv_cgen_ifld_table[40]) },
{ 0, { (const PTR) &frv_cgen_ifld_table[40] } },
{ 0, { (1<<MACH_BASE) } } },
/* psr_esr: PSR.ESR bit */
{ "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psr_s: PSR.S bit */
{ "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psr_ps: PSR.PS bit */
{ "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psr_et: PSR.ET bit */
{ "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* bpsr_bs: BPSR.BS bit */
{ "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* bpsr_bet: BPSR.BET bit */
{ "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* tbr_tba: TBR.TBA */
{ "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* tbr_tt: TBR.TT */
{ "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
@ -6270,7 +6274,7 @@ frv_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
@ -6278,7 +6282,7 @@ frv_cgen_cpu_close (cd)
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}
@ -6288,7 +6292,7 @@ frv_cgen_cpu_close (cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}

4
opcodes/frv-dis.c
View File

@ -4,7 +4,8 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "frv-desc.h"
#include "frv-opc.h"
#include "opintl.h"

383
opcodes/ip2k-asm.c
View File

@ -49,6 +49,17 @@ static const char * parse_insn_normal
/* -- asm.c */
#define PARSE_FUNC_DECL(name) \
static const char *name PARAMS ((CGEN_CPU_DESC, const char **, int, long *))
PARSE_FUNC_DECL (parse_fr);
PARSE_FUNC_DECL (parse_addr16);
PARSE_FUNC_DECL (parse_addr16_p);
PARSE_FUNC_DECL (parse_addr16_cjp);
PARSE_FUNC_DECL (parse_lit8);
PARSE_FUNC_DECL (parse_bit3);
static const char *
parse_fr (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
@ -57,12 +68,12 @@ parse_fr (cd, strp, opindex, valuep)
long *valuep;
{
const char *errmsg;
char *old_strp;
const char *old_strp;
char *afteroffset;
enum cgen_parse_operand_result result_type;
bfd_vma value;
extern CGEN_KEYWORD ip2k_cgen_opval_register_names;
long tempvalue;
bfd_vma tempvalue;
old_strp = *strp;
afteroffset = NULL;
@ -71,36 +82,37 @@ parse_fr (cd, strp, opindex, valuep)
/* Check here to see if you're about to try parsing a w as the first arg */
/* and return an error if you are. */
if ( (strncmp(*strp,"w",1)==0) || (strncmp(*strp,"W",1)==0) )
{
(*strp)++;
{
(*strp)++;
if ( (strncmp(*strp,",",1)==0) || isspace(**strp) )
{
/* We've been passed a w. Return with an error message so that */
/* cgen will try the next parsing option. */
errmsg = _("W keyword invalid in FR operand slot.");
return errmsg;
}
*strp = old_strp;
}
if ( (strncmp(*strp,",",1)==0) || ISSPACE(**strp) )
{
/* We've been passed a w. Return with an error message so that */
/* cgen will try the next parsing option. */
errmsg = _("W keyword invalid in FR operand slot.");
return errmsg;
}
*strp = old_strp;
}
/* Attempt parse as register keyword. */
/* old_strp = *strp; */
errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names, valuep);
errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names,
valuep);
if ( *strp != NULL )
if (errmsg == NULL)
return errmsg;
if (errmsg == NULL)
return errmsg;
/* Attempt to parse for "(IP)" */
afteroffset = strstr(*strp,"(IP)");
if ( afteroffset == NULL)
{
/* Make sure it's not in lower case */
afteroffset = strstr(*strp,"(ip)");
}
{
/* Make sure it's not in lower case */
afteroffset = strstr(*strp,"(ip)");
}
if ( afteroffset != NULL )
{
@ -127,42 +139,44 @@ parse_fr (cd, strp, opindex, valuep)
afteroffset = strstr(*strp,"(DP)");
if ( afteroffset == NULL)
{
/* Maybe it's in lower case */
afteroffset = strstr(*strp,"(dp)");
}
{
/* Maybe it's in lower case */
afteroffset = strstr(*strp,"(dp)");
}
if ( afteroffset != NULL )
{
if ( afteroffset == *strp )
{
/* No offset present. Use 0 by default. */
tempvalue = 0;
errmsg = NULL;
}
else
{
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR_OFFSET,
& result_type, & tempvalue);
}
{
if ( afteroffset == *strp )
{
/* No offset present. Use 0 by default. */
tempvalue = 0;
errmsg = NULL;
}
else
{
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_IP2K_FR_OFFSET,
& result_type, & tempvalue);
}
if (errmsg == NULL)
{
if ( (tempvalue >= 0) && (tempvalue <= 127) )
{
/* Value is ok. Fix up the first 2 bits and return */
*valuep = 0x0100 | tempvalue;
*strp += 4; /* skip over the (DP) in *strp */
return errmsg;
} else
{
/* Found something there in front of (DP) but it's out of range. */
errmsg = _("(DP) offset out of range.");
return errmsg;
}
}
}
if (errmsg == NULL)
{
if (tempvalue <= 127)
{
/* Value is ok. Fix up the first 2 bits and return */
*valuep = 0x0100 | tempvalue;
*strp += 4; /* skip over the (DP) in *strp */
return errmsg;
}
else
{
/* Found something there in front of (DP) but it's out
of range. */
errmsg = _("(DP) offset out of range.");
return errmsg;
}
}
}
/* Attempt to parse for SP. ex: mov w, offset(SP) */
@ -172,41 +186,44 @@ parse_fr (cd, strp, opindex, valuep)
afteroffset = strstr(*strp,"(SP)");
if (afteroffset == NULL)
{
/* Maybe it's in lower case. */
afteroffset = strstr(*strp, "(sp)");
}
{
/* Maybe it's in lower case. */
afteroffset = strstr(*strp, "(sp)");
}
if ( afteroffset != NULL )
{
if ( afteroffset == *strp )
{
/* No offset present. Use 0 by default. */
tempvalue = 0;
errmsg = NULL;
}
else
{
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR_OFFSET,
& result_type, & tempvalue);
}
if (errmsg == NULL)
{
if ( (tempvalue >= 0) && (tempvalue <= 127) )
{
/* Value is ok. Fix up the first 2 bits and return */
*valuep = 0x0180 | tempvalue;
*strp += 4; /* skip over the (SP) in *strp */
return errmsg;
} else
{
/* Found something there in front of (SP) but it's out of range. */
errmsg = _("(SP) offset out of range.");
return errmsg;
}
{
if ( afteroffset == *strp )
{
/* No offset present. Use 0 by default. */
tempvalue = 0;
errmsg = NULL;
}
else
{
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_IP2K_FR_OFFSET,
& result_type, & tempvalue);
}
if (errmsg == NULL)
{
if (tempvalue <= 127)
{
/* Value is ok. Fix up the first 2 bits and return */
*valuep = 0x0180 | tempvalue;
*strp += 4; /* skip over the (SP) in *strp */
return errmsg;
}
else
{
/* Found something there in front of (SP) but it's out
of range. */
errmsg = _("(SP) offset out of range.");
return errmsg;
}
}
}
}
}
/* Attempt to parse as an address. */
@ -223,7 +240,8 @@ parse_fr (cd, strp, opindex, valuep)
{
errmsg = _("illegal use of parentheses");
}
/* if a numeric value is specified, ensure that it is between 1 and 255 */
/* if a numeric value is specified, ensure that it is between
1 and 255 */
else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
if (value < 0x1 || value > 0xff)
@ -243,12 +261,12 @@ parse_addr16 (cd, strp, opindex, valuep)
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
long value;
bfd_vma value;
if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16H )
code = BFD_RELOC_IP2K_HI8DATA;
code = BFD_RELOC_IP2K_HI8DATA;
else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16L )
code = BFD_RELOC_IP2K_LO8DATA;
code = BFD_RELOC_IP2K_LO8DATA;
else
{
/* Something is very wrong. opindex has to be one of the above. */
@ -257,93 +275,94 @@ parse_addr16 (cd, strp, opindex, valuep)
}
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
& result_type, & value);
if (errmsg == NULL)
{
/* We either have a relocation or a number now. */
/* We either have a relocation or a number now. */
if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
{
/* We got a number back. */
if ( code == BFD_RELOC_IP2K_HI8DATA )
{
/* We got a number back. */
if ( code == BFD_RELOC_IP2K_HI8DATA )
value >>= 8;
else /* code = BFD_RELOC_IP2K_LOW8DATA */
else /* code = BFD_RELOC_IP2K_LOW8DATA */
value &= 0x00FF;
}
*valuep = value;
}
}
*valuep = value;
}
return errmsg;
}
static const char *
parse_addr16_p (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_IP2K_PAGE3;
long value;
static const char *
parse_addr16_p (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_IP2K_PAGE3;
bfd_vma value;
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if (errmsg == NULL)
{
if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
*valuep = (value >> 13) & 0x7;
else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED )
*valuep = value;
}
return errmsg;
}
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if (errmsg == NULL)
{
if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
*valuep = (value >> 13) & 0x7;
else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED )
*valuep = value;
}
return errmsg;
}
static const char *
parse_addr16_cjp (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
long value;
static const char *
parse_addr16_cjp (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
bfd_vma value;
if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP )
code = BFD_RELOC_IP2K_ADDR16CJP;
else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P )
code = BFD_RELOC_IP2K_PAGE3;
if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP )
code = BFD_RELOC_IP2K_ADDR16CJP;
else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P )
code = BFD_RELOC_IP2K_PAGE3;
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if (errmsg == NULL)
{
if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
{
if ( (value & 0x1) == 0) /* If the address is even .... */
{
if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP )
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if (errmsg == NULL)
{
if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER )
{
if ( (value & 0x1) == 0) /* If the address is even .... */
{
if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP )
*valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */
else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P )
else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P )
*valuep = (value >> 14) & 0x7;
}
}
else
errmsg = _("Byte address required. - must be even.");
}else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED )
{
/* This will happen for things like (s2-s1) where s2 and s1 */
/* are labels. */
*valuep = value;
}
}
else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED )
{
/* This will happen for things like (s2-s1) where s2 and s1
are labels. */
*valuep = value;
}
else
errmsg = _("cgen_parse_address returned a symbol. Literal required.");
}
return errmsg;
}
}
return errmsg;
}
static const char *
@ -356,7 +375,7 @@ parse_lit8 (cd, strp, opindex, valuep)
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
long value;
bfd_vma value;
/* Parse %OP relocating operators. */
if (strncmp (*strp, "%bank", 5) == 0)
@ -444,33 +463,39 @@ parse_bit3 (cd, strp, opindex, valuep)
}
errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
if (errmsg) {
if (errmsg)
return errmsg;
}
if (mode) {
value = (unsigned long) *valuep;
if (value == 0) {
errmsg = _("Attempt to find bit index of 0");
return errmsg;
}
if (mode)
{
value = (unsigned long) *valuep;
if (value == 0)
{
errmsg = _("Attempt to find bit index of 0");
return errmsg;
}
if (mode == 1) {
count = 31;
while ((value & 0x80000000) == 0) {
count--;
value <<= 1;
}
} else if (mode == 2) {
count = 0;
while ((value & 0x00000001) == 0) {
count++;
value >>= 1;
}
}
if (mode == 1)
{
count = 31;
while ((value & 0x80000000) == 0)
{
count--;
value <<= 1;
}
}
else if (mode == 2)
{
count = 0;
while ((value & 0x00000001) == 0)
{
count++;
value >>= 1;
}
}
*valuep = count;
}
*valuep = count;
}
return errmsg;
}

38
opcodes/ip2k-desc.c
View File

@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "ip2k-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
@ -347,57 +348,60 @@ const CGEN_OPERAND ip2k_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, &(ip2k_cgen_ifld_table[0]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[0] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* addr16cjp: 13-bit address */
{ "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
{ 0, &(ip2k_cgen_ifld_table[4]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[4] } },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* fr: register */
{ "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9,
{ 0, &(ip2k_cgen_ifld_table[3]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[3] } },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* lit8: 8-bit signed literal */
{ "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8,
{ 0, &(ip2k_cgen_ifld_table[2]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[2] } },
{ 0, { (1<<MACH_BASE) } } },
/* bitno: bit number */
{ "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
{ 0, &(ip2k_cgen_ifld_table[6]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[6] } },
{ 0, { (1<<MACH_BASE) } } },
/* addr16p: page number */
{ "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
{ 0, &(ip2k_cgen_ifld_table[16]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[16] } },
{ 0, { (1<<MACH_BASE) } } },
/* addr16h: high 8 bits of address */
{ "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
{ 0, &(ip2k_cgen_ifld_table[2]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[2] } },
{ 0, { (1<<MACH_BASE) } } },
/* addr16l: low 8 bits of address */
{ "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
{ 0, &(ip2k_cgen_ifld_table[2]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[2] } },
{ 0, { (1<<MACH_BASE) } } },
/* reti3: reti flags */
{ "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
{ 0, &(ip2k_cgen_ifld_table[14]) },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[14] } },
{ 0, { (1<<MACH_BASE) } } },
/* pabits: page bits */
{ "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* zbit: zero bit */
{ "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* cbit: carry bit */
{ "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* dcbit: digit carry bit */
{ "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
@ -1178,7 +1182,7 @@ ip2k_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
@ -1186,7 +1190,7 @@ ip2k_cgen_cpu_close (cd)
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}
@ -1196,7 +1200,7 @@ ip2k_cgen_cpu_close (cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}

109
opcodes/ip2k-dis.c
View File

@ -4,7 +4,8 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "ip2k-desc.h"
#include "ip2k-opc.h"
#include "opintl.h"
@ -59,14 +61,27 @@ static int read_insn
/* -- dis.c */
#define PRINT_FUNC_DECL(name) \
static void name PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int))
PRINT_FUNC_DECL (print_fr);
PRINT_FUNC_DECL (print_dollarhex);
PRINT_FUNC_DECL (print_dollarhex8);
PRINT_FUNC_DECL (print_dollarhex16);
PRINT_FUNC_DECL (print_dollarhex_addr16h);
PRINT_FUNC_DECL (print_dollarhex_addr16l);
PRINT_FUNC_DECL (print_dollarhex_p);
PRINT_FUNC_DECL (print_dollarhex_cj);
PRINT_FUNC_DECL (print_decimal);
static void
print_fr (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
const CGEN_KEYWORD_ENTRY *ke;
@ -75,33 +90,33 @@ print_fr (cd, dis_info, value, attrs, pc, length)
long offsetvalue;
if ( value == 0 ) /* This is (IP) */
{
{
(*info->fprintf_func) (info->stream, "%s", "(IP)");
return;
}
}
offsettest = value >> 7;
offsetvalue = value & 0x7F;
/* Check to see if first two bits are 10 -> (DP) */
if ( offsettest == 2 )
{
{
if ( offsetvalue == 0 )
(*info->fprintf_func) (info->stream, "%s","(DP)");
(*info->fprintf_func) (info->stream, "%s","(DP)");
else
(*info->fprintf_func) (info->stream, "$%x%s",offsetvalue, "(DP)");
(*info->fprintf_func) (info->stream, "$%x%s",offsetvalue, "(DP)");
return;
}
}
/* Check to see if first two bits are 11 -> (SP) */
if ( offsettest == 3 )
{
{
if ( offsetvalue == 0 )
(*info->fprintf_func) (info->stream, "%s", "(SP)");
(*info->fprintf_func) (info->stream, "%s", "(SP)");
else
(*info->fprintf_func) (info->stream, "$%x%s", offsetvalue,"(SP)");
(*info->fprintf_func) (info->stream, "$%x%s", offsetvalue,"(SP)");
return;
}
}
/* Attempt to print as a register keyword. */
ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value);
@ -117,12 +132,12 @@ print_fr (cd, dis_info, value, attrs, pc, length)
static void
print_dollarhex (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -131,12 +146,12 @@ print_dollarhex (cd, dis_info, value, attrs, pc, length)
static void
print_dollarhex8 (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -145,12 +160,12 @@ print_dollarhex8 (cd, dis_info, value, attrs, pc, length)
static void
print_dollarhex16 (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -159,12 +174,12 @@ print_dollarhex16 (cd, dis_info, value, attrs, pc, length)
static void
print_dollarhex_addr16h (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -177,12 +192,12 @@ print_dollarhex_addr16h (cd, dis_info, value, attrs, pc, length)
static void
print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -191,12 +206,12 @@ print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length)
static void
print_dollarhex_p (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -207,12 +222,12 @@ print_dollarhex_p (cd, dis_info, value, attrs, pc, length)
static void
print_dollarhex_cj (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -223,12 +238,12 @@ print_dollarhex_cj (cd, dis_info, value, attrs, pc, length)
static void
print_decimal (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;

20
opcodes/ip2k-opc.c
View File

@ -32,6 +32,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* -- opc.c */
#include "safe-ctype.h"
/* A better hash function for instruction mnemonics. */
unsigned int
ip2k_asm_hash (insn)
@ -40,8 +42,8 @@ ip2k_asm_hash (insn)
unsigned int hash;
const char* m = insn;
for (hash = 0; *m && !isspace(*m); m++)
hash = (hash * 23) ^ (0x1F & tolower(*m));
for (hash = 0; *m && !ISSPACE(*m); m++)
hash = (hash * 23) ^ (0x1F & TOLOWER(*m));
/* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
@ -49,6 +51,20 @@ ip2k_asm_hash (insn)
}
/* Special check to ensure that instruction exists for given machine. */
int
ip2k_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
const CGEN_INSN *insn;
{
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
/* No mach attribute? Assume it's supported for all machs. */
if (machs == 0)
return 1;
return ((machs & cd->machs) != 0);
}
/* -- asm.c */

21
opcodes/ip2k-opc.h
View File

@ -41,24 +41,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define CGEN_ASM_HASH_SIZE 127
#define CGEN_ASM_HASH(insn) ip2k_asm_hash(insn)
extern unsigned int ip2k_asm_hash (const char *insn);
/* Special check to ensure that instruction exists for given machine. */
static int
ip2k_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
CGEN_INSN *insn;
{
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
/* No mach attribute? Assume it's supported for all machs. */
if (machs == 0)
return 1;
return ((machs & cd->machs) != 0);
}
extern unsigned int ip2k_asm_hash PARAMS ((const char *insn));
extern int ip2k_cgen_insn_supported
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *));
/* -- opc.c */
/* Enum declaration for ip2k instruction types. */

64
opcodes/m32r-desc.c
View File

@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "m32r-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
@ -319,109 +320,112 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, &(m32r_cgen_ifld_table[0]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[0] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: source register */
{ "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
{ 0, &(m32r_cgen_ifld_table[6]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[6] } },
{ 0, { (1<<MACH_BASE) } } },
/* dr: destination register */
{ "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
{ 0, &(m32r_cgen_ifld_table[5]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[5] } },
{ 0, { (1<<MACH_BASE) } } },
/* src1: source register 1 */
{ "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
{ 0, &(m32r_cgen_ifld_table[5]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[5] } },
{ 0, { (1<<MACH_BASE) } } },
/* src2: source register 2 */
{ "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
{ 0, &(m32r_cgen_ifld_table[6]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[6] } },
{ 0, { (1<<MACH_BASE) } } },
/* scr: source control register */
{ "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
{ 0, &(m32r_cgen_ifld_table[6]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[6] } },
{ 0, { (1<<MACH_BASE) } } },
/* dcr: destination control register */
{ "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
{ 0, &(m32r_cgen_ifld_table[5]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[5] } },
{ 0, { (1<<MACH_BASE) } } },
/* simm8: 8 bit signed immediate */
{ "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, &(m32r_cgen_ifld_table[7]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[7] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* simm16: 16 bit signed immediate */
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, &(m32r_cgen_ifld_table[8]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
{ 0, &(m32r_cgen_ifld_table[10]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[10] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm5: 5 bit shift count */
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
{ 0, &(m32r_cgen_ifld_table[11]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[11] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, &(m32r_cgen_ifld_table[12]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[12] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
{ 0, &(m32r_cgen_ifld_table[25]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[25] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
{ 0, &(m32r_cgen_ifld_table[22]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[22] } },
{ 0, { (1<<MACH_M32RX) } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
{ 0, &(m32r_cgen_ifld_table[21]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[21] } },
{ 0, { (1<<MACH_M32RX) } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
{ 0, &(m32r_cgen_ifld_table[20]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[20] } },
{ 0, { (1<<MACH_M32RX) } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
{ 0, &(m32r_cgen_ifld_table[14]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[14] } },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
{ 0, &(m32r_cgen_ifld_table[8]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[8] } },
{ 0, { (1<<MACH_BASE) } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
{ 0, &(m32r_cgen_ifld_table[12]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[12] } },
{ 0, { (1<<MACH_BASE) } } },
/* uimm24: 24 bit address */
{ "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
{ 0, &(m32r_cgen_ifld_table[13]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[13] } },
{ 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* disp8: 8 bit displacement */
{ "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
{ 0, &(m32r_cgen_ifld_table[15]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[15] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp16: 16 bit displacement */
{ "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
{ 0, &(m32r_cgen_ifld_table[16]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[16] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp24: 24 bit displacement */
{ "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
{ 0, &(m32r_cgen_ifld_table[17]) },
{ 0, { (const PTR) &m32r_cgen_ifld_table[17] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* condbit: condition bit */
{ "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* accum: accumulator */
{ "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
@ -1442,7 +1446,7 @@ m32r_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
@ -1450,7 +1454,7 @@ m32r_cgen_cpu_close (cd)
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}
@ -1460,7 +1464,7 @@ m32r_cgen_cpu_close (cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}

4
opcodes/m32r-dis.c
View File

@ -4,7 +4,8 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "m32r-desc.h"
#include "m32r-opc.h"
#include "opintl.h"

50
opcodes/openrisc-desc.c
View File

@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "openrisc-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
@ -263,9 +264,9 @@ const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] =
{
{ 0, &(openrisc_cgen_ifld_table[19]) },
{ 0, &(openrisc_cgen_ifld_table[20]) },
{0,0}
{ 0, { (const PTR) &openrisc_cgen_ifld_table[19] } },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[20] } },
{ 0, { (const PTR) 0 } }
};
/* The operand table. */
@ -285,69 +286,72 @@ const CGEN_OPERAND openrisc_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, &(openrisc_cgen_ifld_table[0]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[0] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: special register */
{ "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* cbit: condition bit */
{ "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* simm-16: 16 bit signed immediate */
{ "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
{ 0, &(openrisc_cgen_ifld_table[7]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[7] } },
{ 0, { (1<<MACH_BASE) } } },
/* uimm-16: 16 bit unsigned immediate */
{ "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
{ 0, &(openrisc_cgen_ifld_table[8]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[8] } },
{ 0, { (1<<MACH_BASE) } } },
/* disp-26: pc-rel 26 bit */
{ "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
{ 0, &(openrisc_cgen_ifld_table[21]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[21] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* abs-26: abs 26 bit */
{ "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
{ 0, &(openrisc_cgen_ifld_table[22]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[22] } },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* uimm-5: imm5 */
{ "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
{ 0, &(openrisc_cgen_ifld_table[9]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[9] } },
{ 0, { (1<<MACH_BASE) } } },
/* rD: destination register */
{ "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
{ 0, &(openrisc_cgen_ifld_table[4]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[4] } },
{ 0, { (1<<MACH_BASE) } } },
/* rA: source register A */
{ "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
{ 0, &(openrisc_cgen_ifld_table[5]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[5] } },
{ 0, { (1<<MACH_BASE) } } },
/* rB: source register B */
{ "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
{ 0, &(openrisc_cgen_ifld_table[6]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[6] } },
{ 0, { (1<<MACH_BASE) } } },
/* op-f-23: f-op23 */
{ "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
{ 0, &(openrisc_cgen_ifld_table[15]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[15] } },
{ 0, { (1<<MACH_BASE) } } },
/* op-f-3: f-op3 */
{ "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
{ 0, &(openrisc_cgen_ifld_table[16]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[16] } },
{ 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
{ 0, &(openrisc_cgen_ifld_table[7]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[7] } },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* lo16: low 16 bit immediate, sign optional */
{ "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
{ 0, &(openrisc_cgen_ifld_table[11]) },
{ 0, { (const PTR) &openrisc_cgen_ifld_table[11] } },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* ui16nc: 16 bit immediate, sign optional */
{ "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
{ 2, &(OPENRISC_F_I16NC_MULTI_IFIELD[0]) },
{ 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } },
{ 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
@ -1018,7 +1022,7 @@ openrisc_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
@ -1026,7 +1030,7 @@ openrisc_cgen_cpu_close (cd)
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}
@ -1036,7 +1040,7 @@ openrisc_cgen_cpu_close (cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}

4
opcodes/openrisc-dis.c
View File

@ -4,7 +4,8 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "openrisc-desc.h"
#include "openrisc-opc.h"
#include "opintl.h"

2
opcodes/xstormy16-asm.c
View File

@ -73,7 +73,7 @@ parse_mem8 (cd, strp, opindex, valuep)
if (s[1] == '-' && s[2] == '-')
return _("Bad register in preincrement");
while (isalnum (*++s))
while (ISALNUM (*++s))
;
if (s[0] == '+' && s[1] == '+' && (s[2] == ')' || s[2] == ','))
return _("Bad register in postincrement");

96
opcodes/xstormy16-desc.c
View File

@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "xstormy16-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
@ -312,9 +313,9 @@ const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
{
{ 0, &(xstormy16_cgen_ifld_table[34]) },
{ 0, &(xstormy16_cgen_ifld_table[35]) },
{0,0}
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[34] } },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[35] } },
{ 0, { (const PTR) 0 } }
};
/* The operand table. */
@ -334,161 +335,164 @@ const CGEN_OPERAND xstormy16_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, &(xstormy16_cgen_ifld_table[0]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[0] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-z8: */
{ "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-z16: */
{ "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-cy: */
{ "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-hc: */
{ "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-ov: */
{ "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-pt: */
{ "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-s: */
{ "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Rd: general register destination */
{ "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
{ 0, &(xstormy16_cgen_ifld_table[2]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[2] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rdm: general register destination */
{ "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
{ 0, &(xstormy16_cgen_ifld_table[3]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[3] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rm: general register for memory */
{ "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
{ 0, &(xstormy16_cgen_ifld_table[4]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[4] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rs: general register source */
{ "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
{ 0, &(xstormy16_cgen_ifld_table[5]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[5] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rb: base register */
{ "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
{ 0, &(xstormy16_cgen_ifld_table[6]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[6] } },
{ 0, { (1<<MACH_BASE) } } },
/* Rbj: base register for jump */
{ "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
{ 0, &(xstormy16_cgen_ifld_table[7]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[7] } },
{ 0, { (1<<MACH_BASE) } } },
/* bcond2: branch condition opcode */
{ "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
{ 0, &(xstormy16_cgen_ifld_table[9]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[9] } },
{ 0, { (1<<MACH_BASE) } } },
/* ws2: word size opcode */
{ "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
{ 0, &(xstormy16_cgen_ifld_table[11]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[11] } },
{ 0, { (1<<MACH_BASE) } } },
/* bcond5: branch condition opcode */
{ "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
{ 0, &(xstormy16_cgen_ifld_table[18]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[18] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm2: 2 bit unsigned immediate */
{ "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
{ 0, &(xstormy16_cgen_ifld_table[21]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[21] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm3: 3 bit unsigned immediate */
{ "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
{ 0, &(xstormy16_cgen_ifld_table[22]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[22] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm3b: 3 bit unsigned immediate for bit tests */
{ "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
{ 0, &(xstormy16_cgen_ifld_table[23]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[23] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm4: 4 bit unsigned immediate */
{ "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
{ 0, &(xstormy16_cgen_ifld_table[24]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[24] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm8: 8 bit unsigned immediate */
{ "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
{ 0, &(xstormy16_cgen_ifld_table[25]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[25] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm8small: 8 bit unsigned immediate */
{ "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
{ 0, &(xstormy16_cgen_ifld_table[25]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[25] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm12: 12 bit signed immediate */
{ "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
{ 0, &(xstormy16_cgen_ifld_table[26]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[26] } },
{ 0, { (1<<MACH_BASE) } } },
/* imm16: 16 bit immediate */
{ "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
{ 0, &(xstormy16_cgen_ifld_table[27]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[27] } },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* lmem8: 8 bit unsigned immediate low memory */
{ "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
{ 0, &(xstormy16_cgen_ifld_table[28]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[28] } },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* hmem8: 8 bit unsigned immediate high memory */
{ "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
{ 0, &(xstormy16_cgen_ifld_table[29]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[29] } },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* rel8-2: 8 bit relative address */
{ "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
{ 0, &(xstormy16_cgen_ifld_table[30]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[30] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* rel8-4: 8 bit relative address */
{ "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
{ 0, &(xstormy16_cgen_ifld_table[31]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[31] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* rel12: 12 bit relative address */
{ "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
{ 0, &(xstormy16_cgen_ifld_table[32]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[32] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* rel12a: 12 bit relative address */
{ "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
{ 0, &(xstormy16_cgen_ifld_table[33]) },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[33] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* abs24: 24 bit absolute address */
{ "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
{ 2, &(XSTORMY16_F_ABS24_MULTI_IFIELD[0]) },
{ 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* psw: program status word */
{ "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Rpsw: N0-N3 of the program status word */
{ "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sp: stack pointer */
{ "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R0: R0 */
{ "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R1: R1 */
{ "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R2: R2 */
{ "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R8: R8 */
{ "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
{ 0, 0 },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
@ -1474,7 +1478,7 @@ xstormy16_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
CGEN_INSN *insns;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
@ -1482,7 +1486,7 @@ xstormy16_cgen_cpu_close (cd)
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}
@ -1492,7 +1496,7 @@ xstormy16_cgen_cpu_close (cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree(CGEN_INSN_RX (insns));
regfree (CGEN_INSN_RX (insns));
}
}

4
opcodes/xstormy16-dis.c
View File

@ -4,7 +4,8 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "xstormy16-desc.h"
#include "xstormy16-opc.h"
#include "opintl.h"