From 97f4d183416b7319db0a2c44296e4b677a17d956 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Tue, 21 Apr 1998 04:30:27 +0000 Subject: [PATCH] Implement ERET instruction. Add {signed,unsigned}_address type. --- sim/common/ChangeLog | 9 ++++++++ sim/common/sim-types.h | 23 ++++++++++++++++---- sim/mips/ChangeLog | 13 +++++++++++ sim/mips/interp.c | 49 +++++++++++++++++++++++++++++++----------- sim/mips/mips.igen | 20 +++++++++++++++++ 5 files changed, 98 insertions(+), 16 deletions(-) diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index fa67c10b2e1..59dd8ccaf4a 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,12 @@ +Tue Apr 21 13:18:41 1998 Andrew Cagney + + * sim-types.h (signed_address, unsigned_address): Define. + +Mon Apr 20 21:47:54 1998 Andrew Cagney + + * sim-fpu.c (sim_fpu_2d): Don't return an SNaN, convert it into a + QNaN. + Thu Apr 16 10:30:14 1998 Andrew Cagney * sim-fpu.c, sim-fpu.h (sim_fpu_fractionto, sim_fpu_tofraction): diff --git a/sim/common/sim-types.h b/sim/common/sim-types.h index ddf90957086..3b6d6ad2852 100644 --- a/sim/common/sim-types.h +++ b/sim/common/sim-types.h @@ -65,15 +65,18 @@ typedef unsigned long unsigned32; #if defined __GNUC__ || defined _MSC_VER #ifdef __GNUC__ +/* GDB sometimes likes to make what appear to be signed `0x*L' values + unsigned by default */ + typedef long long natural64; typedef signed long long signed64; typedef unsigned long long unsigned64; #define UNSIGNED64(X) (X##ULL) -#define SIGNED64(X) (X##LL) +#define SIGNED64(X) ((signed64) X##LL) #define UNSIGNED32(X) (X##UL) -#define SIGNED32(X) (X##L) +#define SIGNED32(X) ((signed32) X##L) #else /* _MSC_VER */ @@ -137,11 +140,14 @@ typedef signed32 signed_word; /* Other instructions */ #if (WITH_TARGET_ADDRESS_BITSIZE == 64) -typedef unsigned64 address_word; +typedef unsigned64 unsigned_address; +typedef signed64 signed_address; #endif #if (WITH_TARGET_ADDRESS_BITSIZE == 32) -typedef unsigned32 address_word; +typedef unsigned32 unsigned_address; +typedef signed32 signed_address; #endif +typedef unsigned_address address_word; /* IEEE 1275 cell size */ #if (WITH_TARGET_CELL_BITSIZE == 64) @@ -155,4 +161,13 @@ typedef unsigned32 unsigned_cell; typedef signed32 signed_cell; #endif +/* Floating point registers */ +#if (WITH_TARGET_FLOATING_POINT_BITSIZE == 64) +typedef unsigned64 fp_word; +#endif +#if (WITH_TARGET_FLOATING_POINT_BITSIZE == 32) +typedef unsigned32 fp_word; +#endif + + #endif /* _SIM_TYPES_H_ */ diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index f1725ab4265..f183029f483 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,16 @@ +Tue Apr 21 11:59:50 1998 Andrew Cagney + + * mips.igen (ERET): Implement. + + * interp.c (decode_coproc): Return sign-extended EPC. + + * mips.igen (ANDI, LUI, MFC0): Add tracing code. + + * interp.c (signal_exception): Do not ignore Trap. + (signal_exception): On TRAP, restart at exception address. + (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. + (signal_exception): Update. + Mon Apr 20 11:26:55 1998 Andrew Cagney * sim-main.h (struct hilo_access, struct hilo_history): Define, diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 612b73b1a1d..73143882dcb 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -100,6 +100,7 @@ char* pr_uword64 PARAMS ((uword64 addr)); /* The following reserved instruction value is used when a simulator trap is required. NOTE: Care must be taken, since this value may be used in later revisions of the MIPS ISA. */ + #define RSVD_INSTRUCTION (0x00000005) #define RSVD_INSTRUCTION_MASK (0xFC00003F) @@ -107,6 +108,13 @@ char* pr_uword64 PARAMS ((uword64 addr)); #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF +/* The following reserved instruction value is used when a simulator + halt is required. NOTE: Care must be taken, since this value may + be used in later revisions of the MIPS ISA. */ +#define HALT_INSTRUCTION (0x03ff000d) +#define HALT_INSTRUCTION_MASK (0x03FFFFC0) + + /* Bits in the Debug register */ #define Debug_DBD 0x80000000 /* Debug Branch Delay */ #define Debug_DM 0x40000000 /* Debug Mode */ @@ -455,6 +463,19 @@ sim_open (kind, cb, abfd, argv) open_trace(sd); #endif /* TRACE */ + /* Write an abort sequence into the TRAP (common) exception vector + addresses. This is to catch code executing a TRAP (et.al.) + instruction without installing a trap handler. */ + { + unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */, + HALT_INSTRUCTION /* BREAK */ }; + H2T (halt[0]); + H2T (halt[1]); + sim_write (sd, 0x80000180, (char *) halt, sizeof (halt)); + sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt)); + } + + /* Write the monitor trap address handlers into the monitor (eeprom) address space. This can only be done once the target endianness has been determined. */ @@ -1574,13 +1595,6 @@ signal_exception (SIM_DESC sd, LLBIT = 0; switch (exception) { - /* TODO: For testing purposes I have been ignoring TRAPs. In - reality we should either simulate them, or allow the user to - ignore them at run-time. - Same for SYSCALL */ - case Trap : - sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); - break; case SystemCall : { @@ -1668,14 +1682,16 @@ signal_exception (SIM_DESC sd, { va_list ap; unsigned int instruction; - va_start(ap,exception); + va_start(ap, exception); instruction = va_arg(ap,unsigned int); va_end(ap); /* Check for our special terminating BREAK: */ - if ((instruction & 0x03FFFFC0) == 0x03ff0000) { - sim_engine_halt (SD, CPU, NULL, cia, - sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); - } + if ((instruction & HALT_INSTRUCTION_MASK) + == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK)) + { + sim_engine_halt (SD, CPU, NULL, cia, + sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); + } } if (STATE & simDELAYSLOT) PC = cia - 4; /* reference the branch instruction */ @@ -1751,6 +1767,9 @@ signal_exception (SIM_DESC sd, sim_stopped, SIM_SIGFPE); case Trap: + sim_engine_restart (SD, CPU, NULL, PC); + break; + case Watch: case SystemCall: PC = EPC; @@ -3140,6 +3159,12 @@ decode_coproc (SIM_DESC sd, CAUSE = GPR[rt]; break; /* 14 = EPC R4000 VR4100 VR4300 */ + case 14: + if (code == 0x00) + GPR[rt] = (signed_word) (signed_address) EPC; + else + EPC = GPR[rt]; + break; /* 15 = PRId R4000 VR4100 VR4300 */ #ifdef SUBTARGET_R3900 /* 16 = Debug */ diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 89c1986defe..4050a2c730e 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -349,7 +349,9 @@ *tx19: // end-sanitize-tx19 { + TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); GPR[RT] = GPR[RS] & IMMEDIATE; + TRACE_ALU_RESULT (GPR[RT]); } @@ -1933,7 +1935,9 @@ *tx19: // end-sanitize-tx19 { + TRACE_ALU_INPUT1 (IMMEDIATE); GPR[RT] = EXTEND32 (IMMEDIATE << 16); + TRACE_ALU_RESULT (GPR[RT]); } @@ -5288,6 +5292,20 @@ // start-sanitize-r5900 *r5900: // end-sanitize-r5900 +{ + if (SR & status_ERL) + { + /* Oops, not yet available */ + sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); + NIA = EPC; + SR &= ~status_ERL; + } + else + { + NIA = EPC; + SR &= ~status_EXL; + } +} 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 @@ -5304,7 +5322,9 @@ *r5900: // end-sanitize-r5900 { + TRACE_ALU_INPUT0 (); DecodeCoproc (instruction_0); + TRACE_ALU_RESULT (GPR[RT]); } 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0