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Implement ERET instruction.
Add {signed,unsigned}_address type.
This commit is contained in:
Andrew Cagney
parent
421cbaae98
commit
97f4d18341
@ -1,3 +1,12 @@
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Tue Apr 21 13:18:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-types.h (signed_address, unsigned_address): Define.
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Mon Apr 20 21:47:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-fpu.c (sim_fpu_2d): Don't return an SNaN, convert it into a
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QNaN.
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Thu Apr 16 10:30:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-fpu.c, sim-fpu.h (sim_fpu_fractionto, sim_fpu_tofraction):
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@ -65,15 +65,18 @@ typedef unsigned long unsigned32;
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#if defined __GNUC__ || defined _MSC_VER
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#ifdef __GNUC__
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/* GDB sometimes likes to make what appear to be signed `0x*L' values
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unsigned by default */
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typedef long long natural64;
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typedef signed long long signed64;
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typedef unsigned long long unsigned64;
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#define UNSIGNED64(X) (X##ULL)
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#define SIGNED64(X) (X##LL)
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#define SIGNED64(X) ((signed64) X##LL)
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#define UNSIGNED32(X) (X##UL)
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#define SIGNED32(X) (X##L)
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#define SIGNED32(X) ((signed32) X##L)
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#else /* _MSC_VER */
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@ -137,11 +140,14 @@ typedef signed32 signed_word;
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/* Other instructions */
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#if (WITH_TARGET_ADDRESS_BITSIZE == 64)
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typedef unsigned64 address_word;
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typedef unsigned64 unsigned_address;
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typedef signed64 signed_address;
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#endif
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#if (WITH_TARGET_ADDRESS_BITSIZE == 32)
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typedef unsigned32 address_word;
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typedef unsigned32 unsigned_address;
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typedef signed32 signed_address;
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#endif
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typedef unsigned_address address_word;
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/* IEEE 1275 cell size */
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#if (WITH_TARGET_CELL_BITSIZE == 64)
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@ -155,4 +161,13 @@ typedef unsigned32 unsigned_cell;
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typedef signed32 signed_cell;
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#endif
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/* Floating point registers */
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#if (WITH_TARGET_FLOATING_POINT_BITSIZE == 64)
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typedef unsigned64 fp_word;
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#endif
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#if (WITH_TARGET_FLOATING_POINT_BITSIZE == 32)
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typedef unsigned32 fp_word;
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#endif
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#endif /* _SIM_TYPES_H_ */
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@ -1,3 +1,16 @@
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Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen (ERET): Implement.
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* interp.c (decode_coproc): Return sign-extended EPC.
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* mips.igen (ANDI, LUI, MFC0): Add tracing code.
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* interp.c (signal_exception): Do not ignore Trap.
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(signal_exception): On TRAP, restart at exception address.
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(HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
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(signal_exception): Update.
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Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-main.h (struct hilo_access, struct hilo_history): Define,
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@ -100,6 +100,7 @@ char* pr_uword64 PARAMS ((uword64 addr));
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/* The following reserved instruction value is used when a simulator
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trap is required. NOTE: Care must be taken, since this value may be
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used in later revisions of the MIPS ISA. */
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#define RSVD_INSTRUCTION (0x00000005)
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#define RSVD_INSTRUCTION_MASK (0xFC00003F)
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@ -107,6 +108,13 @@ char* pr_uword64 PARAMS ((uword64 addr));
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#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
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/* The following reserved instruction value is used when a simulator
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halt is required. NOTE: Care must be taken, since this value may
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be used in later revisions of the MIPS ISA. */
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#define HALT_INSTRUCTION (0x03ff000d)
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#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
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/* Bits in the Debug register */
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#define Debug_DBD 0x80000000 /* Debug Branch Delay */
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#define Debug_DM 0x40000000 /* Debug Mode */
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@ -455,6 +463,19 @@ sim_open (kind, cb, abfd, argv)
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open_trace(sd);
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#endif /* TRACE */
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/* Write an abort sequence into the TRAP (common) exception vector
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addresses. This is to catch code executing a TRAP (et.al.)
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instruction without installing a trap handler. */
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{
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unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
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HALT_INSTRUCTION /* BREAK */ };
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H2T (halt[0]);
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H2T (halt[1]);
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sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
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sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
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}
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/* Write the monitor trap address handlers into the monitor (eeprom)
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address space. This can only be done once the target endianness
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has been determined. */
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@ -1574,13 +1595,6 @@ signal_exception (SIM_DESC sd,
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LLBIT = 0;
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switch (exception) {
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/* TODO: For testing purposes I have been ignoring TRAPs. In
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reality we should either simulate them, or allow the user to
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ignore them at run-time.
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Same for SYSCALL */
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case Trap :
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sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
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break;
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case SystemCall :
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{
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@ -1668,14 +1682,16 @@ signal_exception (SIM_DESC sd,
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{
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va_list ap;
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unsigned int instruction;
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va_start(ap,exception);
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va_start(ap, exception);
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instruction = va_arg(ap,unsigned int);
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va_end(ap);
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/* Check for our special terminating BREAK: */
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if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
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sim_engine_halt (SD, CPU, NULL, cia,
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sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
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}
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if ((instruction & HALT_INSTRUCTION_MASK)
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== (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK))
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{
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sim_engine_halt (SD, CPU, NULL, cia,
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sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
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}
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}
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if (STATE & simDELAYSLOT)
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PC = cia - 4; /* reference the branch instruction */
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@ -1751,6 +1767,9 @@ signal_exception (SIM_DESC sd,
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sim_stopped, SIM_SIGFPE);
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case Trap:
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sim_engine_restart (SD, CPU, NULL, PC);
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break;
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case Watch:
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case SystemCall:
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PC = EPC;
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@ -3140,6 +3159,12 @@ decode_coproc (SIM_DESC sd,
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CAUSE = GPR[rt];
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break;
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/* 14 = EPC R4000 VR4100 VR4300 */
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case 14:
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if (code == 0x00)
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GPR[rt] = (signed_word) (signed_address) EPC;
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else
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EPC = GPR[rt];
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break;
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/* 15 = PRId R4000 VR4100 VR4300 */
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#ifdef SUBTARGET_R3900
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/* 16 = Debug */
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@ -349,7 +349,9 @@
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*tx19:
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// end-sanitize-tx19
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{
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TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
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GPR[RT] = GPR[RS] & IMMEDIATE;
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TRACE_ALU_RESULT (GPR[RT]);
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}
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@ -1933,7 +1935,9 @@
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*tx19:
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// end-sanitize-tx19
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{
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TRACE_ALU_INPUT1 (IMMEDIATE);
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GPR[RT] = EXTEND32 (IMMEDIATE << 16);
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TRACE_ALU_RESULT (GPR[RT]);
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}
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@ -5288,6 +5292,20 @@
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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if (SR & status_ERL)
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{
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/* Oops, not yet available */
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sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
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NIA = EPC;
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SR &= ~status_ERL;
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}
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else
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{
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NIA = EPC;
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SR &= ~status_EXL;
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}
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}
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010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
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@ -5304,7 +5322,9 @@
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*r5900:
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// end-sanitize-r5900
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{
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TRACE_ALU_INPUT0 ();
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DecodeCoproc (instruction_0);
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TRACE_ALU_RESULT (GPR[RT]);
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}
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010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
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