mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-26 18:03:33 +08:00
* Makefile.in: Get rid of srcroot. Set all INSTALL macros via
autoconf. * gencode.c (write_opcodes): Pad operands field to account for MSVC braindamage. * simops.c: Include errno.h. Exclude SYS_chown, since MSVC doesn't support it. (Why is this here in the first place?!?) * v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's. Change number of operands in struct simops from 9 to 6. Define SIGTRAP and SIGQUIT for MSVC.
This commit is contained in:
Stu Grossman
parent
139e2c0f92
commit
968519095a
@ -1,3 +1,15 @@
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Thu Oct 24 10:33:33 1996 Stu Grossman (grossman@critters.cygnus.com)
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* Makefile.in: Get rid of srcroot. Set all INSTALL macros via
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autoconf.
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* gencode.c (write_opcodes): Pad operands field to account for
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MSVC braindamage.
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* simops.c: Include errno.h. Exclude SYS_chown, since MSVC
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doesn't support it. (Why is this here in the first place?!?)
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* v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's.
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Change number of operands in struct simops from 9 to 6. Define
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SIGTRAP and SIGQUIT for MSVC.
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Tue Oct 15 16:19:51 1996 Stu Grossman (grossman@critters.cygnus.com)
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* interp.c (MEM_SIZE): It's now bytes, not a power of 2.
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@ -86,6 +86,7 @@ write_opcodes ()
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{
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struct v850_opcode *opcode;
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int i, j;
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int numops;
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/* write out opcode table */
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printf ("#include \"v850_sim.h\"\n");
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@ -111,6 +112,7 @@ write_opcodes ()
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printf ("%d,{",j);
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j = 0;
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numops = 0;
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for (i = 0; i < 6; i++)
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{
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int flags = v850_operands[opcode->operands[i]].flags;
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@ -123,9 +125,19 @@ write_opcodes ()
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printf ("%d,%d,%d", shift,
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v850_operands[opcode->operands[i]].bits,flags);
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j = 1;
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numops++;
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}
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}
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switch (numops)
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{
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case 0:
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printf ("0,0,0");
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case 1:
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printf (",0,0,0");
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}
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printf ("}},\n");
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}
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printf ("{ 0,0,NULL,0,{ }},\n};\n");
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printf ("{ 0,0,NULL,0,{0,0,0,0,0,0}},\n};\n");
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}
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@ -3,6 +3,7 @@
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#include "simops.h"
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#include "sys/syscall.h"
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#include "bfd.h"
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#include <errno.h>
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enum op_types {
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OP_UNKNOWN,
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@ -150,7 +151,7 @@ trace_input (name, type, size)
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case OP_IMM_REG:
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case OP_IMM_REG_CMP:
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case OP_IMM_REG_MOVE:
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sprintf (buf, "%d,r%d", OP[1], OP[0]);
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sprintf (buf, "%d,r%d", OP[0], OP[1]);
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break;
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case OP_COND_BR:
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@ -166,11 +167,11 @@ trace_input (name, type, size)
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break;
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case OP_LOAD32:
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sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]), OP[0], OP[1]);
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sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
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break;
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case OP_STORE32:
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sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2]), OP[0]);
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sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
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break;
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case OP_JUMP:
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@ -424,7 +425,7 @@ OP_300 ()
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temp = OP[1];
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temp = SEXT7 (temp);
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op2 = temp;
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result = get_byte (State.mem + State.regs[30] + op2);
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result = load_mem (State.regs[30] + op2, 1);
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State.regs[OP[0]] = SEXT8 (result);
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trace_output (OP_LOAD16);
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}
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@ -440,7 +441,7 @@ OP_400 ()
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temp = OP[1];
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temp = SEXT7 (temp);
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op2 = temp << 1;
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result = get_half (State.mem + State.regs[30] + op2);
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result = load_mem (State.regs[30] + op2, 2);
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State.regs[OP[0]] = SEXT16 (result);
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trace_output (OP_LOAD16);
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}
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@ -456,7 +457,7 @@ OP_500 ()
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temp = OP[1];
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temp = SEXT7 (temp);
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op2 = temp << 2;
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result = get_word (State.mem + State.regs[30] + op2);
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result = load_mem (State.regs[30] + op2, 4);
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State.regs[OP[0]] = result;
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trace_output (OP_LOAD16);
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}
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@ -473,7 +474,7 @@ OP_380 ()
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temp = OP[1];
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temp = SEXT7 (temp);
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op1 = temp;
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put_byte (State.mem + State.regs[30] + op1, op0);
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store_mem (State.regs[30] + op1, 1, op0);
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trace_output (OP_STORE16);
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}
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@ -489,7 +490,7 @@ OP_480 ()
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temp = OP[1];
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temp = SEXT7 (temp);
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op1 = temp << 1;
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put_half (State.mem + State.regs[30] + op1, op0);
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store_mem (State.regs[30] + op1, 2, op0);
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trace_output (OP_STORE16);
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}
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@ -505,7 +506,7 @@ OP_501 ()
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temp = OP[1];
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temp = SEXT7 (temp);
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op1 = temp << 2;
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put_word (State.mem + State.regs[30] + op1, op0);
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store_mem (State.regs[30] + op1, 4, op0);
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trace_output (OP_STORE16);
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}
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@ -520,7 +521,7 @@ OP_700 ()
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op0 = State.regs[OP[0]];
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temp = SEXT16 (OP[2]);
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op2 = temp;
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result = get_byte (State.mem + op0 + op2);
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result = load_mem (op0 + op2, 1);
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State.regs[OP[1]] = SEXT8 (result);
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trace_output (OP_LOAD32);
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}
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@ -537,7 +538,7 @@ OP_720 ()
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temp = SEXT16 (OP[2]);
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temp &= ~0x1;
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op2 = temp;
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result = get_half (State.mem + op0 + op2);
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result = load_mem (op0 + op2, 2);
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State.regs[OP[1]] = SEXT16 (result);
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trace_output (OP_LOAD32);
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}
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@ -554,7 +555,7 @@ OP_10720 ()
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temp = SEXT16 (OP[2]);
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temp &= ~0x1;
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op2 = temp;
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result = get_word (State.mem + op0 + op2);
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result = load_mem (op0 + op2, 4);
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State.regs[OP[1]] = result;
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trace_output (OP_LOAD32);
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}
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@ -571,7 +572,7 @@ OP_740 ()
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op1 = State.regs[OP[1]];
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temp = SEXT16 (OP[2]);
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op2 = temp;
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put_byte (State.mem + op0 + op2, op1);
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store_mem (op0 + op2, 1, op1);
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trace_output (OP_STORE32);
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}
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@ -587,7 +588,7 @@ OP_760 ()
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op1 = State.regs[OP[1]];
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temp = SEXT16 (OP[2] & ~0x1);
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op2 = temp;
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put_half (State.mem + op0 + op2, op1);
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store_mem (op0 + op2, 2, op1);
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trace_output (OP_STORE32);
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}
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@ -603,7 +604,7 @@ OP_10760 ()
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op1 = State.regs[OP[1]];
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temp = SEXT16 (OP[2] & ~0x1);
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op2 = temp;
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put_word (State.mem + op0 + op2, op1);
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store_mem (op0 + op2, 4, op1);
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trace_output (OP_STORE32);
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}
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@ -1828,12 +1829,12 @@ OP_7C0 ()
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op1 = OP[1] & 0x7;
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temp = SEXT16 (OP[2]);
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op2 = temp;
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temp = get_byte (State.mem + op0 + op2);
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temp = load_mem (op0 + op2, 1);
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State.sregs[5] &= ~PSW_Z;
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if ((temp & (1 << op1)) == 0)
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State.sregs[5] |= PSW_Z;
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temp |= (1 << op1);
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put_byte (State.mem + op0 + op2, temp);
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store_mem (op0 + op2, 1, temp);
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trace_output (OP_BIT);
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}
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@ -1849,12 +1850,12 @@ OP_47C0 ()
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op1 = OP[1] & 0x7;
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temp = SEXT16 (OP[2]);
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op2 = temp;
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temp = get_byte (State.mem + op0 + op2);
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temp = load_mem (op0 + op2, 1);
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State.sregs[5] &= ~PSW_Z;
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if ((temp & (1 << op1)) == 0)
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State.sregs[5] |= PSW_Z;
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temp ^= (1 << op1);
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put_byte (State.mem + op0 + op2, temp);
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store_mem (op0 + op2, 1, temp);
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trace_output (OP_BIT);
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}
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@ -1870,12 +1871,12 @@ OP_87C0 ()
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op1 = OP[1] & 0x7;
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temp = SEXT16 (OP[2]);
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op2 = temp;
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temp = get_byte (State.mem + op0 + op2);
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temp = load_mem (op0 + op2, 1);
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State.sregs[5] &= ~PSW_Z;
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if ((temp & (1 << op1)) == 0)
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State.sregs[5] |= PSW_Z;
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temp &= ~(1 << op1);
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put_byte (State.mem + op0 + op2, temp);
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store_mem (op0 + op2, 1, temp);
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trace_output (OP_BIT);
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}
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@ -1891,7 +1892,7 @@ OP_C7C0 ()
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op1 = OP[1] & 0x7;
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temp = SEXT16 (OP[2]);
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op2 = temp;
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temp = get_byte (State.mem + op0 + op2);
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temp = load_mem (op0 + op2, 1);
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State.sregs[5] &= ~PSW_Z;
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if ((temp & (1 << op1)) == 0)
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State.sregs[5] |= PSW_Z;
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@ -1939,7 +1940,17 @@ OP_14007E0 ()
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{
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trace_input ("reti", OP_NONE, 0);
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trace_output (OP_NONE);
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abort ();
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if ((State.sregs[5] & (PSW_NP | PSW_EP)) == PSW_NP)
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{ /* Only NP is on */
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PC = State.sregs[2] - 4; /* FEPC */
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State.sregs[5] = State.sregs[3]; /* FEPSW */
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}
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else
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{
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PC = State.sregs[0] - 4; /* EIPC */
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State.sregs[5] = State.sregs[1]; /* EIPSW */
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}
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}
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/* trap, not supportd */
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@ -1951,9 +1962,9 @@ OP_10007E0 ()
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trace_input ("trap", OP_TRAP, 0);
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trace_output (OP_TRAP);
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/* Trap 0 is used for simulating low-level I/O */
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/* Trap 31 is used for simulating OS I/O functions */
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if (OP[0] == 0)
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if (OP[0] == 31)
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{
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int save_errno = errno;
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errno = 0;
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@ -1972,8 +1983,7 @@ OP_10007E0 ()
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/* Turn a pointer in a register into a pointer into real memory. */
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#define MEMPTR(x) ((char *)((x) + State.mem))
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#define MEMPTR(x) (map (x))
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switch (FUNC)
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{
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@ -2069,12 +2079,12 @@ OP_10007E0 ()
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SLW (buf+28, host_stat.st_mtime);
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SLW (buf+36, host_stat.st_ctime);
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}
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#endif
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break;
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case SYS_chown:
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RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
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break;
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#endif
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case SYS_chmod:
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RETVAL = chmod (MEMPTR (PARM1), PARM2);
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break;
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@ -2089,10 +2099,14 @@ OP_10007E0 ()
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RETERR = errno;
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errno = save_errno;
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}
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else if (OP[0] == 1 )
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{
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char *fstr = State.regs[2] + State.mem;
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puts (fstr);
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else
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{ /* Trap 0 -> 30 */
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State.sregs[0] = PC + 4; /* EIPC */
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State.sregs[1] = State.sregs[5]; /* EIPSW */
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State.sregs[4] &= 0xffff0000; /* Mask out EICC */
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State.sregs[4] |= 0x40 + OP[0]; /* EICC */
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State.sregs[5] |= PSW_EP | PSW_ID; /* Now doing exception processing */
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PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
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}
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}
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@ -3,17 +3,45 @@
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#include "ansidecl.h"
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#include "callback.h"
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#include "opcode/v850.h"
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#include <limits.h>
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#include "remote-sim.h"
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extern host_callback *v850_callback;
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/* FIXME: host defines */
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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extern int v850_debug;
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#if UCHAR_MAX == 255
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typedef unsigned char uint8;
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typedef unsigned short uint16;
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typedef unsigned int uint32;
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typedef signed char int8;
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#else
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#error "Char is not an 8-bit type"
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#endif
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#if SHRT_MAX == 32767
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typedef unsigned short uint16;
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typedef signed short int16;
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#else
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#error "Short is not a 16-bit type"
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#endif
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#if INT_MAX == 2147483647
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typedef unsigned int uint32;
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typedef signed int int32;
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typedef signed long long int64;
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#else
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# if LONG_MAX == 2147483647
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typedef unsigned long uint32;
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typedef signed long int32;
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# else
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# error "Neither int nor long is a 32-bit type"
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# endif
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#endif
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/* FIXME: V850 defines */
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typedef uint32 reg_t;
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@ -24,7 +52,7 @@ struct simops
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long mask;
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void (*func)();
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int numops;
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int operands[9];
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int operands[6];
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};
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struct _state
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@ -50,17 +78,29 @@ extern struct simops Simops[];
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#define PSW_S 0x2
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#define PSW_Z 0x1
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#define SEXT3(x) ((((x)&0x7)^(~3))+4)
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~7))+8)
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#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
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/* sign-extend a 5-bit number */
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#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
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/* sign-extend a 7-bit number */
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#define SEXT7(x) ((((x)&0x7f)^(~0x4f))+0x40)
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/* sign-extend an 8-bit number */
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#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
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/* sign-extend a 9-bit number */
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#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
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/* sign-extend a 16-bit number */
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#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
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/* sign-extend a 22-bit number */
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#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
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@ -80,22 +120,24 @@ extern struct simops Simops[];
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#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
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#define RB(x) (*((uint8 *)((x)+State.mem)))
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#define SB(addr,data) ( RB(addr) = (data & 0xff))
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#ifdef WORDS_BIGENDIAN
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/*#define RB(x) (*((uint8 *)((x)+State.mem)))*/
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/*#define SB(addr,data) ( RB(addr) = (data & 0xff))*/
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uint32 get_word PARAMS ((uint8 *));
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uint16 get_half PARAMS ((uint8 *));
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uint8 get_byte PARAMS ((uint8 *));
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#define RLW(x) (*((uint32 *)((x)+State.mem)))
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void put_word PARAMS ((uint8 *, uint32));
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void put_half PARAMS ((uint8 *, uint16));
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void put_byte PARAMS ((uint8 *, uint8));
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#else
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uint32 load_mem PARAMS ((SIM_ADDR addr, int len));
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void store_mem PARAMS ((SIM_ADDR addr, int len, uint32 data));
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uint32 get_word PARAMS ((uint8 *));
|
||||
uint16 get_half PARAMS ((uint8 *));
|
||||
uint8 get_byte PARAMS ((uint8 *));
|
||||
uint8 *map PARAMS ((SIM_ADDR addr));
|
||||
|
||||
#define RLW(x) get_word((long)(x)+State.mem)
|
||||
#define RLW(x) load_mem (x, 4)
|
||||
|
||||
#endif /* not WORDS_BIGENDIAN */
|
||||
#ifdef _WIN32
|
||||
#define SIGTRAP 5
|
||||
#define SIGQUIT 3
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user