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* config/i386/tm-i386.h (FP7_REGNUM, FIRST_FPU_CTRL_REGNUM,
FCTRL_REGNUM, FPC_REGNUM, FSTAT_REGNUM, FTAG_REGNUM, FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM, FOP_REGNUM, LAST_FPU_CTRL_REGNUM, XMM0_REGNUM, XMM7_REGNUM, MXCSR_REGNUM, IS_FP_REGNUM, IS_SSE_REGNUM): Removed. (FP0_REGNUM): Define conditionally depending on HAVE_I387_REGS. (SIZEOF_FPU_CTRL_REGS): Hardcode value. * i386-tdep.h (struct gdbarch_tdep): Change such that it contains a single member `num_xmm_regs'. (FPC_REGNUM): New macro. (FIRST_FPU_REGNUM, LAST_FPU_REGNUM, FISRT_XMM_REGNUM, LAST_XMM_REGNUM, MXCSR_REGNUM, FIRST_FPU_CTRL_REGNUM, LAST_FPU_CTRL_REGNUM): Removed. (FCTRL_REGNUM, FSTAT_REGNUM, FTAG_REGNUM, FOP_REGNUM, XMM0_REGNUM, MXCSR_REGNUM): Define unconditionally. Change macros to match the comment describing the register layout. (FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM, FOOFF_REGNUM): New macros. (FP_REGNUM_P, FPC_REGNUM_P, SSE_REGNUM_P): New macros. (IS_FP_REGNUM, IS_FPU_CTRL_REGNUM, IS_SSE_REGNUM): Make obsolete, unconditionally define in terms of FP_REGNUM_P, FPC_REGNUM_P and SSE_REGNUM_P). (FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM): Make obsolete, unconditionally define in terms of FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM, FOOFF_REGNUM. * i386-tdep.c (i386_gdbarch_init): Initialize `num_xmm_regs' member of `struct gdbarch_tdep'. * x86-64-tdep.c (i386_gdbarch_init): Change initialization of `struct gdbarch_tdep'. * i387-nat.c (FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM): Replace with FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM and FOOFF_REGNUM. Use FPC_REGNUM instead of FIRST_FPU_CTRL_REGNUM. Use XMM0_REGNUM instead of LAST_FPU_CTRL_REGNUM.
This commit is contained in:
Mark Kettenis
parent
fd6b65e518
commit
96297dabb3
@ -1,3 +1,38 @@
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2001-12-27 Mark Kettenis <kettenis@gnu.org>
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* config/i386/tm-i386.h (FP7_REGNUM, FIRST_FPU_CTRL_REGNUM,
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FCTRL_REGNUM, FPC_REGNUM, FSTAT_REGNUM, FTAG_REGNUM, FCS_REGNUM,
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FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM, FOP_REGNUM,
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LAST_FPU_CTRL_REGNUM, XMM0_REGNUM, XMM7_REGNUM, MXCSR_REGNUM,
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IS_FP_REGNUM, IS_SSE_REGNUM): Removed.
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(FP0_REGNUM): Define conditionally depending on HAVE_I387_REGS.
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(SIZEOF_FPU_CTRL_REGS): Hardcode value.
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* i386-tdep.h (struct gdbarch_tdep): Change such that it contains
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a single member `num_xmm_regs'.
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(FPC_REGNUM): New macro.
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(FIRST_FPU_REGNUM, LAST_FPU_REGNUM, FISRT_XMM_REGNUM,
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LAST_XMM_REGNUM, MXCSR_REGNUM, FIRST_FPU_CTRL_REGNUM,
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LAST_FPU_CTRL_REGNUM): Removed.
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(FCTRL_REGNUM, FSTAT_REGNUM, FTAG_REGNUM, FOP_REGNUM, XMM0_REGNUM,
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MXCSR_REGNUM): Define unconditionally. Change macros to match the
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comment describing the register layout.
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(FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM, FOOFF_REGNUM): New macros.
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(FP_REGNUM_P, FPC_REGNUM_P, SSE_REGNUM_P): New macros.
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(IS_FP_REGNUM, IS_FPU_CTRL_REGNUM, IS_SSE_REGNUM): Make obsolete,
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unconditionally define in terms of FP_REGNUM_P, FPC_REGNUM_P and
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SSE_REGNUM_P).
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(FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM): Make
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obsolete, unconditionally define in terms of FISEG_REGNUM,
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FIOFF_REGNUM, FOSEG_REGNUM, FOOFF_REGNUM.
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* i386-tdep.c (i386_gdbarch_init): Initialize `num_xmm_regs'
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member of `struct gdbarch_tdep'.
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* x86-64-tdep.c (i386_gdbarch_init): Change initialization of
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`struct gdbarch_tdep'.
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* i387-nat.c (FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM):
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Replace with FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM and
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FOOFF_REGNUM. Use FPC_REGNUM instead of FIRST_FPU_CTRL_REGNUM.
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Use XMM0_REGNUM instead of LAST_FPU_CTRL_REGNUM.
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2001-12-25 Andrew Cagney <ac131313@redhat.com>
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* cli/cli-script.c (execute_control_command): Replace value_ptr
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@ -140,39 +140,12 @@ extern CORE_ADDR i386_saved_pc_after_call (struct frame_info *frame);
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#define PC_REGNUM 8 /* (eip) Contains program counter */
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#define PS_REGNUM 9 /* (ps) Contains processor status */
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/* These registers are present only if HAVE_I387_REGS is #defined.
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We promise that FP0 .. FP7 will always be consecutive register numbers. */
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#define FP0_REGNUM 16 /* first FPU floating-point register */
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#define FP7_REGNUM 23 /* last FPU floating-point register */
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/* All of these control registers (except for FCOFF and FDOFF) are
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sixteen bits long (at most) in the FPU, but are zero-extended to
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thirty-two bits in GDB's register file. This makes it easier to
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compute the size of the control register file, and somewhat easier
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to convert to and from the FSAVE instruction's 32-bit format. */
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#define FIRST_FPU_CTRL_REGNUM 24
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#define FCTRL_REGNUM 24 /* FPU control word */
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#define FPC_REGNUM 24 /* old name for FCTRL_REGNUM */
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#define FSTAT_REGNUM 25 /* FPU status word */
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#define FTAG_REGNUM 26 /* FPU register tag word */
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#define FCS_REGNUM 27 /* FPU instruction's code segment selector
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16 bits, called "FPU Instruction Pointer
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Selector" in the x86 manuals */
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#define FCOFF_REGNUM 28 /* FPU instruction's offset within segment
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("Fpu Code OFFset") */
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#define FDS_REGNUM 29 /* FPU operand's data segment */
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#define FDOFF_REGNUM 30 /* FPU operand's offset within segment */
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#define FOP_REGNUM 31 /* FPU opcode, bottom eleven bits */
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#define LAST_FPU_CTRL_REGNUM 31
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/* These registers are present only if HAVE_SSE_REGS is #defined.
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We promise that XMM0 .. XMM7 will always have consecutive reg numbers. */
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#define XMM0_REGNUM 32 /* first SSE data register */
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#define XMM7_REGNUM 39 /* last SSE data register */
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#define MXCSR_REGNUM 40 /* Streaming SIMD Extension control/status */
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#define IS_FP_REGNUM(n) (FP0_REGNUM <= (n) && (n) <= FP7_REGNUM)
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#define IS_SSE_REGNUM(n) (XMM0_REGNUM <= (n) && (n) <= XMM7_REGNUM)
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/* First FPU data register. */
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#ifdef HAVE_I387_REGS
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#define FP0_REGNUM 16
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#else
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#define FP0_REGNUM 0
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#endif
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/* Return the name of register REG. */
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@ -200,8 +173,7 @@ extern int i386_dwarf_reg_to_regnum (int reg);
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yields REGISTER_BYTES. */
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#define SIZEOF_GREGS (NUM_GREGS * 4)
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#define SIZEOF_FPU_REGS (8 * 10)
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#define SIZEOF_FPU_CTRL_REGS \
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((LAST_FPU_CTRL_REGNUM - FIRST_FPU_CTRL_REGNUM + 1) * 4)
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#define SIZEOF_FPU_CTRL_REGS (8 * 4)
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#define SIZEOF_SSE_REGS (8 * 16 + 4)
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@ -1218,6 +1218,10 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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tdep = XMALLOC (struct gdbarch_tdep);
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gdbarch = gdbarch_alloc (&info, tdep);
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/* FIXME: kettenis/2001-11-24: Although not all IA-32 processors
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have the SSE registers, it's easier to set the default to 8. */
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tdep->num_xmm_regs = 8;
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set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
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/* Call dummy code. */
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158
gdb/i386-tdep.h
158
gdb/i386-tdep.h
@ -22,90 +22,92 @@
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#ifndef I386_TDEP_H
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#define I386_TDEP_H
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#define FPU_REG_RAW_SIZE 10
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/* GDB's i386 target supports both the 32-bit Intel Architecture
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(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
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a similar register layout for both.
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#if !defined (XMM0_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define XMM0_REGNUM FIRST_XMM_REGNUM
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#endif
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#if !defined (FIRST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FIRST_FPU_REGNUM FP0_REGNUM
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#endif
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#if !defined (LAST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define LAST_FPU_REGNUM (gdbarch_tdep (current_gdbarch)->last_fpu_regnum)
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#endif
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#if !defined (FIRST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FIRST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->first_xmm_regnum)
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#endif
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#if !defined (LAST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define LAST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->last_xmm_regnum)
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#endif
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#if !defined (MXCSR_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define MXCSR_REGNUM (gdbarch_tdep (current_gdbarch)->mxcsr_regnum)
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#endif
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#if !defined (FIRST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FIRST_FPU_CTRL_REGNUM (gdbarch_tdep (current_gdbarch)->first_fpu_ctrl_regnum)
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#endif
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#if !defined (LAST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define LAST_FPU_CTRL_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
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#endif
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- General purpose registers
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- FPU data registers
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- FPU control registers
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- SSE data registers
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- SSE control register
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/* All of these control registers (except for FCOFF and FDOFF) are
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sixteen bits long (at most) in the FPU, but are zero-extended to
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thirty-two bits in GDB's register file. This makes it easier to
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compute the size of the control register file, and somewhat easier
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to convert to and from the FSAVE instruction's 32-bit format. */
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/* FPU control word. */
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#if !defined (FCTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FCTRL_REGNUM (FIRST_FPU_CTRL_REGNUM)
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#endif
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/* FPU status word. */
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#if !defined (FSTAT_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FSTAT_REGNUM (FIRST_FPU_CTRL_REGNUM + 1)
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#endif
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/* FPU register tag word. */
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#if !defined (FTAG_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FTAG_REGNUM (FIRST_FPU_CTRL_REGNUM + 2)
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#endif
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/* FPU instruction's code segment selector 16 bits, called "FPU Instruction
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Pointer Selector" in the x86 manuals. */
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#if !defined (FCS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FCS_REGNUM (FIRST_FPU_CTRL_REGNUM + 3)
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#endif
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/* FPU instruction's offset within segment ("Fpu Code OFFset"). */
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#if !defined (FCOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FCOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 4)
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#endif
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/* FPU operand's data segment. */
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#if !defined (FDS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FDS_REGNUM (FIRST_FPU_CTRL_REGNUM + 5)
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#endif
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/* FPU operand's offset within segment. */
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#if !defined (FDOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FDOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 6)
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#endif
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/* FPU opcode, bottom eleven bits. */
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#if !defined (FOP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FOP_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
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#endif
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The general purpose registers for the x86-64 architecture are quite
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different from IA-32. Therefore, the FP0_REGNUM target macro
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determines the register number at which the FPU data registers
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start. The number of FPU data and control registers is the same
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for both architectures. The number of SSE registers however,
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differs and is determined by the num_xmm_regs member of `struct
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gdbarch_tdep'. */
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/* i386 architecture specific information. */
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struct gdbarch_tdep
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{
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int last_fpu_regnum;
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int first_xmm_regnum;
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int last_xmm_regnum;
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int mxcsr_regnum; /* Streaming SIMD Extension control/status. */
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int first_fpu_ctrl_regnum;
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/* Number of SSE registers. */
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int num_xmm_regs;
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};
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#if !defined (IS_FP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define IS_FP_REGNUM(n) (FIRST_FPU_REGNUM <= (n) && (n) <= LAST_FPU_REGNUM)
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#endif
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#if !defined (IS_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define IS_FPU_CTRL_REGNUM(n) (FIRST_FPU_CTRL_REGNUM <= (n) && (n) <= LAST_FPU_CTRL_REGNUM)
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#endif
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#if !defined (IS_SSE_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define IS_SSE_REGNUM(n) (FIRST_XMM_REGNUM <= (n) && (n) <= LAST_XMM_REGNUM)
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#endif
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/* Floating-point registers. */
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#endif
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#define FPU_REG_RAW_SIZE 10
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/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
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(at most) in the FPU, but are zero-extended to 32 bits in GDB's
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register cache. */
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/* "Generic" floating point control register. */
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#define FPC_REGNUM (FP0_REGNUM + 8)
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/* FPU control word. */
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#define FCTRL_REGNUM FPC_REGNUM
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/* FPU status word. */
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#define FSTAT_REGNUM (FPC_REGNUM + 1)
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/* FPU register tag word. */
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#define FTAG_REGNUM (FPC_REGNUM + 2)
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/* FPU instruction's code segment selector, called "FPU Instruction
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Pointer Selector" in the IA-32 manuals. */
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#define FISEG_REGNUM (FPC_REGNUM + 3)
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/* FPU instruction's offset within segment. */
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#define FIOFF_REGNUM (FPC_REGNUM + 4)
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/* FPU operand's data segment. */
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#define FOSEG_REGNUM (FPC_REGNUM + 5)
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/* FPU operand's offset within segment */
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#define FOOFF_REGNUM (FPC_REGNUM + 6)
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/* FPU opcode, bottom eleven bits. */
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#define FOP_REGNUM (FPC_REGNUM + 7)
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/* Return non-zero if N corresponds to a FPU data registers. */
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#define FP_REGNUM_P(n) (FP0_REGNUM <= (n) && (n) < FPC_REGNUM)
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/* Return non-zero if N corresponds to a FPU control register. */
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#define FPC_REGNUM_P(n) (FPC_REGNUM <= (n) && (n) < XMM0_REGNUM)
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/* SSE registers. */
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/* First SSE data register. */
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#define XMM0_REGNUM (FPC_REGNUM + 8)
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/* SSE control/status register. */
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#define MXCSR_REGNUM \
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(XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs)
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/* Return non-zero if N corresponds to a SSE data register. */
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#define SSE_REGNUM_P(n) (XMM0_REGNUM <= (n) && (n) < MXCSR_REGNUM)
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/* FIXME: kettenis/2001-11-24: Obsolete macro's. */
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#define FCS_REGNUM FISEG_REGNUM
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#define FCOFF_REGNUM FIOFF_REGNUM
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#define FDS_REGNUM FOSEG_REGNUM
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#define FDOFF_REGNUM FOOFF_REGNUM
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#define IS_FP_REGNUM(n) FP_REGNUM_P (n)
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#define IS_FPU_CTRL_REGNUM(n) FPC_REGNUM_P (n)
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#define IS_SSE_REGNUM(n) SSE_REGNUM_P (n)
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#endif /* i386-tdep.h */
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@ -49,10 +49,10 @@ static int fsave_offset[] =
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0, /* FCTRL_REGNUM (16 bits). */
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4, /* FSTAT_REGNUM (16 bits). */
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8, /* FTAG_REGNUM (16 bits). */
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16, /* FCS_REGNUM (16 bits). */
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12, /* FCOFF_REGNUM. */
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24, /* FDS_REGNUM. */
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20, /* FDOFF_REGNUM. */
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16, /* FISEG_REGNUM (16 bits). */
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12, /* FIOFF_REGNUM. */
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24, /* FOSEG_REGNUM. */
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20, /* FOOFF_REGNUM. */
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18 /* FOP_REGNUM (bottom 11 bits). */
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};
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@ -68,8 +68,8 @@ i387_supply_register (int regnum, char *fsave)
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{
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/* Most of the FPU control registers occupy only 16 bits in
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the fsave area. Give those a special treatment. */
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if (regnum >= FIRST_FPU_CTRL_REGNUM
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&& regnum != FCOFF_REGNUM && regnum != FDOFF_REGNUM)
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if (regnum >= FPC_REGNUM
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&& regnum != FIOFF_REGNUM && regnum != FOOFF_REGNUM)
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{
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unsigned int val = *(unsigned short *) (FSAVE_ADDR (fsave, regnum));
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@ -94,7 +94,7 @@ i387_supply_fsave (char *fsave)
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{
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int i;
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for (i = FP0_REGNUM; i <= LAST_FPU_CTRL_REGNUM; i++)
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for (i = FP0_REGNUM; i < XMM0_REGNUM; i++)
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i387_supply_register (i, fsave);
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}
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@ -108,13 +108,13 @@ i387_fill_fsave (char *fsave, int regnum)
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{
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int i;
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for (i = FP0_REGNUM; i <= LAST_FPU_CTRL_REGNUM; i++)
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for (i = FP0_REGNUM; i < XMM0_REGNUM; i++)
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if (regnum == -1 || regnum == i)
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{
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/* Most of the FPU control registers occupy only 16 bits in
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the fsave area. Give those a special treatment. */
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if (i >= FIRST_FPU_CTRL_REGNUM
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&& i != FCOFF_REGNUM && i != FDOFF_REGNUM)
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if (i >= FPC_REGNUM
|
||||
&& i != FIOFF_REGNUM && i != FOOFF_REGNUM)
|
||||
{
|
||||
if (i == FOP_REGNUM)
|
||||
{
|
||||
@ -154,10 +154,10 @@ static int fxsave_offset[] =
|
||||
0, /* FCTRL_REGNUM (16 bits). */
|
||||
2, /* FSTAT_REGNUM (16 bits). */
|
||||
4, /* FTAG_REGNUM (16 bits). */
|
||||
12, /* FCS_REGNUM (16 bits). */
|
||||
8, /* FCOFF_REGNUM. */
|
||||
20, /* FDS_REGNUM (16 bits). */
|
||||
16, /* FDOFF_REGNUM. */
|
||||
12, /* FISEG_REGNUM (16 bits). */
|
||||
8, /* FIOFF_REGNUM. */
|
||||
20, /* FOSEG_REGNUM (16 bits). */
|
||||
16, /* FOOFF_REGNUM. */
|
||||
6, /* FOP_REGNUM (bottom 11 bits). */
|
||||
160, /* XMM0_REGNUM through ... */
|
||||
176,
|
||||
@ -189,8 +189,8 @@ i387_supply_fxsave (char *fxsave)
|
||||
{
|
||||
/* Most of the FPU control registers occupy only 16 bits in
|
||||
the fxsave area. Give those a special treatment. */
|
||||
if (i >= FIRST_FPU_CTRL_REGNUM && i < XMM0_REGNUM
|
||||
&& i != FCOFF_REGNUM && i != FDOFF_REGNUM)
|
||||
if (i >= FPC_REGNUM && i < XMM0_REGNUM
|
||||
&& i != FIOFF_REGNUM && i != FOOFF_REGNUM)
|
||||
{
|
||||
unsigned long val = *(unsigned short *) (FXSAVE_ADDR (fxsave, i));
|
||||
|
||||
@ -252,8 +252,8 @@ i387_fill_fxsave (char *fxsave, int regnum)
|
||||
{
|
||||
/* Most of the FPU control registers occupy only 16 bits in
|
||||
the fxsave area. Give those a special treatment. */
|
||||
if (i >= FIRST_FPU_CTRL_REGNUM && i < XMM0_REGNUM
|
||||
&& i != FCOFF_REGNUM && i != FDOFF_REGNUM)
|
||||
if (i >= FPC_REGNUM && i < XMM0_REGNUM
|
||||
&& i != FIOFF_REGNUM && i != FDOFF_REGNUM)
|
||||
{
|
||||
if (i == FOP_REGNUM)
|
||||
{
|
||||
|
||||
@ -817,11 +817,7 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
||||
{
|
||||
case bfd_mach_x86_64:
|
||||
case bfd_mach_x86_64_intel_syntax:
|
||||
tdep->last_fpu_regnum = 25;
|
||||
tdep->first_xmm_regnum = 34;
|
||||
tdep->last_xmm_regnum = 49;
|
||||
tdep->mxcsr_regnum = 50;
|
||||
tdep->first_fpu_ctrl_regnum = 26;
|
||||
tdep->num_xmm_regs = 16;
|
||||
break;
|
||||
case bfd_mach_i386_i386:
|
||||
case bfd_mach_i386_i8086:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user