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x86: introduce %BW to avoid going through vex_w_table[]
This parallels %LW and %XW.
This commit is contained in:
Jan Beulich
parent
3be5145ee6
commit
931452b644
@ -1,3 +1,16 @@
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2020-07-07 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
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EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
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EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
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EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
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Delete.
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(putop): Handle "BW".
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* i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
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0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
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and 0F3A3F ...
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* i386-dis-evex-prefix.h: ... here.
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2020-07-06 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
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@ -474,8 +474,8 @@
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/* PREFIX_EVEX_0F3826 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3826_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3826_P_2) },
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{ "vptestnm%BW", { XMask, Vex, EXx }, 0 },
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{ "vptestm%BW", { XMask, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3827 */
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{
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@ -486,13 +486,13 @@
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/* PREFIX_EVEX_0F3828 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3828_P_1) },
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{ "vpmovm2%BW", { XM, MaskR }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F3828_P_2) },
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},
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/* PREFIX_EVEX_0F3829 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3829_P_1) },
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{ "vpmov%BW2m", { XMask, EXx }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F3829_P_2) },
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},
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/* PREFIX_EVEX_0F382A */
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@ -693,7 +693,7 @@
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3854_P_2) },
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{ "vpopcnt%BW", { XM, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3855 */
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{
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@ -747,7 +747,7 @@
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3866_P_2) },
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{ "vpblendm%BW", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3868 */
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{
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@ -785,7 +785,7 @@
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3875_P_2) },
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{ "vpermi2%BW", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3876 */
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{
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@ -821,7 +821,7 @@
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F387D_P_2) },
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{ "vpermt2%BW", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F387E */
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{
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@ -869,7 +869,7 @@
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F388D_P_2) },
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{ "vperm%BW", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F388F */
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{
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@ -1227,13 +1227,13 @@
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3A3E_P_2) },
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{ "vpcmpu%BW", { XMask, Vex, EXx, VPCMP }, 0 },
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},
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/* PREFIX_EVEX_0F3A3F */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3A3F_P_2) },
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{ "vpcmp%BW", { XMask, Vex, EXx, VPCMP }, 0 },
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},
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/* PREFIX_EVEX_0F3A42 */
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{
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@ -442,31 +442,11 @@
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{
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{ "vpmovsxdq", { XM, EXxmmq }, 0 },
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},
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/* EVEX_W_0F3826_P_1 */
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{
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{ "vptestnmb", { XMask, Vex, EXx }, 0 },
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{ "vptestnmw", { XMask, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F3826_P_2 */
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{
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{ "vptestmb", { XMask, Vex, EXx }, 0 },
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{ "vptestmw", { XMask, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F3828_P_1 */
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{
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{ "vpmovm2b", { XM, MaskR }, 0 },
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{ "vpmovm2w", { XM, MaskR }, 0 },
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},
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/* EVEX_W_0F3828_P_2 */
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{
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{ Bad_Opcode },
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{ "vpmuldq", { XM, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F3829_P_1 */
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{
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{ "vpmovb2m", { XMask, EXx }, 0 },
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{ "vpmovw2m", { XMask, EXx }, 0 },
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},
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/* EVEX_W_0F3829_P_2 */
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{
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{ Bad_Opcode },
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@ -527,11 +507,6 @@
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{ "vdpbf16ps", { XM, Vex, EXx }, 0 },
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{ Bad_Opcode },
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},
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/* EVEX_W_0F3854_P_2 */
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{
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{ "vpopcntb", { XM, EXx }, 0 },
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{ "vpopcntw", { XM, EXx }, 0 },
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},
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/* EVEX_W_0F3859_P_2 */
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{
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{ "vbroadcasti32x2", { XM, EXxmm_mq }, 0 },
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@ -557,11 +532,6 @@
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{ "vpcompressb", { EXbScalar, XM }, 0 },
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{ "vpcompressw", { EXwScalar, XM }, 0 },
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},
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/* EVEX_W_0F3866_P_2 */
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{
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{ "vpblendmb", { XM, Vex, EXx }, 0 },
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{ "vpblendmw", { XM, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F3870_P_2 */
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{
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{ Bad_Opcode },
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@ -582,11 +552,6 @@
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{ "vcvtne2ps2bf16", { XM, Vex, EXx}, 0 },
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{ Bad_Opcode },
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},
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/* EVEX_W_0F3875_P_2 */
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{
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{ "vpermi2b", { XM, Vex, EXx }, 0 },
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{ "vpermi2w", { XM, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F387A_P_2 */
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{
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{ "vpbroadcastb", { XM, Rd }, 0 },
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@ -595,21 +560,11 @@
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{
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{ "vpbroadcastw", { XM, Rd }, 0 },
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},
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/* EVEX_W_0F387D_P_2 */
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{
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{ "vpermt2b", { XM, Vex, EXx }, 0 },
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{ "vpermt2w", { XM, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F3883_P_2 */
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{
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{ Bad_Opcode },
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{ "vpmultishiftqb", { XM, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F388D_P_2 */
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{
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{ "vpermb", { XM, Vex, EXx }, 0 },
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{ "vpermw", { XM, Vex, EXx }, 0 },
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},
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/* EVEX_W_0F3891_P_2 */
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{
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{ "vpgatherqd", { XMxmmq, MVexVSIBQDWpX }, 0 },
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@ -732,16 +687,6 @@
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A3B_P_2_W_0) },
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{ EVEX_LEN_TABLE (EVEX_LEN_0F3A3B_P_2_W_1) },
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},
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/* EVEX_W_0F3A3E_P_2 */
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{
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{ "vpcmpub", { XMask, Vex, EXx, VPCMP }, 0 },
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{ "vpcmpuw", { XMask, Vex, EXx, VPCMP }, 0 },
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},
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/* EVEX_W_0F3A3F_P_2 */
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{
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{ "vpcmpb", { XMask, Vex, EXx, VPCMP }, 0 },
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{ "vpcmpw", { XMask, Vex, EXx, VPCMP }, 0 },
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},
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/* EVEX_W_0F3A42_P_2 */
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{
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{ "vdbpsadbw", { XM, Vex, EXx, Ib }, 0 },
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@ -2059,11 +2059,7 @@ enum
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EVEX_W_0F3824_P_1,
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EVEX_W_0F3825_P_1,
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EVEX_W_0F3825_P_2,
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EVEX_W_0F3826_P_1,
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EVEX_W_0F3826_P_2,
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EVEX_W_0F3828_P_1,
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EVEX_W_0F3828_P_2,
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EVEX_W_0F3829_P_1,
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EVEX_W_0F3829_P_2,
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EVEX_W_0F382A_P_1,
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EVEX_W_0F382A_P_2,
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@ -2078,23 +2074,18 @@ enum
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EVEX_W_0F3837_P_2,
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EVEX_W_0F383A_P_1,
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EVEX_W_0F3852_P_1,
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EVEX_W_0F3854_P_2,
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EVEX_W_0F3859_P_2,
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EVEX_W_0F385A_P_2,
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EVEX_W_0F385B_P_2,
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EVEX_W_0F3862_P_2,
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EVEX_W_0F3863_P_2,
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EVEX_W_0F3866_P_2,
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EVEX_W_0F3870_P_2,
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EVEX_W_0F3872_P_1,
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EVEX_W_0F3872_P_2,
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EVEX_W_0F3872_P_3,
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EVEX_W_0F3875_P_2,
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EVEX_W_0F387A_P_2,
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EVEX_W_0F387B_P_2,
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EVEX_W_0F387D_P_2,
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EVEX_W_0F3883_P_2,
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EVEX_W_0F388D_P_2,
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EVEX_W_0F3891_P_2,
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EVEX_W_0F3893_P_2,
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EVEX_W_0F38A1_P_2,
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@ -2121,8 +2112,6 @@ enum
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EVEX_W_0F3A39_P_2,
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EVEX_W_0F3A3A_P_2,
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EVEX_W_0F3A3B_P_2,
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EVEX_W_0F3A3E_P_2,
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EVEX_W_0F3A3F_P_2,
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EVEX_W_0F3A42_P_2,
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EVEX_W_0F3A43_P_2,
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EVEX_W_0F3A70_P_2,
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@ -2198,6 +2187,7 @@ struct dis386 {
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"LS" => print "abs" in 64bit mode and behave as 'S' otherwise
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"LV" => print "abs" for 64bit operand and behave as 'S' otherwise
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"LW" => print 'd', 'q' depending on the VEX.W bit
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"BW" => print 'b' or 'w' depending on the EVEX.W bit
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"LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
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an operand size prefix, or suffix_always is true. print
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'q' if rex prefix is present.
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@ -13129,6 +13119,8 @@ putop (const char *in_template, int sizeflag)
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*obufp++ = vex.w ? 'd': 's';
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else if (last[0] == 'L')
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*obufp++ = vex.w ? 'q': 'd';
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else if (last[0] == 'B')
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*obufp++ = vex.w ? 'w': 'b';
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else
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abort ();
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}
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