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sim: bpf: remove support for ldinddw and ldabsdw instructions
This patch removes support for the two instructions above from the GNU simulator, including the corresponding tests. These instructions do not really exist in BPF and are not recognized as such by the kernel verifier. This has now been pointed out during the standardization of the BPF ISA. Signed-off-by: Jose E. Marchesi <jose.marchesi@oracle.com>
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@ -943,13 +943,6 @@ execute (SIM_CPU *cpu, struct bpf_insn *insn)
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bpf_read_u64 (cpu, bpf_regs[BPF_R6] + skb_data_offset)
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+ bpf_regs[insn->src] + insn->imm32);
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break;
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case BPF_INSN_LDINDDW:
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BPF_TRACE ("BPF_INSN_LDINDDW\n");
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bpf_regs[BPF_R0] = bpf_read_u64 (cpu,
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bpf_read_u64 (cpu, bpf_regs[BPF_R6] + skb_data_offset)
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+ bpf_regs[insn->src] + insn->imm32);
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break;
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/* Absolute load instructions. */
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case BPF_INSN_LDABSB:
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BPF_TRACE ("BPF_INSN_LDABSB\n");
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bpf_regs[BPF_R0] = bpf_read_u8 (cpu,
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@ -968,12 +961,6 @@ execute (SIM_CPU *cpu, struct bpf_insn *insn)
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bpf_read_u64 (cpu, bpf_regs[BPF_R6] + skb_data_offset)
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+ insn->imm32);
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break;
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case BPF_INSN_LDABSDW:
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BPF_TRACE ("BPF_INSN_LDABSDW\n");
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bpf_regs[BPF_R0] = bpf_read_u64 (cpu,
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bpf_read_u64 (cpu, bpf_regs[BPF_R6] + skb_data_offset)
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+ insn->imm32);
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break;
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/* Generic load instructions (to register.) */
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case BPF_INSN_LDXB:
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BPF_TRACE ("BPF_INSN_LDXB\n");
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@ -52,14 +52,6 @@ main:
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ldabsb 0x10
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fail_ne32 %r0, 0x5a
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/* Repeat for a double-word (8-byte)
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(note: fail_ne macro uses r0, so copy to another r1 to compare) */
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lddw %r2, 0x1234deadbeef5678
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stxdw [%r6+0x1018], %r2
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ldabsdw 0x18
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mov %r1, %r0
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fail_ne %r1, 0x1234deadbeef5678
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/* Now, we do the same for the indirect loads */
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mov %r7, 0x100
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stw [%r6+0x1100], 0x0eedbeef
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@ -77,11 +69,4 @@ main:
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ldindb %r7, 0x8
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fail_ne32 %r0, 0x5f
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/* double-word */
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lddw %r2, 0xcafe12345678d00d
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stxdw [%r6+0x1110], %r2
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ldinddw %r7, 0x10
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mov %r1, %r0
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fail_ne %r1, 0xcafe12345678d00d
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pass
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