Enable Intel AVX512_VP2INTERSECT insn

This patch enables support for VP2INTERSECT in binutils.  Please refer to

https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

for VP2INTERSECT details.

Make check-gas is ok.

gas/

2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document avx512_vp2intersect.
	* testsuite/gas/i386/i386.exp: Run vp2intersect tests.
	* testsuite/gas/i386/vp2intersect-intel.d: New test.
	* testsuite/gas/i386/vp2intersect.d: Likewise.
	* testsuite/gas/i386/vp2intersect.s: Likewise.
	* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.
	* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.

opcodes/

2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
	* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
	instructions.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
	CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
	(cpu_flags): Add CpuAVX512_VP2INTERSECT.
	* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
	(i386_cpu_flags): Add cpuavx512_vp2intersect.
	* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu 2019-06-04 08:58:21 -07:00
parent 5d79adc4b2
commit 9186c494a3
26 changed files with 4665 additions and 4143 deletions

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@ -1,3 +1,21 @@
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document avx512_vp2intersect.
* testsuite/gas/i386/i386.exp: Run vp2intersect tests.
* testsuite/gas/i386/vp2intersect-intel.d: New test.
* testsuite/gas/i386/vp2intersect.d: Likewise.
* testsuite/gas/i386/vp2intersect.s: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>

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@ -1082,6 +1082,8 @@ static const arch_entry cpu_arch[] =
CPU_MOVDIR64B_FLAGS, 0 },
{ STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN,
CPU_AVX512_BF16_FLAGS, 0 },
{ STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN,
CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
};
static const noarch_entry cpu_noarch[] =
@ -1122,6 +1124,7 @@ static const noarch_entry cpu_noarch[] =
{ STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
{ STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
{ STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
{ STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS },
};
#ifdef I386COFF

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@ -215,6 +215,7 @@ accept various extension mnemonics. For example,
@code{noavx512_vbmi2},
@code{noavx512_vnni},
@code{noavx512_bitalg},
@code{noavx512_vp2intersect},
@code{noavx512_bf16},
@code{vmx},
@code{vmfunc},
@ -1306,7 +1307,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16}
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}

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@ -241,6 +241,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "sse2avx"
run_list_test "inval-avx" "-al"
run_list_test "inval-avx512f" "-al"
run_list_test "inval-avx512vl" "-al"
run_dump_test "sse-check"
run_dump_test "sse-check-none"
run_dump_test "sse-check-warn"
@ -456,6 +457,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "enqcmd"
run_dump_test "enqcmd-intel"
run_list_test "enqcmd-inval"
run_dump_test "vp2intersect"
run_dump_test "vp2intersect-intel"
run_list_test "vp2intersect-inval-bcast"
run_list_test "avx512vl-1" "-al"
run_list_test "avx512vl-2" "-al"
run_list_test "avx512vl-plain" "-al"
@ -773,6 +777,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-sse2avx"
run_list_test "x86-64-inval-avx" "-al"
run_list_test "x86-64-inval-avx512f" "-al"
run_list_test "x86-64-inval-avx512vl" "-al"
run_dump_test "x86-64-sse-check"
run_dump_test "x86-64-sse-check-none"
run_dump_test "x86-64-sse-check-warn"
@ -975,6 +980,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-enqcmd"
run_dump_test "x86-64-enqcmd-intel"
run_list_test "x86-64-enqcmd-inval"
run_dump_test "x86-64-vp2intersect"
run_dump_test "x86-64-vp2intersect-intel"
run_list_test "x86-64-vp2intersect-inval-bcast"
run_dump_test "x86-64-fence-as-lock-add-yes"
run_dump_test "x86-64-fence-as-lock-add-no"
run_dump_test "x86-64-pr20141"

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@ -0,0 +1,12 @@
.*: Assembler messages:
.*:5: Error: .*unsupported instruction.*
.*:6: Error: .*unsupported instruction.*
GAS LISTING .*
[ ]*1[ ]+# Check illegal AVX512VL instructions
[ ]*2[ ]+\.text
[ ]*3[ ]+\.arch \.noavx512vl
[ ]*4[ ]+_start:
[ ]*5[ ]+vp2intersectd %ymm1, %ymm2, %k3
[ ]*6[ ]+vp2intersectq %ymm1, %ymm2, %k3

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@ -0,0 +1,6 @@
# Check illegal AVX512VL instructions
.text
.arch .noavx512vl
_start:
vp2intersectd %ymm1, %ymm2, %k3
vp2intersectq %ymm1, %ymm2, %k3

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@ -0,0 +1,48 @@
#as:
#objdump: -dw -Mintel
#name: i386 VP2INTERSECT insns (Intel disassembly)
#source: vp2intersect.s
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd k3,zmm2,ZMMWORD PTR \[eax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd k3,zmm2,DWORD PTR \[eax\+0x8\]\{1to16\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd k3,ymm2,YMMWORD PTR \[eax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd k3,ymm2,DWORD PTR \[eax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd k3,xmm2,XMMWORD PTR \[eax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd k3,xmm2,DWORD PTR \[eax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq k3,zmm2,ZMMWORD PTR \[eax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq k3,zmm2,QWORD PTR \[eax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq k3,ymm2,YMMWORD PTR \[eax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq k3,ymm2,QWORD PTR \[eax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq k3,xmm2,XMMWORD PTR \[eax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq k3,xmm2,QWORD PTR \[eax\+0x8\]\{1to2\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd k3,zmm2,ZMMWORD PTR \[eax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd k3,zmm2,DWORD PTR \[eax\+0x8\]\{1to16\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd k3,ymm2,YMMWORD PTR \[eax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd k3,ymm2,DWORD PTR \[eax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd k3,xmm2,XMMWORD PTR \[eax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd k3,xmm2,DWORD PTR \[eax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq k3,zmm2,ZMMWORD PTR \[eax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq k3,zmm2,QWORD PTR \[eax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq k3,ymm2,YMMWORD PTR \[eax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq k3,ymm2,QWORD PTR \[eax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq k3,xmm2,XMMWORD PTR \[eax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq k3,xmm2,QWORD PTR \[eax\+0x8\]\{1to2\}
#pass

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@ -0,0 +1,13 @@
.*: Assembler messages:
.*:6: Error: unsupported broadcast for `vp2intersectd'
.*:7: Error: unsupported broadcast for `vp2intersectd'
.*:8: Error: unsupported broadcast for `vp2intersectd'
.*:9: Error: unsupported broadcast for `vp2intersectq'
.*:10: Error: unsupported broadcast for `vp2intersectq'
.*:11: Error: unsupported broadcast for `vp2intersectq'
.*:14: Error: unsupported broadcast for `vp2intersectd'
.*:15: Error: unsupported broadcast for `vp2intersectd'
.*:16: Error: unsupported broadcast for `vp2intersectd'
.*:17: Error: unsupported broadcast for `vp2intersectq'
.*:18: Error: unsupported broadcast for `vp2intersectq'
.*:19: Error: unsupported broadcast for `vp2intersectq'

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@ -0,0 +1,19 @@
# Check error for invalid {1toXX} and {2toXX} broadcasts.
.allow_index_reg
.text
_start:
vp2intersectd 8(%eax){1to8}, %xmm2, %k3
vp2intersectd 8(%eax){1to16}, %ymm2, %k3
vp2intersectd 8(%eax){1to8}, %zmm2, %k3
vp2intersectq 8(%eax){1to4}, %xmm2, %k3
vp2intersectq 8(%eax){1to8}, %ymm2, %k3
vp2intersectq 8(%eax){1to16}, %zmm2, %k3
.intel_syntax noprefix
vp2intersectd k3, zmm2, 8[eax]{1to8}
vp2intersectd k3, ymm2, 8[eax]{1to16}
vp2intersectd k3, xmm2, 8[eax]{1to8}
vp2intersectq k3, zmm2, 8[eax]{1to16}
vp2intersectq k3, ymm2, 8[eax]{1to8}
vp2intersectq k3, xmm2, 8[eax]{1to4}

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@ -0,0 +1,48 @@
#as:
#objdump: -dw
#name: i386 VP2INTERSECT insns
#source: vp2intersect.s
.*: +file format .*
Disassembly of section \.text:
00000000 <\.text>:
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd 0x40\(%eax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd 0x8\(%eax\)\{1to16\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd 0x20\(%eax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd 0x8\(%eax\)\{1to8\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd 0x10\(%eax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd 0x8\(%eax\)\{1to4\},%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq 0x40\(%eax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq 0x8\(%eax\)\{1to8\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq 0x20\(%eax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq 0x8\(%eax\)\{1to4\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq 0x10\(%eax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq 0x8\(%eax\)\{1to2\},%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd 0x40\(%eax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd 0x8\(%eax\)\{1to16\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd 0x20\(%eax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd 0x8\(%eax\)\{1to8\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd 0x10\(%eax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd 0x8\(%eax\)\{1to4\},%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq 0x40\(%eax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq 0x8\(%eax\)\{1to8\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq 0x20\(%eax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq 0x8\(%eax\)\{1to4\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq 0x10\(%eax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq 0x8\(%eax\)\{1to2\},%xmm2,%k3
#pass

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@ -0,0 +1,51 @@
# Check AVX512_VP2INTERSECT new instructions.
.text
vp2intersectd %zmm1, %zmm2, %k3
vp2intersectd 64(%eax), %zmm2, %k3
vp2intersectd 8(%eax){1to16}, %zmm2, %k3
vp2intersectd %ymm1, %ymm2, %k3
vp2intersectd 32(%eax), %ymm2, %k3
vp2intersectd 8(%eax){1to8}, %ymm2, %k3
vp2intersectd %xmm1, %xmm2, %k3
vp2intersectd 16(%eax), %xmm2, %k3
vp2intersectd 8(%eax){1to4}, %xmm2, %k3
vp2intersectq %zmm1, %zmm2, %k3
vp2intersectq 64(%eax), %zmm2, %k3
vp2intersectq 8(%eax){1to8}, %zmm2, %k3
vp2intersectq %ymm1, %ymm2, %k3
vp2intersectq 32(%eax), %ymm2, %k3
vp2intersectq 8(%eax){1to4}, %ymm2, %k3
vp2intersectq %xmm1, %xmm2, %k3
vp2intersectq 16(%eax), %xmm2, %k3
vp2intersectq 8(%eax){1to2}, %xmm2, %k3
.intel_syntax noprefix
vp2intersectd k3, zmm2, zmm1
vp2intersectd k3, zmm2, 64[eax]
vp2intersectd k3, zmm2, 8[eax]{1to16}
vp2intersectd k3, ymm2, ymm1
vp2intersectd k3, ymm2, 32[eax]
vp2intersectd k3, ymm2, 8[eax]{1to8}
vp2intersectd k3, xmm2, xmm1
vp2intersectd k3, xmm2, 16[eax]
vp2intersectd k3, xmm2, 8[eax]{1to4}
vp2intersectq k3, zmm2, zmm1
vp2intersectq k3, zmm2, 64[eax]
vp2intersectq k3, zmm2, 8[eax]{1to8}
vp2intersectq k3, ymm2, ymm1
vp2intersectq k3, ymm2, 32[eax]
vp2intersectq k3, ymm2, 8[eax]{1to4}
vp2intersectq k3, xmm2, xmm1
vp2intersectq k3, xmm2, 16[eax]
vp2intersectq k3, xmm2, 8[eax]{1to2}

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@ -0,0 +1,12 @@
.*: Assembler messages:
.*:5: Error: .*unsupported instruction.*
.*:6: Error: .*unsupported instruction.*
GAS LISTING .*
[ ]*1[ ]+# Check illegal AVX512VL instructions
[ ]*2[ ]+\.text
[ ]*3[ ]+\.arch \.noavx512vl
[ ]*4[ ]+_start:
[ ]*5[ ]+vp2intersectd 32\(%rax\), %ymm2, %k3
[ ]*6[ ]+vp2intersectq 16\(%rax\), %xmm2, %k3

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@ -0,0 +1,6 @@
# Check illegal AVX512VL instructions
.text
.arch .noavx512vl
_start:
vp2intersectd 32(%rax), %ymm2, %k3
vp2intersectq 16(%rax), %xmm2, %k3

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@ -0,0 +1,48 @@
#as:
#objdump: -dw -Mintel
#name: x86_64 VP2INTERSECT insns (Intel disassembly)
#source: x86-64-vp2intersect.s
.*: +file format .*
Disassembly of section \.text:
0+ <\.text>:
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd k3,zmm2,ZMMWORD PTR \[rax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd k3,zmm2,DWORD PTR \[rax\+0x8\]\{1to16\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd k3,ymm2,YMMWORD PTR \[rax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd k3,ymm2,DWORD PTR \[rax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd k3,xmm2,XMMWORD PTR \[rax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd k3,xmm2,DWORD PTR \[rax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq k3,zmm2,ZMMWORD PTR \[rax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq k3,zmm2,QWORD PTR \[rax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq k3,ymm2,YMMWORD PTR \[rax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq k3,ymm2,QWORD PTR \[rax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq k3,xmm2,XMMWORD PTR \[rax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq k3,xmm2,QWORD PTR \[rax\+0x8\]\{1to2\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd k3,zmm2,ZMMWORD PTR \[rax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd k3,zmm2,DWORD PTR \[rax\+0x8\]\{1to16\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd k3,ymm2,YMMWORD PTR \[rax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd k3,ymm2,DWORD PTR \[rax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd k3,xmm2,XMMWORD PTR \[rax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd k3,xmm2,DWORD PTR \[rax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq k3,zmm2,zmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq k3,zmm2,ZMMWORD PTR \[rax\+0x40\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq k3,zmm2,QWORD PTR \[rax\+0x8\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq k3,ymm2,ymm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq k3,ymm2,YMMWORD PTR \[rax\+0x20\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq k3,ymm2,QWORD PTR \[rax\+0x8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq k3,xmm2,xmm1
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq k3,xmm2,XMMWORD PTR \[rax\+0x10\]
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq k3,xmm2,QWORD PTR \[rax\+0x8\]\{1to2\}
#pass

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@ -0,0 +1,13 @@
.*: Assembler messages:
.*:6: Error: unsupported broadcast for `vp2intersectd'
.*:7: Error: unsupported broadcast for `vp2intersectd'
.*:8: Error: unsupported broadcast for `vp2intersectd'
.*:9: Error: unsupported broadcast for `vp2intersectq'
.*:10: Error: unsupported broadcast for `vp2intersectq'
.*:11: Error: unsupported broadcast for `vp2intersectq'
.*:14: Error: unsupported broadcast for `vp2intersectd'
.*:15: Error: unsupported broadcast for `vp2intersectd'
.*:16: Error: unsupported broadcast for `vp2intersectd'
.*:17: Error: unsupported broadcast for `vp2intersectq'
.*:18: Error: unsupported broadcast for `vp2intersectq'
.*:19: Error: unsupported broadcast for `vp2intersectq'

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@ -0,0 +1,19 @@
# Check error for invalid {1toXX} and {2toXX} broadcasts.
.allow_index_reg
.text
_start:
vp2intersectd 8(%rax){1to8}, %zmm2, %k3
vp2intersectd 8(%rax){1to4}, %ymm2, %k3
vp2intersectd 8(%rax){1to2}, %xmm2, %k3
vp2intersectq 8(%rax){1to16}, %zmm2, %k3
vp2intersectq 8(%rax){1to8}, %ymm2, %k3
vp2intersectq 8(%rax){1to4}, %xmm2, %k3
.intel_syntax noprefix
vp2intersectd k3, zmm2, 8[rax]{1to8}
vp2intersectd k3, ymm2, 8[rax]{1to4}
vp2intersectd k3, xmm2, 8[rax]{1to2}
vp2intersectq k3, zmm2, 8[rax]{1to16}
vp2intersectq k3, ymm2, 8[rax]{1to8}
vp2intersectq k3, xmm2, 8[rax]{1to4}

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@ -0,0 +1,48 @@
#as:
#objdump: -dw
#name: x86_64 VP2INTERSECT insns
#source: x86-64-vp2intersect.s
.*: +file format .*
Disassembly of section \.text:
0+ <\.text>:
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd 0x40\(%rax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd 0x8\(%rax\)\{1to16\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd 0x20\(%rax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd 0x8\(%rax\)\{1to8\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd 0x10\(%rax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd 0x8\(%rax\)\{1to4\},%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq 0x40\(%rax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq 0x8\(%rax\)\{1to8\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq 0x20\(%rax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq 0x8\(%rax\)\{1to4\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq 0x10\(%rax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq 0x8\(%rax\)\{1to2\},%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 d9[ ]*vp2intersectd %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 68 58 01[ ]*vp2intersectd 0x40\(%rax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 58 68 58 02[ ]*vp2intersectd 0x8\(%rax\)\{1to16\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 d9[ ]*vp2intersectd %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 28 68 58 01[ ]*vp2intersectd 0x20\(%rax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 38 68 58 02[ ]*vp2intersectd 0x8\(%rax\)\{1to8\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 d9[ ]*vp2intersectd %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 08 68 58 01[ ]*vp2intersectd 0x10\(%rax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 6f 18 68 58 02[ ]*vp2intersectd 0x8\(%rax\)\{1to4\},%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 d9[ ]*vp2intersectq %zmm1,%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 48 68 58 01[ ]*vp2intersectq 0x40\(%rax\),%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 58 68 58 01[ ]*vp2intersectq 0x8\(%rax\)\{1to8\},%zmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 d9[ ]*vp2intersectq %ymm1,%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 28 68 58 01[ ]*vp2intersectq 0x20\(%rax\),%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 38 68 58 01[ ]*vp2intersectq 0x8\(%rax\)\{1to4\},%ymm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 d9[ ]*vp2intersectq %xmm1,%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 08 68 58 01[ ]*vp2intersectq 0x10\(%rax\),%xmm2,%k3
[ ]*[a-f0-9]+:[ ]*62 f2 ef 18 68 58 01[ ]*vp2intersectq 0x8\(%rax\)\{1to2\},%xmm2,%k3
#pass

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@ -0,0 +1,51 @@
# Check AVX512_VP2INTERSECT new instructions.
.text
vp2intersectd %zmm1, %zmm2, %k3
vp2intersectd 64(%rax), %zmm2, %k3
vp2intersectd 8(%rax){1to16}, %zmm2, %k3
vp2intersectd %ymm1, %ymm2, %k3
vp2intersectd 32(%rax), %ymm2, %k3
vp2intersectd 8(%rax){1to8}, %ymm2, %k3
vp2intersectd %xmm1, %xmm2, %k3
vp2intersectd 16(%rax), %xmm2, %k3
vp2intersectd 8(%rax){1to4}, %xmm2, %k3
vp2intersectq %zmm1, %zmm2, %k3
vp2intersectq 64(%rax), %zmm2, %k3
vp2intersectq 8(%rax){1to8}, %zmm2, %k3
vp2intersectq %ymm1, %ymm2, %k3
vp2intersectq 32(%rax), %ymm2, %k3
vp2intersectq 8(%rax){1to4}, %ymm2, %k3
vp2intersectq %xmm1, %xmm2, %k3
vp2intersectq 16(%rax), %xmm2, %k3
vp2intersectq 8(%rax){1to2}, %xmm2, %k3
.intel_syntax noprefix
vp2intersectd k3, zmm2, zmm1
vp2intersectd k3, zmm2, 64[rax]
vp2intersectd k3, zmm2, 8[rax]{1to16}
vp2intersectd k3, ymm2, ymm1
vp2intersectd k3, ymm2, 32[rax]
vp2intersectd k3, ymm2, 8[rax]{1to8}
vp2intersectd k3, xmm2, xmm1
vp2intersectd k3, xmm2, 16[rax]
vp2intersectd k3, xmm2, 8[rax]{1to4}
vp2intersectq k3, zmm2, zmm1
vp2intersectq k3, zmm2, 64[rax]
vp2intersectq k3, zmm2, 8[rax]{1to8}
vp2intersectq k3, ymm2, ymm1
vp2intersectq k3, ymm2, 32[rax]
vp2intersectq k3, ymm2, 8[rax]{1to4}
vp2intersectq k3, xmm2, xmm1
vp2intersectq k3, xmm2, 16[rax]
vp2intersectq k3, xmm2, 8[rax]{1to2}

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@ -1,3 +1,18 @@
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
instructions.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
(cpu_flags): Add CpuAVX512_VP2INTERSECT.
* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
(i386_cpu_flags): Add cpuavx512_vp2intersect.
* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>

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@ -412,7 +412,7 @@ static const struct dis386 evex_table[][256] = {
{ PREFIX_TABLE (PREFIX_EVEX_0F3866) },
{ Bad_Opcode },
/* 68 */
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_0F3868) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@ -2097,6 +2097,13 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3866_P_2) },
},
/* PREFIX_EVEX_0F3868 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3868_P_3) },
},
/* PREFIX_EVEX_0F3870 */
{
{ Bad_Opcode },
@ -3755,6 +3762,11 @@ static const struct dis386 evex_table[][256] = {
{ "vpblendmb", { XM, Vex, EXx }, 0 },
{ "vpblendmw", { XM, Vex, EXx }, 0 },
},
/* EVEX_W_0F3868_P_3 */
{
{ "vp2intersectd", { XMask, Vex, EXx, EXxEVexS }, 0 },
{ "vp2intersectq", { XMask, Vex, EXx, EXxEVexS }, 0 },
},
/* EVEX_W_0F3870_P_2 */
{
{ Bad_Opcode },

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@ -1613,6 +1613,7 @@ enum
PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865,
PREFIX_EVEX_0F3866,
PREFIX_EVEX_0F3868,
PREFIX_EVEX_0F3870,
PREFIX_EVEX_0F3871,
PREFIX_EVEX_0F3872,
@ -2201,6 +2202,7 @@ enum
EVEX_W_0F3862_P_2,
EVEX_W_0F3863_P_2,
EVEX_W_0F3866_P_2,
EVEX_W_0F3868_P_3,
EVEX_W_0F3870_P_2,
EVEX_W_0F3871_P_2,
EVEX_W_0F3872_P_1,

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@ -297,6 +297,8 @@ static initializer cpu_flag_init[] =
"CpuMOVDIR64B" },
{ "CPU_ENQCMD_FLAGS",
"CpuENQCMD" },
{ "CPU_AVX512_VP2INTERSECT_FLAGS",
"CpuAVX512_VP2INTERSECT" },
{ "CPU_ANY_X87_FLAGS",
"CPU_ANY_287_FLAGS|Cpu8087" },
{ "CPU_ANY_287_FLAGS",
@ -328,7 +330,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_AVX2_FLAGS",
"CPU_ANY_AVX512F_FLAGS|CpuAVX2" },
{ "CPU_ANY_AVX512F_FLAGS",
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16" },
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" },
{ "CPU_ANY_AVX512CD_FLAGS",
"CpuAVX512CD" },
{ "CPU_ANY_AVX512ER_FLAGS",
@ -369,6 +371,8 @@ static initializer cpu_flag_init[] =
"CpuMOVDIR64B" },
{ "CPU_ANY_ENQCMD_FLAGS",
"CpuENQCMD" },
{ "CPU_ANY_AVX512_VP2INTERSECT_FLAGS",
"CpuAVX512_VP2INTERSECT" },
};
static const initializer operand_type_shorthands[] =
@ -587,6 +591,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX512_VNNI),
BITFIELD (CpuAVX512_BITALG),
BITFIELD (CpuAVX512_BF16),
BITFIELD (CpuAVX512_VP2INTERSECT),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),

File diff suppressed because it is too large Load Diff

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@ -208,6 +208,8 @@ enum
CpuAVX512_BITALG,
/* Intel AVX-512 BF16 Instructions support required. */
CpuAVX512_BF16,
/* Intel AVX-512 VP2INTERSECT Instructions support required. */
CpuAVX512_VP2INTERSECT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@ -352,6 +354,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx512_vnni:1;
unsigned int cpuavx512_bitalg:1;
unsigned int cpuavx512_bf16:1;
unsigned int cpuavx512_vp2intersect:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;

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@ -4734,3 +4734,10 @@ enqcmds, 2, 0xf30f38f8, None, 3, CpuENQCMD|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_
enqcmds, 2, 0xf30f38f8, None, 3, CpuENQCMD|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg32|Reg64 }
// ENQCMD instructions end.
// VP2INTERSECT instructions.
vp2intersectd, 3, 0xf268, None, 1, CpuAVX512_VP2INTERSECT, Modrm|VexOpcode|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
vp2intersectq, 3, 0xf268, None, 1, CpuAVX512_VP2INTERSECT, Modrm|VexOpcode|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
// VP2INTERSECT instructions end.

File diff suppressed because it is too large Load Diff