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[ARC] Fix support for double assist instructions.

Browse Source 
opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-regs.h: Add a new subclass field.  Add double assist
        accumulator register values.
        * arc-tbl.h: Use DPA subclass to mark the double assist
        instructions.  Use DPX/SPX subclas to mark the FPX instructions.
        * arc-opc.c (RSP): Define instead of SP.
        (arc_aux_regs): Add the subclass field.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
        (ARC_FPUDA): Define.
        (arc_aux_reg): Add new field.

gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * config/tc-arc.c (is_code_density_p): Compare directly the
        subclass field.
        (is_spfp_p, is_dpfp_p, is_spfp_p): Define.
        (check_cpu_feature): New function.
        (find_opcode_match): Use check_cpu_feature function.
        (preprocess_operands): Likewise.
        (md_parse_option): Use mfpuda, mdpfp, mspfp options.
        * testsuite/gas/arc/tdpfp.d: New file.
        * testsuite/gas/arc/tfpuda.d: Likewise.
        * testsuite/gas/arc/tfpx.s: Likewise.
This commit is contained in:
Claudiu Zissulescu 2016-04-05 17:37:29 +02:00
parent 1e5885b72e
commit 8ddf6b2a13
11 changed files with 1235 additions and 1071 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
gas/ChangeLog
View File

@ -1,3 +1,16 @@
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (is_code_density_p): Compare directly the
subclass field.
(is_spfp_p, is_dpfp_p, is_spfp_p): Define.
(check_cpu_feature): New function.
(find_opcode_match): Use check_cpu_feature function.
(preprocess_operands): Likewise.
(md_parse_option): Use mfpuda, mdpfp, mspfp options.
* testsuite/gas/arc/tdpfp.d: New file.
* testsuite/gas/arc/tfpuda.d: Likewise.
* testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16.

55
gas/config/tc-arc.c
View File

@ -93,7 +93,10 @@ enum arc_rlx_types
#define regno(x) ((x) & 0x3F)
#define is_ir_num(x) (((x) & ~0x3F) == 0)
#define is_code_density_p(op) (((op)->subclass == CD1 || (op)->subclass == CD2))
#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
#define is_spfp_p(op) (((sc) == SPX))
#define is_dpfp_p(op) (((sc) == DPX))
#define is_fpuda_p(op) (((sc) == DPA))
#define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
#define is_kernel_insn_p(op) (((op)->class == KERNEL))
@ -1344,6 +1347,30 @@ allocate_tok (expressionS *tok, int ntok, int cidx)
return allocate_tok (tok, ntok - 1, cidx);
}
/* Check if an particular ARC feature is enabled. */
static bfd_boolean
check_cpu_feature (insn_subclass_t sc)
{
if (!(arc_features & ARC_CD)
&& is_code_density_p (sc))
return FALSE;
if (!(arc_features & ARC_SPFP)
&& is_spfp_p (sc))
return FALSE;
if (!(arc_features & ARC_DPFP)
&& is_dpfp_p (sc))
return FALSE;
if (!(arc_features & ARC_FPUDA)
&& is_fpuda_p (sc))
return FALSE;
return TRUE;
}
/* Search forward through all variants of an opcode looking for a
syntax match. */
@ -1381,7 +1408,7 @@ find_opcode_match (const struct arc_opcode *first_opcode,
if (!(opcode->cpu & arc_target))
goto match_failed;
if (is_code_density_p (opcode) && !(arc_features & ARC_CD))
if (!check_cpu_feature (opcode->subclass))
goto match_failed;
got_cpu_match = 1;
@ -1972,7 +1999,9 @@ preprocess_operands (const struct arc_opcode *opcode,
auxr = &arc_aux_regs[0];
for (j = 0; j < arc_num_aux_regs; j++, auxr++)
if (len == auxr->length
&& strcasecmp (auxr->name, p) == 0)
&& (strcasecmp (auxr->name, p) == 0)
&& ((auxr->subclass == NONE)
|| check_cpu_feature (auxr->subclass)))
{
tok[i].X_op = O_constant;
tok[i].X_add_number = auxr->address;
@ -2951,6 +2980,8 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
/* This option has an effect only on ARC EM. */
if (arc_target & ARC_OPCODE_ARCv2EM)
arc_features |= ARC_CD;
else
as_warn (_("Code density option invalid for selected CPU"));
break;
case OPTION_RELAX:
@ -2967,8 +2998,17 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
case OPTION_EA:
case OPTION_MUL64:
case OPTION_SIMD:
/* Dummy options are accepted but have no effect. */
break;
case OPTION_SPFP:
arc_features |= ARC_SPFP;
break;
case OPTION_DPFP:
arc_features |= ARC_DPFP;
break;
case OPTION_XMAC_D16:
case OPTION_XMAC_24:
case OPTION_DSP_PACKA:
@ -2979,10 +3019,17 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
case OPTION_LOCK:
case OPTION_SWAPE:
case OPTION_RTSC:
case OPTION_FPUDA:
/* Dummy options are accepted but have no effect. */
break;
case OPTION_FPUDA:
/* This option has an effect only on ARC EM. */
if (arc_target & ARC_OPCODE_ARCv2EM)
arc_features |= ARC_FPUDA;
else
as_warn (_("FPUDA invalid for selected CPU"));
break;
default:
return 0;
}

28
gas/testsuite/gas/arc/tdpfp.d Normal file
View File

@ -0,0 +1,28 @@
#as:-mcpu=arcem -mdpfp
#objdump: -dr
#source: tfpx.s
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 24aa 008c lr r4,\[770\]
4: 23aa 004c lr r3,\[769\]
8: 24aa 010c lr r4,\[772\]
c: 23aa 00cc lr r3,\[771\]
10: 320c 00c1 daddh11 r1,r2,r3
14: 320d 00c1 daddh12 r1,r2,r3
18: 320e 00c1 daddh21 r1,r2,r3
1c: 320f 00c1 daddh22 r1,r2,r3
20: 3218 00c1 dexcl1 r1,r2,r3
24: 3219 00c1 dexcl2 r1,r2,r3
28: 3208 00c1 dmulh11 r1,r2,r3
2c: 3209 00c1 dmulh12 r1,r2,r3
30: 320a 00c1 dmulh21 r1,r2,r3
34: 320b 00c1 dmulh22 r1,r2,r3
38: 3210 00c1 dsubh11 r1,r2,r3
3c: 3211 00c1 dsubh12 r1,r2,r3
40: 3212 00c1 dsubh21 r1,r2,r3
44: 3213 00c1 dsubh22 r1,r2,r3

28
gas/testsuite/gas/arc/tfpuda.d Normal file
View File

@ -0,0 +1,28 @@
#as:-mcpu=arcem -mfpuda
#objdump: -dr
#source: tfpx.s
.*: +file format .*arc.*
Disassembly of section .text:
00000000 <.text>:
0: 24aa 00cc lr r4,\[771\]
4: 23aa 008c lr r3,\[770\]
8: 24aa 014c lr r4,\[773\]
c: 23aa 010c lr r3,\[772\]
10: 3234 00c1 daddh11 r1,r2,r3
14: 3235 00c1 daddh12 r1,r2,r3
18: 3236 00c1 daddh21 r1,r2,r3
1c: 3237 00c1 daddh22 r1,r2,r3
20: 323c 00c1 dexcl1 r1,r2,r3
24: 323d 00c1 dexcl2 r1,r2,r3
28: 3230 00c1 dmulh11 r1,r2,r3
2c: 3231 00c1 dmulh12 r1,r2,r3
30: 3232 00c1 dmulh21 r1,r2,r3
34: 3233 00c1 dmulh22 r1,r2,r3
38: 3238 00c1 dsubh11 r1,r2,r3
3c: 3239 00c1 dsubh12 r1,r2,r3
40: 323a 00c1 dsubh21 r1,r2,r3
44: 323b 00c1 dsubh22 r1,r2,r3

22
gas/testsuite/gas/arc/tfpx.s Normal file
View File

@ -0,0 +1,22 @@
lr r4,[d1h]
lr r3,[d1l]
lr r4,[d2h]
lr r3,[d2l]
daddh11 r1,r2,r3
daddh12 r1,r2,r3
daddh21 r1,r2,r3
daddh22 r1,r2,r3
dexcl1 r1,r2,r3
dexcl2 r1,r2,r3
dmulh11 r1,r2,r3
dmulh12 r1,r2,r3
dmulh21 r1,r2,r3
dmulh22 r1,r2,r3
dsubh11 r1,r2,r3
dsubh12 r1,r2,r3
dsubh21 r1,r2,r3
dsubh22 r1,r2,r3

8
include/ChangeLog
View File

@ -1,4 +1,10 @@
2016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
22016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (DPA, DPX, SPX): New subclass enums.
(ARC_FPUDA): Define.
(arc_aux_reg): Add new field.
016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
* opcode/arc-func.h (replace_bits24): Changed.
(replace_bits24_be): Created.

11
include/opcode/arc.h
View File

@ -59,6 +59,8 @@ typedef enum
CD2,
DIV,
DP,
DPA,
DPX,
MPY1E,
MPY6E,
MPY7E,
@ -68,7 +70,8 @@ typedef enum
SHFT1,
SHFT2,
SWAP,
SP
SP,
SPX
} insn_subclass_t;
/* Flags class. */
@ -148,6 +151,7 @@ extern const unsigned arc_num_opcodes;
#define ARC_DPFP 0x0010
#define ARC_SPFP 0x0020
#define ARC_FPU 0x0030
#define ARC_FPUDA 0x0040
/* NORM & SWAP. */
#define ARC_SWAP 0x0100
@ -403,7 +407,10 @@ struct arc_aux_reg
/* Register address. */
int address;
/* Register name. */
/* AUX register subclass. */
insn_subclass_t subclass;
/* Register name. */
const char *name;
/* Size of the string. */

9
opcodes/ChangeLog
View File

@ -1,3 +1,12 @@
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* arc-regs.h: Add a new subclass field. Add double assist
accumulator register values.
* arc-tbl.h: Use DPA subclass to mark the double assist
instructions. Use DPX/SPX subclas to mark the FPX instructions.
* arc-opc.c (RSP): Define instead of SP.
(arc_aux_regs): Add the subclass field.
2016-04-05 Jiong Wang <jiong.wang@arm.com>
* arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).

10
opcodes/arc-opc.c
View File

@ -1054,11 +1054,11 @@ const struct arc_operand arc_operands[] =
#define R3 (R2 + 1)
#define R3_S (R2 + 1)
{ 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
#define SP (R3 + 1)
#define RSP (R3 + 1)
#define SP_S (R3 + 1)
{ 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
#define SPdup (SP + 1)
#define SP_Sdup (SP + 1)
#define SPdup (RSP + 1)
#define SP_Sdup (RSP + 1)
{ 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
#define GP (SPdup + 1)
#define GP_S (SPdup + 1)
@ -1496,8 +1496,8 @@ const unsigned arc_num_pseudo_insn =
const struct arc_aux_reg arc_aux_regs[] =
{
#undef DEF
#define DEF(ADDR, NAME) \
{ ADDR, #NAME, sizeof (#NAME)-1 },
#define DEF(ADDR, SUBCLASS, NAME) \
{ ADDR, SUBCLASS, #NAME, sizeof (#NAME)-1 },
#include "arc-regs.h"

722
opcodes/arc-regs.h
View File

@ -19,362 +19,366 @@
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
DEF (0x0, STATUS)
DEF (0x1, SEMAPHORE)
DEF (0x2, LP_START)
DEF (0x3, LP_END)
DEF (0x4, IDENTITY)
DEF (0x5, DEBUG)
DEF (0x6, PC)
DEF (0x7, ADCR)
DEF (0x8, APCR)
DEF (0x9, ACR)
DEF (0xA, STATUS32)
DEF (0xB, STATUS32_L1)
DEF (0xC, STATUS32_L2)
DEF (0xF, BPU_FLUSH)
DEF (0x10, IVIC)
DEF (0x10, IC_IVIC)
DEF (0x11, CHE_MODE)
DEF (0x11, IC_CTRL)
DEF (0x12, MULHI)
DEF (0x13, LOCKLINE)
DEF (0x13, IC_LIL)
DEF (0x14, DMC_CODE_RAM)
DEF (0x15, TAG_ADDR_MASK)
DEF (0x16, TAG_DATA_MASK)
DEF (0x17, LINE_LENGTH_MASK)
DEF (0x18, AUX_LDST_RAM)
DEF (0x18, AUX_DCCM)
DEF (0x19, UNLOCKLINE)
DEF (0x19, IC_IVIL)
DEF (0x1A, IC_RAM_ADDRESS)
DEF (0x1B, IC_TAG)
DEF (0x1C, IC_WP)
DEF (0x1D, IC_DATA)
DEF (0x20, SRAM_SEQ)
DEF (0x21, COUNT0)
DEF (0x22, CONTROL0)
DEF (0x23, LIMIT0)
DEF (0x24, PCPORT)
DEF (0x25, INT_VECTOR_BASE)
DEF (0x26, AUX_VBFDW_MODE)
DEF (0x26, JLI_BASE)
DEF (0x27, AUX_VBFDW_BM0)
DEF (0x28, AUX_VBFDW_BM1)
DEF (0x29, AUX_VBFDW_ACCU)
DEF (0x2A, AUX_VBFDW_OFST)
DEF (0x2B, AUX_VBFDW_INTSTAT)
DEF (0x2C, AUX_XMAC0_24)
DEF (0x2D, AUX_XMAC1_24)
DEF (0x2E, AUX_XMAC2_24)
DEF (0x2F, AUX_FBF_STORE_16)
DEF (0x30, AX0)
DEF (0x31, AX1)
DEF (0x32, AUX_CRC_POLY)
DEF (0x33, AUX_CRC_MODE)
DEF (0x34, MX0)
DEF (0x35, MX1)
DEF (0x36, MY0)
DEF (0x37, MY1)
DEF (0x38, XYCONFIG)
DEF (0x39, SCRATCH_A)
DEF (0x3A, BURSTSYS)
DEF (0x3A, TSCH)
DEF (0x3B, BURSTXYM)
DEF (0x3C, BURSTSZ)
DEF (0x3D, BURSTVAL)
DEF (0x40, XTP_NEWVAL)
DEF (0x41, AUX_MACMODE)
DEF (0x42, LSP_NEWVAL)
DEF (0x43, AUX_IRQ_LV12)
DEF (0x44, AUX_XMAC0)
DEF (0x45, AUX_XMAC1)
DEF (0x46, AUX_XMAC2)
DEF (0x47, DC_IVDC)
DEF (0x48, DC_CTRL)
DEF (0x49, DC_LDL)
DEF (0x4A, DC_IVDL)
DEF (0x4B, DC_FLSH)
DEF (0x4C, DC_FLDL)
DEF (0x50, HEXDATA)
DEF (0x51, HEXCTRL)
DEF (0x52, LED)
DEF (0x56, DILSTAT)
DEF (0x57, SWSTAT)
DEF (0x58, DC_RAM_ADDR)
DEF (0x59, DC_TAG)
DEF (0x5A, DC_WP)
DEF (0x5B, DC_DATA)
DEF (0x61, DCCM_BASE_BUILD)
DEF (0x62, CRC_BUILD)
DEF (0x63, BTA_LINK_BUILD)
DEF (0x64, VBFDW_BUILD)
DEF (0x65, EA_BUILD)
DEF (0x66, DATASPACE)
DEF (0x67, MEMSUBSYS)
DEF (0x68, VECBASE_AC_BUILD)
DEF (0x69, P_BASE_ADDR)
DEF (0x6A, DATA_UNCACHED_BUILD)
DEF (0x6B, FP_BUILD)
DEF (0x6C, DPFP_BUILD)
DEF (0x6D, MPU_BUILD)
DEF (0x6E, RF_BUILD)
DEF (0x6F, MMU_BUILD)
DEF (0x70, AA2_BUILD)
DEF (0x71, VECBASE_BUILD)
DEF (0x72, D_CACHE_BUILD)
DEF (0x73, MADI_BUILD)
DEF (0x74, DCCM_BUILD)
DEF (0x75, TIMER_BUILD)
DEF (0x76, AP_BUILD)
DEF (0x77, I_CACHE_BUILD)
DEF (0x78, ICCM_BUILD)
DEF (0x79, DSPRAM_BUILD)
DEF (0x7A, MAC_BUILD)
DEF (0x7B, MULTIPLY_BUILD)
DEF (0x7C, SWAP_BUILD)
DEF (0x7D, NORM_BUILD)
DEF (0x7E, MINMAX_BUILD)
DEF (0x7F, BARREL_BUILD)
DEF (0x80, AX0)
DEF (0x81, AX1)
DEF (0x82, AX2)
DEF (0x83, AX3)
DEF (0x84, AY0)
DEF (0x85, AY1)
DEF (0x86, AY2)
DEF (0x87, AY3)
DEF (0x88, MX00)
DEF (0x89, MX01)
DEF (0x8A, MX10)
DEF (0x8B, MX11)
DEF (0x8C, MX20)
DEF (0x8D, MX21)
DEF (0x8E, MX30)
DEF (0x8F, MX31)
DEF (0x90, MY00)
DEF (0x91, MY01)
DEF (0x92, MY10)
DEF (0x93, MY11)
DEF (0x94, MY20)
DEF (0x95, MY21)
DEF (0x96, MY30)
DEF (0x97, MY31)
DEF (0x98, XYCONFIG)
DEF (0x99, BURSTSYS)
DEF (0x9A, BURSTXYM)
DEF (0x9B, BURSTSZ)
DEF (0x9C, BURSTVAL)
DEF (0x9D, XYLSBASEX)
DEF (0x9E, XYLSBASEY)
DEF (0x9F, AUX_XMACLW_H)
DEF (0xA0, AUX_XMACLW_L)
DEF (0xA1, SE_CTRL)
DEF (0xA2, SE_STAT)
DEF (0xA3, SE_ERR)
DEF (0xA4, SE_EADR)
DEF (0xA5, SE_SPC)
DEF (0xA6, SDM_BASE)
DEF (0xA7, SCM_BASE)
DEF (0xA8, SE_DBG_CTRL)
DEF (0xA9, SE_DBG_DATA0)
DEF (0xAA, SE_DBG_DATA1)
DEF (0xAB, SE_DBG_DATA2)
DEF (0xAC, SE_DBG_DATA3)
DEF (0xAD, SE_WATCH)
DEF (0xC0, BPU_BUILD)
DEF (0xC1, ARC600_BUILD_CONFIG)
DEF (0xC2, ISA_CONFIG)
DEF (0xF4, HWP_BUILD)
DEF (0xF5, PCT_BUILD)
DEF (0xF6, CC_BUILD)
DEF (0xF7, PM_BCR)
DEF (0xF8, SCQ_SWITCH_BUILD)
DEF (0xF9, VRAPTOR_BUILD)
DEF (0xFA, DMA_CONFIG)
DEF (0xFB, SIMD_CONFIG)
DEF (0xFC, VLC_BUILD)
DEF (0xFD, SIMD_DMA_BUILD)
DEF (0xFE, IFETCH_QUEUE_BUILD)
DEF (0xFF, SMART_BUILD)
DEF (0x100, COUNT1)
DEF (0x101, CONTROL1)
DEF (0x102, LIMIT1)
DEF (0x103, TIMER_XX)
DEF (0x120, ARCANGEL_PERIPH_XX)
DEF (0x140, PERIPH_XX)
DEF (0x200, AUX_IRQ_LEV)
DEF (0x201, AUX_IRQ_HINT)
DEF (0x202, AUX_INTER_CORE_INTERRUPT)
DEF (0x210, AES_AUX_0)
DEF (0x211, AES_AUX_1)
DEF (0x212, AES_AUX_2)
DEF (0x213, AES_CRYPT_MODE)
DEF (0x214, AES_AUXS)
DEF (0x215, AES_AUXI)
DEF (0x216, AES_AUX_3)
DEF (0x217, AES_AUX_4)
DEF (0x218, ARITH_CTL_AUX)
DEF (0x219, DES_AUX)
DEF (0x220, AP_AMV0)
DEF (0x221, AP_AMM0)
DEF (0x222, AP_AC0)
DEF (0x223, AP_AMV1)
DEF (0x224, AP_AMM1)
DEF (0x225, AP_AC1)
DEF (0x226, AP_AMV2)
DEF (0x227, AP_AMM2)
DEF (0x228, AP_AC2)
DEF (0x229, AP_AMV3)
DEF (0x22A, AP_AMM3)
DEF (0x22B, AP_AC3)
DEF (0x22C, AP_AMV4)
DEF (0x22D, AP_AMM4)
DEF (0x22E, AP_AC4)
DEF (0x22F, AP_AMV5)
DEF (0x230, AP_AMM5)
DEF (0x231, AP_AC5)
DEF (0x232, AP_AMV6)
DEF (0x233, AP_AMM6)
DEF (0x234, AP_AC6)
DEF (0x235, AP_AMV7)
DEF (0x236, AP_AMM7)
DEF (0x237, AP_AC7)
DEF (0x278, PCT_CONTROL)
DEF (0x279, PCT_BANK)
DEF (0x300, FP_STATUS)
DEF (0x301, AUX_DPFP1L)
DEF (0x301, D1L)
DEF (0x302, AUX_DPFP1H)
DEF (0x302, D1H)
DEF (0x303, AUX_DPFP2L)
DEF (0x303, D2L)
DEF (0x304, AUX_DPFP2H)
DEF (0x304, D2H)
DEF (0x305, DPFP_STATUS)
DEF (0x306, RTT)
DEF (0x400, ERET)
DEF (0x401, ERBTA)
DEF (0x402, ERSTATUS)
DEF (0x403, ECR)
DEF (0x404, EFA)
DEF (0x405, TLBPD0)
DEF (0x406, TLBPD1)
DEF (0x407, TLBIndex)
DEF (0x408, TLBCommand)
DEF (0x409, PID)
DEF (0x409, MPUEN)
DEF (0x40A, ICAUSE1)
DEF (0x40B, ICAUSE2)
DEF (0x40C, AUX_IENABLE)
DEF (0x40D, AUX_ITRIGGER)
DEF (0x410, XPU)
DEF (0x412, BTA)
DEF (0x413, BTA_L1)
DEF (0x414, BTA_L2)
DEF (0x415, AUX_IRQ_PULSE_CANCEL)
DEF (0x416, AUX_IRQ_PENDING)
DEF (0x418, SCRATCH_DATA0)
DEF (0x420, MPUIC)
DEF (0x421, MPUFA)
DEF (0x422, MPURDB0)
DEF (0x423, MPURDP0)
DEF (0x424, MPURDB1)
DEF (0x425, MPURDP1)
DEF (0x426, MPURDB2)
DEF (0x427, MPURDP2)
DEF (0x428, MPURDB3)
DEF (0x429, MPURDP3)
DEF (0x42A, MPURDB4)
DEF (0x42B, MPURDP4)
DEF (0x42C, MPURDB5)
DEF (0x42D, MPURDP5)
DEF (0x42E, MPURDB6)
DEF (0x42F, MPURDP6)
DEF (0x430, MPURDB7)
DEF (0x431, MPURDP7)
DEF (0x432, MPURDB8)
DEF (0x433, MPURDP8)
DEF (0x434, MPURDB9)
DEF (0x435, MPURDP9)
DEF (0x436, MPURDB10)
DEF (0x437, MPURDP10)
DEF (0x438, MPURDB11)
DEF (0x439, MPURDP11)
DEF (0x43A, MPURDB12)
DEF (0x43B, MPURDP12)
DEF (0x43C, MPURDB13)
DEF (0x43D, MPURDP13)
DEF (0x43E, MPURDB14)
DEF (0x43F, MPURDP14)
DEF (0x440, MPURDB15)
DEF (0x441, MPURDP15)
DEF (0x44F, EIA_FLAGS)
DEF (0x450, PM_STATUS)
DEF (0x451, WAKE)
DEF (0x452, DVFS_PERFORMANCE)
DEF (0x453, PWR_CTRL)
DEF (0x500, AUX_VLC_BUF_IDX)
DEF (0x501, AUX_VLC_READ_BUF)
DEF (0x502, AUX_VLC_VALID_BITS)
DEF (0x503, AUX_VLC_BUF_IN)
DEF (0x504, AUX_VLC_BUF_FREE)
DEF (0x505, AUX_VLC_IBUF_STATUS)
DEF (0x506, AUX_VLC_SETUP)
DEF (0x507, AUX_VLC_BITS)
DEF (0x508, AUX_VLC_TABLE)
DEF (0x509, AUX_VLC_GET_SYMBOL)
DEF (0x50A, AUX_VLC_READ_SYMBOL)
DEF (0x510, AUX_UCAVLC_SETUP)
DEF (0x511, AUX_UCAVLC_STATE)
DEF (0x512, AUX_CAVLC_ZERO_LEFT)
DEF (0x514, AUX_UVLC_I_STATE)
DEF (0x51C, AUX_VLC_DMA_PTR)
DEF (0x51D, AUX_VLC_DMA_END)
DEF (0x51E, AUX_VLC_DMA_ESC)
DEF (0x51F, AUX_VLC_DMA_CTRL)
DEF (0x520, AUX_VLC_GET_0BIT)
DEF (0x521, AUX_VLC_GET_1BIT)
DEF (0x522, AUX_VLC_GET_2BIT)
DEF (0x523, AUX_VLC_GET_3BIT)
DEF (0x524, AUX_VLC_GET_4BIT)
DEF (0x525, AUX_VLC_GET_5BIT)
DEF (0x526, AUX_VLC_GET_6BIT)
DEF (0x527, AUX_VLC_GET_7BIT)
DEF (0x528, AUX_VLC_GET_8BIT)
DEF (0x529, AUX_VLC_GET_9BIT)
DEF (0x52A, AUX_VLC_GET_10BIT)
DEF (0x52B, AUX_VLC_GET_11BIT)
DEF (0x52C, AUX_VLC_GET_12BIT)
DEF (0x52D, AUX_VLC_GET_13BIT)
DEF (0x52E, AUX_VLC_GET_14BIT)
DEF (0x52F, AUX_VLC_GET_15BIT)
DEF (0x530, AUX_VLC_GET_16BIT)
DEF (0x531, AUX_VLC_GET_17BIT)
DEF (0x532, AUX_VLC_GET_18BIT)
DEF (0x533, AUX_VLC_GET_19BIT)
DEF (0x534, AUX_VLC_GET_20BIT)
DEF (0x535, AUX_VLC_GET_21BIT)
DEF (0x536, AUX_VLC_GET_22BIT)
DEF (0x537, AUX_VLC_GET_23BIT)
DEF (0x538, AUX_VLC_GET_24BIT)
DEF (0x539, AUX_VLC_GET_25BIT)
DEF (0x53A, AUX_VLC_GET_26BIT)
DEF (0x53B, AUX_VLC_GET_27BIT)
DEF (0x53C, AUX_VLC_GET_28BIT)
DEF (0x53D, AUX_VLC_GET_29BIT)
DEF (0x53E, AUX_VLC_GET_30BIT)
DEF (0x53F, AUX_VLC_GET_31BIT)
DEF (0x540, AUX_CABAC_CTRL)
DEF (0x541, AUX_CABAC_CTX_STATE)
DEF (0x542, AUX_CABAC_COD_PARAM)
DEF (0x543, AUX_CABAC_MISC0)
DEF (0x544, AUX_CABAC_MISC1)
DEF (0x545, AUX_CABAC_MISC2)
DEF (0x600, ARC600_BUILD_CONFIG)
DEF (0x700, SMART_CONTROL)
DEF (0x701, SMART_DATA_0)
DEF (0x701, SMART_DATA_1)
DEF (0x701, SMART_DATA_2)
DEF (0x701, SMART_DATA_3)
DEF (0x0, NONE, STATUS)
DEF (0x1, NONE, SEMAPHORE)
DEF (0x2, NONE, LP_START)
DEF (0x3, NONE, LP_END)
DEF (0x4, NONE, IDENTITY)
DEF (0x5, NONE, DEBUG)
DEF (0x6, NONE, PC)
DEF (0x7, NONE, ADCR)
DEF (0x8, NONE, APCR)
DEF (0x9, NONE, ACR)
DEF (0xA, NONE, STATUS32)
DEF (0xB, NONE, STATUS32_L1)
DEF (0xC, NONE, STATUS32_L2)
DEF (0xF, NONE, BPU_FLUSH)
DEF (0x10, NONE, IVIC)
DEF (0x10, NONE, IC_IVIC)
DEF (0x11, NONE, CHE_MODE)
DEF (0x11, NONE, IC_CTRL)
DEF (0x12, NONE, MULHI)
DEF (0x13, NONE, LOCKLINE)
DEF (0x13, NONE, IC_LIL)
DEF (0x14, NONE, DMC_CODE_RAM)
DEF (0x15, NONE, TAG_ADDR_MASK)
DEF (0x16, NONE, TAG_DATA_MASK)
DEF (0x17, NONE, LINE_LENGTH_MASK)
DEF (0x18, NONE, AUX_LDST_RAM)
DEF (0x18, NONE, AUX_DCCM)
DEF (0x19, NONE, UNLOCKLINE)
DEF (0x19, NONE, IC_IVIL)
DEF (0x1A, NONE, IC_RAM_ADDRESS)
DEF (0x1B, NONE, IC_TAG)
DEF (0x1C, NONE, IC_WP)
DEF (0x1D, NONE, IC_DATA)
DEF (0x20, NONE, SRAM_SEQ)
DEF (0x21, NONE, COUNT0)
DEF (0x22, NONE, CONTROL0)
DEF (0x23, NONE, LIMIT0)
DEF (0x24, NONE, PCPORT)
DEF (0x25, NONE, INT_VECTOR_BASE)
DEF (0x26, NONE, AUX_VBFDW_MODE)
DEF (0x26, NONE, JLI_BASE)
DEF (0x27, NONE, AUX_VBFDW_BM0)
DEF (0x28, NONE, AUX_VBFDW_BM1)
DEF (0x29, NONE, AUX_VBFDW_ACCU)
DEF (0x2A, NONE, AUX_VBFDW_OFST)
DEF (0x2B, NONE, AUX_VBFDW_INTSTAT)
DEF (0x2C, NONE, AUX_XMAC0_24)
DEF (0x2D, NONE, AUX_XMAC1_24)
DEF (0x2E, NONE, AUX_XMAC2_24)
DEF (0x2F, NONE, AUX_FBF_STORE_16)
DEF (0x30, NONE, AX0)
DEF (0x31, NONE, AX1)
DEF (0x32, NONE, AUX_CRC_POLY)
DEF (0x33, NONE, AUX_CRC_MODE)
DEF (0x34, NONE, MX0)
DEF (0x35, NONE, MX1)
DEF (0x36, NONE, MY0)
DEF (0x37, NONE, MY1)
DEF (0x38, NONE, XYCONFIG)
DEF (0x39, NONE, SCRATCH_A)
DEF (0x3A, NONE, BURSTSYS)
DEF (0x3A, NONE, TSCH)
DEF (0x3B, NONE, BURSTXYM)
DEF (0x3C, NONE, BURSTSZ)
DEF (0x3D, NONE, BURSTVAL)
DEF (0x40, NONE, XTP_NEWVAL)
DEF (0x41, NONE, AUX_MACMODE)
DEF (0x42, NONE, LSP_NEWVAL)
DEF (0x43, NONE, AUX_IRQ_LV12)
DEF (0x44, NONE, AUX_XMAC0)
DEF (0x45, NONE, AUX_XMAC1)
DEF (0x46, NONE, AUX_XMAC2)
DEF (0x47, NONE, DC_IVDC)
DEF (0x48, NONE, DC_CTRL)
DEF (0x49, NONE, DC_LDL)
DEF (0x4A, NONE, DC_IVDL)
DEF (0x4B, NONE, DC_FLSH)
DEF (0x4C, NONE, DC_FLDL)
DEF (0x50, NONE, HEXDATA)
DEF (0x51, NONE, HEXCTRL)
DEF (0x52, NONE, LED)
DEF (0x56, NONE, DILSTAT)
DEF (0x57, NONE, SWSTAT)
DEF (0x58, NONE, DC_RAM_ADDR)
DEF (0x59, NONE, DC_TAG)
DEF (0x5A, NONE, DC_WP)
DEF (0x5B, NONE, DC_DATA)
DEF (0x61, NONE, DCCM_BASE_BUILD)
DEF (0x62, NONE, CRC_BUILD)
DEF (0x63, NONE, BTA_LINK_BUILD)
DEF (0x64, NONE, VBFDW_BUILD)
DEF (0x65, NONE, EA_BUILD)
DEF (0x66, NONE, DATASPACE)
DEF (0x67, NONE, MEMSUBSYS)
DEF (0x68, NONE, VECBASE_AC_BUILD)
DEF (0x69, NONE, P_BASE_ADDR)
DEF (0x6A, NONE, DATA_UNCACHED_BUILD)
DEF (0x6B, NONE, FP_BUILD)
DEF (0x6C, NONE, DPFP_BUILD)
DEF (0x6D, NONE, MPU_BUILD)
DEF (0x6E, NONE, RF_BUILD)
DEF (0x6F, NONE, MMU_BUILD)
DEF (0x70, NONE, AA2_BUILD)
DEF (0x71, NONE, VECBASE_BUILD)
DEF (0x72, NONE, D_CACHE_BUILD)
DEF (0x73, NONE, MADI_BUILD)
DEF (0x74, NONE, DCCM_BUILD)
DEF (0x75, NONE, TIMER_BUILD)
DEF (0x76, NONE, AP_BUILD)
DEF (0x77, NONE, I_CACHE_BUILD)
DEF (0x78, NONE, ICCM_BUILD)
DEF (0x79, NONE, DSPRAM_BUILD)
DEF (0x7A, NONE, MAC_BUILD)
DEF (0x7B, NONE, MULTIPLY_BUILD)
DEF (0x7C, NONE, SWAP_BUILD)
DEF (0x7D, NONE, NORM_BUILD)
DEF (0x7E, NONE, MINMAX_BUILD)
DEF (0x7F, NONE, BARREL_BUILD)
DEF (0x80, NONE, AX0)
DEF (0x81, NONE, AX1)
DEF (0x82, NONE, AX2)
DEF (0x83, NONE, AX3)
DEF (0x84, NONE, AY0)
DEF (0x85, NONE, AY1)
DEF (0x86, NONE, AY2)
DEF (0x87, NONE, AY3)
DEF (0x88, NONE, MX00)
DEF (0x89, NONE, MX01)
DEF (0x8A, NONE, MX10)
DEF (0x8B, NONE, MX11)
DEF (0x8C, NONE, MX20)
DEF (0x8D, NONE, MX21)
DEF (0x8E, NONE, MX30)
DEF (0x8F, NONE, MX31)
DEF (0x90, NONE, MY00)
DEF (0x91, NONE, MY01)
DEF (0x92, NONE, MY10)
DEF (0x93, NONE, MY11)
DEF (0x94, NONE, MY20)
DEF (0x95, NONE, MY21)
DEF (0x96, NONE, MY30)
DEF (0x97, NONE, MY31)
DEF (0x98, NONE, XYCONFIG)
DEF (0x99, NONE, BURSTSYS)
DEF (0x9A, NONE, BURSTXYM)
DEF (0x9B, NONE, BURSTSZ)
DEF (0x9C, NONE, BURSTVAL)
DEF (0x9D, NONE, XYLSBASEX)
DEF (0x9E, NONE, XYLSBASEY)
DEF (0x9F, NONE, AUX_XMACLW_H)
DEF (0xA0, NONE, AUX_XMACLW_L)
DEF (0xA1, NONE, SE_CTRL)
DEF (0xA2, NONE, SE_STAT)
DEF (0xA3, NONE, SE_ERR)
DEF (0xA4, NONE, SE_EADR)
DEF (0xA5, NONE, SE_SPC)
DEF (0xA6, NONE, SDM_BASE)
DEF (0xA7, NONE, SCM_BASE)
DEF (0xA8, NONE, SE_DBG_CTRL)
DEF (0xA9, NONE, SE_DBG_DATA0)
DEF (0xAA, NONE, SE_DBG_DATA1)
DEF (0xAB, NONE, SE_DBG_DATA2)
DEF (0xAC, NONE, SE_DBG_DATA3)
DEF (0xAD, NONE, SE_WATCH)
DEF (0xC0, NONE, BPU_BUILD)
DEF (0xC1, NONE, ARC600_BUILD_CONFIG)
DEF (0xC2, NONE, ISA_CONFIG)
DEF (0xF4, NONE, HWP_BUILD)
DEF (0xF5, NONE, PCT_BUILD)
DEF (0xF6, NONE, CC_BUILD)
DEF (0xF7, NONE, PM_BCR)
DEF (0xF8, NONE, SCQ_SWITCH_BUILD)
DEF (0xF9, NONE, VRAPTOR_BUILD)
DEF (0xFA, NONE, DMA_CONFIG)
DEF (0xFB, NONE, SIMD_CONFIG)
DEF (0xFC, NONE, VLC_BUILD)
DEF (0xFD, NONE, SIMD_DMA_BUILD)
DEF (0xFE, NONE, IFETCH_QUEUE_BUILD)
DEF (0xFF, NONE, SMART_BUILD)
DEF (0x100, NONE, COUNT1)
DEF (0x101, NONE, CONTROL1)
DEF (0x102, NONE, LIMIT1)
DEF (0x103, NONE, TIMER_XX)
DEF (0x120, NONE, ARCANGEL_PERIPH_XX)
DEF (0x140, NONE, PERIPH_XX)
DEF (0x200, NONE, AUX_IRQ_LEV)
DEF (0x201, NONE, AUX_IRQ_HINT)
DEF (0x202, NONE, AUX_INTER_CORE_INTERRUPT)
DEF (0x210, NONE, AES_AUX_0)
DEF (0x211, NONE, AES_AUX_1)
DEF (0x212, NONE, AES_AUX_2)
DEF (0x213, NONE, AES_CRYPT_MODE)
DEF (0x214, NONE, AES_AUXS)
DEF (0x215, NONE, AES_AUXI)
DEF (0x216, NONE, AES_AUX_3)
DEF (0x217, NONE, AES_AUX_4)
DEF (0x218, NONE, ARITH_CTL_AUX)
DEF (0x219, NONE, DES_AUX)
DEF (0x220, NONE, AP_AMV0)
DEF (0x221, NONE, AP_AMM0)
DEF (0x222, NONE, AP_AC0)
DEF (0x223, NONE, AP_AMV1)
DEF (0x224, NONE, AP_AMM1)
DEF (0x225, NONE, AP_AC1)
DEF (0x226, NONE, AP_AMV2)
DEF (0x227, NONE, AP_AMM2)
DEF (0x228, NONE, AP_AC2)
DEF (0x229, NONE, AP_AMV3)
DEF (0x22A, NONE, AP_AMM3)
DEF (0x22B, NONE, AP_AC3)
DEF (0x22C, NONE, AP_AMV4)
DEF (0x22D, NONE, AP_AMM4)
DEF (0x22E, NONE, AP_AC4)
DEF (0x22F, NONE, AP_AMV5)
DEF (0x230, NONE, AP_AMM5)
DEF (0x231, NONE, AP_AC5)
DEF (0x232, NONE, AP_AMV6)
DEF (0x233, NONE, AP_AMM6)
DEF (0x234, NONE, AP_AC6)
DEF (0x235, NONE, AP_AMV7)
DEF (0x236, NONE, AP_AMM7)
DEF (0x237, NONE, AP_AC7)
DEF (0x278, NONE, PCT_CONTROL)
DEF (0x279, NONE, PCT_BANK)
DEF (0x300, DPX, FP_STATUS)
DEF (0x301, DPX, AUX_DPFP1L)
DEF (0x301, DPX, D1L)
DEF (0x302, DPX, AUX_DPFP1H)
DEF (0x302, DPX, D1H)
DEF (0x302, DPA, D1L)
DEF (0x303, DPX, AUX_DPFP2L)
DEF (0x303, DPX, D2L)
DEF (0x303, DPA, D1H)
DEF (0x304, DPX, AUX_DPFP2H)
DEF (0x304, DPX, D2H)
DEF (0x304, DPA, D2L)
DEF (0x305, DPX, DPFP_STATUS)
DEF (0x305, DPA, D2H)
DEF (0x306, NONE, RTT)
DEF (0x400, NONE, ERET)
DEF (0x401, NONE, ERBTA)
DEF (0x402, NONE, ERSTATUS)
DEF (0x403, NONE, ECR)
DEF (0x404, NONE, EFA)
DEF (0x405, NONE, TLBPD0)
DEF (0x406, NONE, TLBPD1)
DEF (0x407, NONE, TLBIndex)
DEF (0x408, NONE, TLBCommand)
DEF (0x409, NONE, PID)
DEF (0x409, NONE, MPUEN)
DEF (0x40A, NONE, ICAUSE1)
DEF (0x40B, NONE, ICAUSE2)
DEF (0x40C, NONE, AUX_IENABLE)
DEF (0x40D, NONE, AUX_ITRIGGER)
DEF (0x410, NONE, XPU)
DEF (0x412, NONE, BTA)
DEF (0x413, NONE, BTA_L1)
DEF (0x414, NONE, BTA_L2)
DEF (0x415, NONE, AUX_IRQ_PULSE_CANCEL)
DEF (0x416, NONE, AUX_IRQ_PENDING)
DEF (0x418, NONE, SCRATCH_DATA0)
DEF (0x420, NONE, MPUIC)
DEF (0x421, NONE, MPUFA)
DEF (0x422, NONE, MPURDB0)
DEF (0x423, NONE, MPURDP0)
DEF (0x424, NONE, MPURDB1)
DEF (0x425, NONE, MPURDP1)
DEF (0x426, NONE, MPURDB2)
DEF (0x427, NONE, MPURDP2)
DEF (0x428, NONE, MPURDB3)
DEF (0x429, NONE, MPURDP3)
DEF (0x42A, NONE, MPURDB4)
DEF (0x42B, NONE, MPURDP4)
DEF (0x42C, NONE, MPURDB5)
DEF (0x42D, NONE, MPURDP5)
DEF (0x42E, NONE, MPURDB6)
DEF (0x42F, NONE, MPURDP6)
DEF (0x430, NONE, MPURDB7)
DEF (0x431, NONE, MPURDP7)
DEF (0x432, NONE, MPURDB8)
DEF (0x433, NONE, MPURDP8)
DEF (0x434, NONE, MPURDB9)
DEF (0x435, NONE, MPURDP9)
DEF (0x436, NONE, MPURDB10)
DEF (0x437, NONE, MPURDP10)
DEF (0x438, NONE, MPURDB11)
DEF (0x439, NONE, MPURDP11)
DEF (0x43A, NONE, MPURDB12)
DEF (0x43B, NONE, MPURDP12)
DEF (0x43C, NONE, MPURDB13)
DEF (0x43D, NONE, MPURDP13)
DEF (0x43E, NONE, MPURDB14)
DEF (0x43F, NONE, MPURDP14)
DEF (0x440, NONE, MPURDB15)
DEF (0x441, NONE, MPURDP15)
DEF (0x44F, NONE, EIA_FLAGS)
DEF (0x450, NONE, PM_STATUS)
DEF (0x451, NONE, WAKE)
DEF (0x452, NONE, DVFS_PERFORMANCE)
DEF (0x453, NONE, PWR_CTRL)
DEF (0x500, NONE, AUX_VLC_BUF_IDX)
DEF (0x501, NONE, AUX_VLC_READ_BUF)
DEF (0x502, NONE, AUX_VLC_VALID_BITS)
DEF (0x503, NONE, AUX_VLC_BUF_IN)
DEF (0x504, NONE, AUX_VLC_BUF_FREE)
DEF (0x505, NONE, AUX_VLC_IBUF_STATUS)
DEF (0x506, NONE, AUX_VLC_SETUP)
DEF (0x507, NONE, AUX_VLC_BITS)
DEF (0x508, NONE, AUX_VLC_TABLE)
DEF (0x509, NONE, AUX_VLC_GET_SYMBOL)
DEF (0x50A, NONE, AUX_VLC_READ_SYMBOL)
DEF (0x510, NONE, AUX_UCAVLC_SETUP)
DEF (0x511, NONE, AUX_UCAVLC_STATE)
DEF (0x512, NONE, AUX_CAVLC_ZERO_LEFT)
DEF (0x514, NONE, AUX_UVLC_I_STATE)
DEF (0x51C, NONE, AUX_VLC_DMA_PTR)
DEF (0x51D, NONE, AUX_VLC_DMA_END)
DEF (0x51E, NONE, AUX_VLC_DMA_ESC)
DEF (0x51F, NONE, AUX_VLC_DMA_CTRL)
DEF (0x520, NONE, AUX_VLC_GET_0BIT)
DEF (0x521, NONE, AUX_VLC_GET_1BIT)
DEF (0x522, NONE, AUX_VLC_GET_2BIT)
DEF (0x523, NONE, AUX_VLC_GET_3BIT)
DEF (0x524, NONE, AUX_VLC_GET_4BIT)
DEF (0x525, NONE, AUX_VLC_GET_5BIT)
DEF (0x526, NONE, AUX_VLC_GET_6BIT)
DEF (0x527, NONE, AUX_VLC_GET_7BIT)
DEF (0x528, NONE, AUX_VLC_GET_8BIT)
DEF (0x529, NONE, AUX_VLC_GET_9BIT)
DEF (0x52A, NONE, AUX_VLC_GET_10BIT)
DEF (0x52B, NONE, AUX_VLC_GET_11BIT)
DEF (0x52C, NONE, AUX_VLC_GET_12BIT)
DEF (0x52D, NONE, AUX_VLC_GET_13BIT)
DEF (0x52E, NONE, AUX_VLC_GET_14BIT)
DEF (0x52F, NONE, AUX_VLC_GET_15BIT)
DEF (0x530, NONE, AUX_VLC_GET_16BIT)
DEF (0x531, NONE, AUX_VLC_GET_17BIT)
DEF (0x532, NONE, AUX_VLC_GET_18BIT)
DEF (0x533, NONE, AUX_VLC_GET_19BIT)
DEF (0x534, NONE, AUX_VLC_GET_20BIT)
DEF (0x535, NONE, AUX_VLC_GET_21BIT)
DEF (0x536, NONE, AUX_VLC_GET_22BIT)
DEF (0x537, NONE, AUX_VLC_GET_23BIT)
DEF (0x538, NONE, AUX_VLC_GET_24BIT)
DEF (0x539, NONE, AUX_VLC_GET_25BIT)
DEF (0x53A, NONE, AUX_VLC_GET_26BIT)
DEF (0x53B, NONE, AUX_VLC_GET_27BIT)
DEF (0x53C, NONE, AUX_VLC_GET_28BIT)
DEF (0x53D, NONE, AUX_VLC_GET_29BIT)
DEF (0x53E, NONE, AUX_VLC_GET_30BIT)
DEF (0x53F, NONE, AUX_VLC_GET_31BIT)
DEF (0x540, NONE, AUX_CABAC_CTRL)
DEF (0x541, NONE, AUX_CABAC_CTX_STATE)
DEF (0x542, NONE, AUX_CABAC_COD_PARAM)
DEF (0x543, NONE, AUX_CABAC_MISC0)
DEF (0x544, NONE, AUX_CABAC_MISC1)
DEF (0x545, NONE, AUX_CABAC_MISC2)
DEF (0x600, NONE, ARC600_BUILD_CONFIG)
DEF (0x700, NONE, SMART_CONTROL)
DEF (0x701, NONE, SMART_DATA_0)
DEF (0x701, NONE, SMART_DATA_1)
DEF (0x701, NONE, SMART_DATA_2)
DEF (0x701, NONE, SMART_DATA_3)

1400
opcodes/arc-tbl.h
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