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sim: bfin: allow byteop[123]p src regs to be the same

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The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-03-24 03:08:15 +00:00
parent a9c3ef4760
commit 8d8a97461a
2 changed files with 5 additions and 9 deletions
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5
sim/bfin/ChangeLog
View File

@ -1,3 +1,8 @@
2011-03-23 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Drop the src0/src1 check for
BYTEOP1P, BYTEOP2P, and BYTEOP3P insns.
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* machs.c (bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev,

9
sim/bfin/bfin-sim.c
View File

@ -4185,9 +4185,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
src0 + 1, src0, src1 + 1, src1, opts[HL + (aop << 1)],
s ? ", r" : "");
if (src0 == src1)
illegal_instruction_combination (cpu);
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);
@ -4306,9 +4303,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
src0 + 1, src0, src1 + 1, src1, HL ? "HI" : "LO",
s ? ", R" : "");
if (src0 == src1)
illegal_instruction_combination (cpu);
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);
@ -4796,9 +4790,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "R%i = BYTEOP1P (R%i:%i, R%i:%i)%s;", dst0,
src0 + 1, src0, src1 + 1, src1, opts[s + (aop << 1)]);
if (src0 == src1)
illegal_instruction_combination (cpu);
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);