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* config/tc-mips.c (mips_cpu): New static variable.
(insns_since_cache_access): New static variable. (md_begin): Set mips_cpu as well as mips_isa. (append_insn): If mips_cpu is 4600, require four nop instructions between an instruction which accesses the cache and certain CACHE instructions. Keep track of the number of instructions seen since an instruction which accesses the cache. (md_parse_option): Set mips_cpu as well as mips_isa. PR 5433.
This commit is contained in:
Ian Lance Taylor
parent
942a4965b7
commit
8c63448afe
@ -1,10 +1,21 @@
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Tue Sep 6 11:42:38 1994 Ian Lance Taylor (ian@sanguine.cygnus.com)
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* config/tc-mips.c (mips_cpu): New static variable.
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(insns_since_cache_access): New static variable.
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(md_begin): Set mips_cpu as well as mips_isa.
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(append_insn): If mips_cpu is 4600, require four nop instructions
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between an instruction which accesses the cache and certain CACHE
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instructions. Keep track of the number of instructions seen since
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an instruction which accesses the cache.
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(md_parse_option): Set mips_cpu as well as mips_isa.
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Mon Sep 5 07:09:00 1994 Ken Raeburn (raeburn@kr-pc.cygnus.com)
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* doc/Makefile.in (VPATH): Define using @srcdir@.
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(prefix, program_transform_name, exec_prefix): Use autoconf style
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@-substitutions.
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Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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* config/ho-riscix.h, config/tc-arm.c, config/tc-arm.h: New files
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* configure.in: Recognize the arm.
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@ -114,6 +114,9 @@ static int mips_isa = -1;
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/* MIPS ISA we are using for this output file. */
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static int file_mips_isa;
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/* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
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static int mips_cpu;
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/* MIPS PIC level. */
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enum mips_pic_level
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@ -249,6 +252,12 @@ static int prev_insn_unreordered;
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/* Non-zero if the previous previous instruction was in a .set
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noreorder. */
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static int prev_prev_insn_unreordered;
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/* The number of instructions since the last instruction which
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accesses the data cache. The instruction itself counts as 1, so 0
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means no information. This is used to work around a bug on the
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r4600 (ORION) chip. */
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static int insns_since_cache_access;
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/* Since the MIPS does not have multiple forms of PC relative
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instructions, we do not have to do relaxing as is done on other
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@ -500,17 +509,55 @@ md_begin ()
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if (mips_isa == -1)
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{
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if (strcmp (TARGET_CPU, "mips") == 0)
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mips_isa = 1;
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else if (strcmp (TARGET_CPU, "r6000") == 0
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|| strcmp (TARGET_CPU, "mips2") == 0)
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mips_isa = 2;
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else if (strcmp (TARGET_CPU, "mips64") == 0
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|| strcmp (TARGET_CPU, "r4000") == 0
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|| strcmp (TARGET_CPU, "mips3") == 0)
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mips_isa = 3;
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const char *cpu;
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char *a = NULL;
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cpu = TARGET_CPU;
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if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
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{
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a = xmalloc (sizeof TARGET_CPU);
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strcpy (a, TARGET_CPU);
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a[(sizeof TARGET_CPU) - 3] = '\0';
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cpu = a;
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}
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if (strcmp (cpu, "mips") == 0)
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{
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mips_isa = 1;
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mips_cpu = 3000;
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}
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else if (strcmp (cpu, "r6000") == 0
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|| strcmp (cpu, "mips2") == 0)
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{
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mips_isa = 2;
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mips_cpu = 6000;
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}
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else if (strcmp (cpu, "mips64") == 0
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|| strcmp (cpu, "r4000") == 0
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|| strcmp (cpu, "mips3") == 0)
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{
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mips_isa = 3;
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mips_cpu = 4000;
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}
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else if (strcmp (cpu, "r4400") == 0)
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{
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mips_isa = 3;
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mips_cpu = 4400;
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}
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else if (strcmp (cpu, "mips64orion") == 0
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|| strcmp (cpu, "r4600") == 0)
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{
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mips_isa = 3;
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mips_cpu = 4600;
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}
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else
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mips_isa = 1;
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{
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mips_isa = 1;
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mips_cpu = 3000;
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}
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if (a != NULL)
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free (a);
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}
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if (mips_isa < 2 && mips_trap)
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@ -866,6 +913,18 @@ append_insn (place, ip, address_expr, reloc_type)
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&& (pinfo & INSN_WRITE_HI))))
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++nops;
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/* The r4600 (ORION) chip has a bug: at least four instructions
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are required between an instruction which accesses memory and
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a certain set of CACHE instructions. Handle that now. */
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if (mips_cpu == 4600
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&& insns_since_cache_access != 0
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&& 5 - insns_since_cache_access > nops
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&& ((ip->insn_opcode & 0xffff0000) == 0xbc0d0000
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|| (ip->insn_opcode & 0xffff0000) == 0xbc110000
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|| (ip->insn_opcode & 0xfc1f0000) == 0xbc150000
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|| (ip->insn_opcode & 0xffff0000) == 0xbc190000))
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nops = 5 - insns_since_cache_access;
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/* If we are being given a nop instruction, don't bother with
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one of the nops we would otherwise output. This will only
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happen when a nop instruction is used with mips_optimize set
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@ -876,8 +935,9 @@ append_insn (place, ip, address_expr, reloc_type)
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/* Now emit the right number of NOP instructions. */
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if (nops > 0)
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{
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emit_nop ();
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if (nops > 1)
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int i;
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for (i = 0; i < nops; i++)
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emit_nop ();
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if (listing)
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listing_prev_line ();
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@ -1168,6 +1228,11 @@ append_insn (place, ip, address_expr, reloc_type)
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prev_insn_where = f - frag_now->fr_literal;
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prev_insn_fixp = fixp;
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prev_insn_valid = 1;
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if ((pinfo & INSN_LOAD_MEMORY_DELAY) != 0
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|| (pinfo & INSN_STORE_MEMORY) != 0)
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insns_since_cache_access = 1;
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else if (insns_since_cache_access != 0)
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++insns_since_cache_access;
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}
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/* We just output an insn, so the next one doesn't have a label. */
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@ -4999,14 +5064,17 @@ md_parse_option (c, arg)
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case OPTION_MIPS1:
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mips_isa = 1;
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mips_cpu = 3000;
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break;
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case OPTION_MIPS2:
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mips_isa = 2;
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mips_cpu = 6000;
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break;
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case OPTION_MIPS3:
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mips_isa = 3;
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mips_cpu = 4000;
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break;
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case OPTION_MCPU:
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@ -5030,35 +5098,58 @@ md_parse_option (c, arg)
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if (strcmp (p, "2000") == 0
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|| strcmp (p, "2k") == 0
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|| strcmp (p, "2K") == 0)
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mips_isa = 1;
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{
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mips_isa = 1;
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mips_cpu = 2000;
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}
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break;
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case '3':
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if (strcmp (p, "3000") == 0
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|| strcmp (p, "3k") == 0
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|| strcmp (p, "3K") == 0)
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mips_isa = 1;
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{
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mips_isa = 1;
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mips_cpu = 3000;
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}
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break;
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case '4':
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if (strcmp (p, "4000") == 0
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|| strcmp (p, "4k") == 0
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|| strcmp (p, "4K") == 0
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|| strcmp (p, "4400") == 0
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|| strcmp (p, "4600") == 0)
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mips_isa = 3;
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|| strcmp (p, "4K") == 0)
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{
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mips_isa = 3;
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mips_cpu = 4000;
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}
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else if (strcmp (p, "4400") == 0)
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{
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mips_isa = 3;
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mips_cpu = 4400;
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}
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else if (strcmp (p, "4600") == 0)
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{
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mips_isa = 3;
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mips_cpu = 4600;
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}
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break;
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case '6':
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if (strcmp (p, "6000") == 0
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|| strcmp (p, "6k") == 0
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|| strcmp (p, "6K") == 0)
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mips_isa = 2;
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{
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mips_isa = 2;
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mips_cpu = 6000;
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}
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break;
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case 'o':
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if (strcmp (p, "orion") == 0)
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mips_isa = 3;
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{
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mips_isa = 3;
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mips_cpu = 4600;
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}
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break;
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}
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