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sim: generated files for the eBPF simulator
This patch adds the CGEN generated files for the eBPF simulator. sim/ChangeLog: 2020-08-04 Jose E. Marchesi <jose.marchesi@oracle.com> David Faust <david.faust@oracle.com> * bpf/arch.c: Likewise. * bpf/arch.h: Likewise. * bpf/cpu.c: Likewise. * bpf/cpu.h: Likewise. * bpf/cpuall.h: Likewise. * bpf/decode-be.c: Likewise. * bpf/decode-be.h: Likewise. * bpf/decode-le.c: Likewise. * bpf/decode-le.h: Likewise. * bpf/defs-be.h: Likewise. * bpf/defs-le.h: Likewise. * bpf/sem-be.c: Likewise. * bpf/sem-le.c: Likewise.
This commit is contained in:
Jose E. Marchesi
parent
b26e2ae7d3
commit
8c4c18181e
@ -1,3 +1,20 @@
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2020-08-04 Jose E. Marchesi <jose.marchesi@oracle.com>
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David Faust <david.faust@oracle.com>
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* bpf/arch.c: Likewise.
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* bpf/arch.h: Likewise.
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* bpf/cpu.c: Likewise.
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* bpf/cpu.h: Likewise.
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* bpf/cpuall.h: Likewise.
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* bpf/decode-be.c: Likewise.
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* bpf/decode-be.h: Likewise.
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* bpf/decode-le.c: Likewise.
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* bpf/decode-le.h: Likewise.
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* bpf/defs-be.h: Likewise.
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* bpf/defs-le.h: Likewise.
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* bpf/sem-be.c: Likewise.
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* bpf/sem-le.c: Likewise.
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2020-08-04 Jose E. Marchesi <jose.marchesi@oracle.com>
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David Faust <david.faust@oracle.com>
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35
sim/bpf/arch.c
Normal file
35
sim/bpf/arch.c
Normal file
@ -0,0 +1,35 @@
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/* Simulator support for bpf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2020 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "sim-main.h"
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#include "bfd.h"
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const SIM_MACH *sim_machs[] =
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{
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#ifdef HAVE_CPU_BPFBF
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& bpf_mach,
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#endif
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0
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};
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50
sim/bpf/arch.h
Normal file
50
sim/bpf/arch.h
Normal file
@ -0,0 +1,50 @@
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/* Simulator header for bpf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2020 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef BPF_ARCH_H
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#define BPF_ARCH_H
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#define TARGET_BIG_ENDIAN 1
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#define WI DI
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#define UWI UDI
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#define AI UDI
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#define IAI UDI
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/* Enum declaration for model types. */
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typedef enum model_type {
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MODEL_BPF_DEF, MODEL_MAX
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} MODEL_TYPE;
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#define MAX_MODELS ((int) MODEL_MAX)
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/* Enum declaration for unit types. */
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typedef enum unit_type {
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UNIT_NONE, UNIT_BPF_DEF_U_EXEC, UNIT_MAX
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} UNIT_TYPE;
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#define MAX_UNITS (1)
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#endif /* BPF_ARCH_H */
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69
sim/bpf/cpu.c
Normal file
69
sim/bpf/cpu.c
Normal file
@ -0,0 +1,69 @@
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/* Misc. support for CPU family bpfbf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2020 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#define WANT_CPU bpfbf
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#define WANT_CPU_BPFBF
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#include "sim-main.h"
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#include "cgen-ops.h"
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/* Get the value of h-gpr. */
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DI
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bpfbf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return CPU (h_gpr[regno]);
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}
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/* Set a value for h-gpr. */
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void
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bpfbf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
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{
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CPU (h_gpr[regno]) = newval;
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}
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/* Get the value of h-pc. */
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UDI
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bpfbf_h_pc_get (SIM_CPU *current_cpu)
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{
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return GET_H_PC ();
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}
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/* Set a value for h-pc. */
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void
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bpfbf_h_pc_set (SIM_CPU *current_cpu, UDI newval)
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{
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SET_H_PC (newval);
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}
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/* Record trace results for INSN. */
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void
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bpfbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
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int *indices, TRACE_RECORD *tr)
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{
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}
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81
sim/bpf/cpu.h
Normal file
81
sim/bpf/cpu.h
Normal file
@ -0,0 +1,81 @@
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/* CPU family header for bpfbf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2020 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef CPU_BPFBF_H
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#define CPU_BPFBF_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 1
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* The size of an "int" needed to hold an instruction word.
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This is usually 32 bits, but some architectures needs 64 bits. */
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typedef CGEN_INSN_LGUINT CGEN_INSN_WORD;
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#include "cgen-engine.h"
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* General Purpose Registers */
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DI h_gpr[16];
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#define GET_H_GPR(a1) CPU (h_gpr)[a1]
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#define SET_H_GPR(a1, x) (CPU (h_gpr)[a1] = (x))
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/* program counter */
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UDI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) \
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do { \
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CPU (h_pc) = (x);\
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;} while (0)
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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} BPFBF_CPU_DATA;
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/* Cover fns for register access. */
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DI bpfbf_h_gpr_get (SIM_CPU *, UINT);
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void bpfbf_h_gpr_set (SIM_CPU *, UINT, DI);
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UDI bpfbf_h_pc_get (SIM_CPU *);
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void bpfbf_h_pc_set (SIM_CPU *, UDI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN bpfbf_fetch_register;
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extern CPUREG_STORE_FN bpfbf_store_register;
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typedef struct {
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int empty;
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} MODEL_BPF_DEF_DATA;
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/* Collection of various things for the trace handler to use. */
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typedef struct trace_record {
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IADDR pc;
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/* FIXME:wip */
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} TRACE_RECORD;
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#endif /* CPU_BPFBF_H */
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65
sim/bpf/cpuall.h
Normal file
65
sim/bpf/cpuall.h
Normal file
@ -0,0 +1,65 @@
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/* Simulator CPU header for bpf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2020 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
|
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any later version.
|
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|
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
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|
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You should have received a copy of the GNU General Public License along
|
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef BPF_CPUALL_H
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#define BPF_CPUALL_H
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/* Include files for each cpu family. */
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#ifdef WANT_CPU_BPFBF
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#include "eng.h"
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#include "cpu.h"
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#include "decode.h"
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#endif
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extern const SIM_MACH bpf_mach;
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#ifndef WANT_CPU
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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IADDR addr;
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const IDESC *idesc;
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char trace_p;
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char profile_p;
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/* ??? Temporary hack for skip insns. */
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char skip_count;
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char unused;
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/* cpu specific data follows */
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};
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#endif
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#ifndef WANT_CPU
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/* A cached insn.
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??? SCACHE used to contain more than just argbuf. We could delete the
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type entirely and always just use ARGBUF, but for future concerns and as
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a level of abstraction it is left in. */
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struct scache {
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struct argbuf argbuf;
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};
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#endif
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#endif /* BPF_CPUALL_H */
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1129
sim/bpf/decode-be.c
Normal file
1129
sim/bpf/decode-be.c
Normal file
File diff suppressed because it is too large
Load Diff
94
sim/bpf/decode-be.h
Normal file
94
sim/bpf/decode-be.h
Normal file
@ -0,0 +1,94 @@
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/* Decode header for bpfbf_ebpfbe.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2020 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
|
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|
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This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
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It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef BPFBF_EBPFBE_DECODE_H
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#define BPFBF_EBPFBE_DECODE_H
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extern const IDESC *bpfbf_ebpfbe_decode (SIM_CPU *, IADDR,
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CGEN_INSN_WORD,
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ARGBUF *);
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extern void bpfbf_ebpfbe_init_idesc_table (SIM_CPU *);
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extern void bpfbf_ebpfbe_sem_init_idesc_table (SIM_CPU *);
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extern void bpfbf_ebpfbe_semf_init_idesc_table (SIM_CPU *);
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/* Enum declaration for instructions in cpu family bpfbf. */
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typedef enum bpfbf_ebpfbe_insn_type {
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BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_AFTER, BPFBF_EBPFBE_INSN_X_BEFORE, BPFBF_EBPFBE_INSN_X_CTI_CHAIN
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, BPFBF_EBPFBE_INSN_X_CHAIN, BPFBF_EBPFBE_INSN_X_BEGIN, BPFBF_EBPFBE_INSN_ADDIBE, BPFBF_EBPFBE_INSN_ADDRBE
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, BPFBF_EBPFBE_INSN_ADD32IBE, BPFBF_EBPFBE_INSN_ADD32RBE, BPFBF_EBPFBE_INSN_SUBIBE, BPFBF_EBPFBE_INSN_SUBRBE
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, BPFBF_EBPFBE_INSN_SUB32IBE, BPFBF_EBPFBE_INSN_SUB32RBE, BPFBF_EBPFBE_INSN_MULIBE, BPFBF_EBPFBE_INSN_MULRBE
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, BPFBF_EBPFBE_INSN_MUL32IBE, BPFBF_EBPFBE_INSN_MUL32RBE, BPFBF_EBPFBE_INSN_DIVIBE, BPFBF_EBPFBE_INSN_DIVRBE
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, BPFBF_EBPFBE_INSN_DIV32IBE, BPFBF_EBPFBE_INSN_DIV32RBE, BPFBF_EBPFBE_INSN_ORIBE, BPFBF_EBPFBE_INSN_ORRBE
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, BPFBF_EBPFBE_INSN_OR32IBE, BPFBF_EBPFBE_INSN_OR32RBE, BPFBF_EBPFBE_INSN_ANDIBE, BPFBF_EBPFBE_INSN_ANDRBE
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, BPFBF_EBPFBE_INSN_AND32IBE, BPFBF_EBPFBE_INSN_AND32RBE, BPFBF_EBPFBE_INSN_LSHIBE, BPFBF_EBPFBE_INSN_LSHRBE
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, BPFBF_EBPFBE_INSN_LSH32IBE, BPFBF_EBPFBE_INSN_LSH32RBE, BPFBF_EBPFBE_INSN_RSHIBE, BPFBF_EBPFBE_INSN_RSHRBE
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, BPFBF_EBPFBE_INSN_RSH32IBE, BPFBF_EBPFBE_INSN_RSH32RBE, BPFBF_EBPFBE_INSN_MODIBE, BPFBF_EBPFBE_INSN_MODRBE
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, BPFBF_EBPFBE_INSN_MOD32IBE, BPFBF_EBPFBE_INSN_MOD32RBE, BPFBF_EBPFBE_INSN_XORIBE, BPFBF_EBPFBE_INSN_XORRBE
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, BPFBF_EBPFBE_INSN_XOR32IBE, BPFBF_EBPFBE_INSN_XOR32RBE, BPFBF_EBPFBE_INSN_ARSHIBE, BPFBF_EBPFBE_INSN_ARSHRBE
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, BPFBF_EBPFBE_INSN_ARSH32IBE, BPFBF_EBPFBE_INSN_ARSH32RBE, BPFBF_EBPFBE_INSN_NEGBE, BPFBF_EBPFBE_INSN_NEG32BE
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, BPFBF_EBPFBE_INSN_MOVIBE, BPFBF_EBPFBE_INSN_MOVRBE, BPFBF_EBPFBE_INSN_MOV32IBE, BPFBF_EBPFBE_INSN_MOV32RBE
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, BPFBF_EBPFBE_INSN_ENDLEBE, BPFBF_EBPFBE_INSN_ENDBEBE, BPFBF_EBPFBE_INSN_LDDWBE, BPFBF_EBPFBE_INSN_LDABSW
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, BPFBF_EBPFBE_INSN_LDABSH, BPFBF_EBPFBE_INSN_LDABSB, BPFBF_EBPFBE_INSN_LDABSDW, BPFBF_EBPFBE_INSN_LDINDWBE
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, BPFBF_EBPFBE_INSN_LDINDHBE, BPFBF_EBPFBE_INSN_LDINDBBE, BPFBF_EBPFBE_INSN_LDINDDWBE, BPFBF_EBPFBE_INSN_LDXWBE
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, BPFBF_EBPFBE_INSN_LDXHBE, BPFBF_EBPFBE_INSN_LDXBBE, BPFBF_EBPFBE_INSN_LDXDWBE, BPFBF_EBPFBE_INSN_STXWBE
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, BPFBF_EBPFBE_INSN_STXHBE, BPFBF_EBPFBE_INSN_STXBBE, BPFBF_EBPFBE_INSN_STXDWBE, BPFBF_EBPFBE_INSN_STBBE
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, BPFBF_EBPFBE_INSN_STHBE, BPFBF_EBPFBE_INSN_STWBE, BPFBF_EBPFBE_INSN_STDWBE, BPFBF_EBPFBE_INSN_JEQIBE
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, BPFBF_EBPFBE_INSN_JEQRBE, BPFBF_EBPFBE_INSN_JEQ32IBE, BPFBF_EBPFBE_INSN_JEQ32RBE, BPFBF_EBPFBE_INSN_JGTIBE
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, BPFBF_EBPFBE_INSN_JGTRBE, BPFBF_EBPFBE_INSN_JGT32IBE, BPFBF_EBPFBE_INSN_JGT32RBE, BPFBF_EBPFBE_INSN_JGEIBE
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, BPFBF_EBPFBE_INSN_JGERBE, BPFBF_EBPFBE_INSN_JGE32IBE, BPFBF_EBPFBE_INSN_JGE32RBE, BPFBF_EBPFBE_INSN_JLTIBE
|
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, BPFBF_EBPFBE_INSN_JLTRBE, BPFBF_EBPFBE_INSN_JLT32IBE, BPFBF_EBPFBE_INSN_JLT32RBE, BPFBF_EBPFBE_INSN_JLEIBE
|
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, BPFBF_EBPFBE_INSN_JLERBE, BPFBF_EBPFBE_INSN_JLE32IBE, BPFBF_EBPFBE_INSN_JLE32RBE, BPFBF_EBPFBE_INSN_JSETIBE
|
||||
, BPFBF_EBPFBE_INSN_JSETRBE, BPFBF_EBPFBE_INSN_JSET32IBE, BPFBF_EBPFBE_INSN_JSET32RBE, BPFBF_EBPFBE_INSN_JNEIBE
|
||||
, BPFBF_EBPFBE_INSN_JNERBE, BPFBF_EBPFBE_INSN_JNE32IBE, BPFBF_EBPFBE_INSN_JNE32RBE, BPFBF_EBPFBE_INSN_JSGTIBE
|
||||
, BPFBF_EBPFBE_INSN_JSGTRBE, BPFBF_EBPFBE_INSN_JSGT32IBE, BPFBF_EBPFBE_INSN_JSGT32RBE, BPFBF_EBPFBE_INSN_JSGEIBE
|
||||
, BPFBF_EBPFBE_INSN_JSGERBE, BPFBF_EBPFBE_INSN_JSGE32IBE, BPFBF_EBPFBE_INSN_JSGE32RBE, BPFBF_EBPFBE_INSN_JSLTIBE
|
||||
, BPFBF_EBPFBE_INSN_JSLTRBE, BPFBF_EBPFBE_INSN_JSLT32IBE, BPFBF_EBPFBE_INSN_JSLT32RBE, BPFBF_EBPFBE_INSN_JSLEIBE
|
||||
, BPFBF_EBPFBE_INSN_JSLERBE, BPFBF_EBPFBE_INSN_JSLE32IBE, BPFBF_EBPFBE_INSN_JSLE32RBE, BPFBF_EBPFBE_INSN_CALLBE
|
||||
, BPFBF_EBPFBE_INSN_JA, BPFBF_EBPFBE_INSN_EXIT, BPFBF_EBPFBE_INSN_XADDDWBE, BPFBF_EBPFBE_INSN_XADDWBE
|
||||
, BPFBF_EBPFBE_INSN_BRKPT, BPFBF_EBPFBE_INSN__MAX
|
||||
} BPFBF_EBPFBE_INSN_TYPE;
|
||||
|
||||
/* Enum declaration for semantic formats in cpu family bpfbf. */
|
||||
typedef enum bpfbf_ebpfbe_sfmt_type {
|
||||
BPFBF_EBPFBE_SFMT_EMPTY, BPFBF_EBPFBE_SFMT_ADDIBE, BPFBF_EBPFBE_SFMT_ADDRBE, BPFBF_EBPFBE_SFMT_NEGBE
|
||||
, BPFBF_EBPFBE_SFMT_MOVIBE, BPFBF_EBPFBE_SFMT_MOVRBE, BPFBF_EBPFBE_SFMT_ENDLEBE, BPFBF_EBPFBE_SFMT_LDDWBE
|
||||
, BPFBF_EBPFBE_SFMT_LDABSW, BPFBF_EBPFBE_SFMT_LDABSH, BPFBF_EBPFBE_SFMT_LDABSB, BPFBF_EBPFBE_SFMT_LDABSDW
|
||||
, BPFBF_EBPFBE_SFMT_LDINDWBE, BPFBF_EBPFBE_SFMT_LDINDHBE, BPFBF_EBPFBE_SFMT_LDINDBBE, BPFBF_EBPFBE_SFMT_LDINDDWBE
|
||||
, BPFBF_EBPFBE_SFMT_LDXWBE, BPFBF_EBPFBE_SFMT_LDXHBE, BPFBF_EBPFBE_SFMT_LDXBBE, BPFBF_EBPFBE_SFMT_LDXDWBE
|
||||
, BPFBF_EBPFBE_SFMT_STXWBE, BPFBF_EBPFBE_SFMT_STXHBE, BPFBF_EBPFBE_SFMT_STXBBE, BPFBF_EBPFBE_SFMT_STXDWBE
|
||||
, BPFBF_EBPFBE_SFMT_STBBE, BPFBF_EBPFBE_SFMT_STHBE, BPFBF_EBPFBE_SFMT_STWBE, BPFBF_EBPFBE_SFMT_STDWBE
|
||||
, BPFBF_EBPFBE_SFMT_JEQIBE, BPFBF_EBPFBE_SFMT_JEQRBE, BPFBF_EBPFBE_SFMT_CALLBE, BPFBF_EBPFBE_SFMT_JA
|
||||
, BPFBF_EBPFBE_SFMT_EXIT, BPFBF_EBPFBE_SFMT_XADDDWBE, BPFBF_EBPFBE_SFMT_XADDWBE
|
||||
} BPFBF_EBPFBE_SFMT_TYPE;
|
||||
|
||||
/* Function unit handlers (user written). */
|
||||
|
||||
extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
|
||||
/* Profiling before/after handlers (user written) */
|
||||
|
||||
extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
|
||||
extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
|
||||
|
||||
#endif /* BPFBF_EBPFBE_DECODE_H */
|
||||
1129
sim/bpf/decode-le.c
Normal file
1129
sim/bpf/decode-le.c
Normal file
File diff suppressed because it is too large
Load Diff
94
sim/bpf/decode-le.h
Normal file
94
sim/bpf/decode-le.h
Normal file
@ -0,0 +1,94 @@
|
||||
/* Decode header for bpfbf_ebpfle.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2020 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef BPFBF_EBPFLE_DECODE_H
|
||||
#define BPFBF_EBPFLE_DECODE_H
|
||||
|
||||
extern const IDESC *bpfbf_ebpfle_decode (SIM_CPU *, IADDR,
|
||||
CGEN_INSN_WORD,
|
||||
ARGBUF *);
|
||||
extern void bpfbf_ebpfle_init_idesc_table (SIM_CPU *);
|
||||
extern void bpfbf_ebpfle_sem_init_idesc_table (SIM_CPU *);
|
||||
extern void bpfbf_ebpfle_semf_init_idesc_table (SIM_CPU *);
|
||||
|
||||
/* Enum declaration for instructions in cpu family bpfbf. */
|
||||
typedef enum bpfbf_ebpfle_insn_type {
|
||||
BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_AFTER, BPFBF_EBPFLE_INSN_X_BEFORE, BPFBF_EBPFLE_INSN_X_CTI_CHAIN
|
||||
, BPFBF_EBPFLE_INSN_X_CHAIN, BPFBF_EBPFLE_INSN_X_BEGIN, BPFBF_EBPFLE_INSN_ADDILE, BPFBF_EBPFLE_INSN_ADDRLE
|
||||
, BPFBF_EBPFLE_INSN_ADD32ILE, BPFBF_EBPFLE_INSN_ADD32RLE, BPFBF_EBPFLE_INSN_SUBILE, BPFBF_EBPFLE_INSN_SUBRLE
|
||||
, BPFBF_EBPFLE_INSN_SUB32ILE, BPFBF_EBPFLE_INSN_SUB32RLE, BPFBF_EBPFLE_INSN_MULILE, BPFBF_EBPFLE_INSN_MULRLE
|
||||
, BPFBF_EBPFLE_INSN_MUL32ILE, BPFBF_EBPFLE_INSN_MUL32RLE, BPFBF_EBPFLE_INSN_DIVILE, BPFBF_EBPFLE_INSN_DIVRLE
|
||||
, BPFBF_EBPFLE_INSN_DIV32ILE, BPFBF_EBPFLE_INSN_DIV32RLE, BPFBF_EBPFLE_INSN_ORILE, BPFBF_EBPFLE_INSN_ORRLE
|
||||
, BPFBF_EBPFLE_INSN_OR32ILE, BPFBF_EBPFLE_INSN_OR32RLE, BPFBF_EBPFLE_INSN_ANDILE, BPFBF_EBPFLE_INSN_ANDRLE
|
||||
, BPFBF_EBPFLE_INSN_AND32ILE, BPFBF_EBPFLE_INSN_AND32RLE, BPFBF_EBPFLE_INSN_LSHILE, BPFBF_EBPFLE_INSN_LSHRLE
|
||||
, BPFBF_EBPFLE_INSN_LSH32ILE, BPFBF_EBPFLE_INSN_LSH32RLE, BPFBF_EBPFLE_INSN_RSHILE, BPFBF_EBPFLE_INSN_RSHRLE
|
||||
, BPFBF_EBPFLE_INSN_RSH32ILE, BPFBF_EBPFLE_INSN_RSH32RLE, BPFBF_EBPFLE_INSN_MODILE, BPFBF_EBPFLE_INSN_MODRLE
|
||||
, BPFBF_EBPFLE_INSN_MOD32ILE, BPFBF_EBPFLE_INSN_MOD32RLE, BPFBF_EBPFLE_INSN_XORILE, BPFBF_EBPFLE_INSN_XORRLE
|
||||
, BPFBF_EBPFLE_INSN_XOR32ILE, BPFBF_EBPFLE_INSN_XOR32RLE, BPFBF_EBPFLE_INSN_ARSHILE, BPFBF_EBPFLE_INSN_ARSHRLE
|
||||
, BPFBF_EBPFLE_INSN_ARSH32ILE, BPFBF_EBPFLE_INSN_ARSH32RLE, BPFBF_EBPFLE_INSN_NEGLE, BPFBF_EBPFLE_INSN_NEG32LE
|
||||
, BPFBF_EBPFLE_INSN_MOVILE, BPFBF_EBPFLE_INSN_MOVRLE, BPFBF_EBPFLE_INSN_MOV32ILE, BPFBF_EBPFLE_INSN_MOV32RLE
|
||||
, BPFBF_EBPFLE_INSN_ENDLELE, BPFBF_EBPFLE_INSN_ENDBELE, BPFBF_EBPFLE_INSN_LDDWLE, BPFBF_EBPFLE_INSN_LDABSW
|
||||
, BPFBF_EBPFLE_INSN_LDABSH, BPFBF_EBPFLE_INSN_LDABSB, BPFBF_EBPFLE_INSN_LDABSDW, BPFBF_EBPFLE_INSN_LDINDWLE
|
||||
, BPFBF_EBPFLE_INSN_LDINDHLE, BPFBF_EBPFLE_INSN_LDINDBLE, BPFBF_EBPFLE_INSN_LDINDDWLE, BPFBF_EBPFLE_INSN_LDXWLE
|
||||
, BPFBF_EBPFLE_INSN_LDXHLE, BPFBF_EBPFLE_INSN_LDXBLE, BPFBF_EBPFLE_INSN_LDXDWLE, BPFBF_EBPFLE_INSN_STXWLE
|
||||
, BPFBF_EBPFLE_INSN_STXHLE, BPFBF_EBPFLE_INSN_STXBLE, BPFBF_EBPFLE_INSN_STXDWLE, BPFBF_EBPFLE_INSN_STBLE
|
||||
, BPFBF_EBPFLE_INSN_STHLE, BPFBF_EBPFLE_INSN_STWLE, BPFBF_EBPFLE_INSN_STDWLE, BPFBF_EBPFLE_INSN_JEQILE
|
||||
, BPFBF_EBPFLE_INSN_JEQRLE, BPFBF_EBPFLE_INSN_JEQ32ILE, BPFBF_EBPFLE_INSN_JEQ32RLE, BPFBF_EBPFLE_INSN_JGTILE
|
||||
, BPFBF_EBPFLE_INSN_JGTRLE, BPFBF_EBPFLE_INSN_JGT32ILE, BPFBF_EBPFLE_INSN_JGT32RLE, BPFBF_EBPFLE_INSN_JGEILE
|
||||
, BPFBF_EBPFLE_INSN_JGERLE, BPFBF_EBPFLE_INSN_JGE32ILE, BPFBF_EBPFLE_INSN_JGE32RLE, BPFBF_EBPFLE_INSN_JLTILE
|
||||
, BPFBF_EBPFLE_INSN_JLTRLE, BPFBF_EBPFLE_INSN_JLT32ILE, BPFBF_EBPFLE_INSN_JLT32RLE, BPFBF_EBPFLE_INSN_JLEILE
|
||||
, BPFBF_EBPFLE_INSN_JLERLE, BPFBF_EBPFLE_INSN_JLE32ILE, BPFBF_EBPFLE_INSN_JLE32RLE, BPFBF_EBPFLE_INSN_JSETILE
|
||||
, BPFBF_EBPFLE_INSN_JSETRLE, BPFBF_EBPFLE_INSN_JSET32ILE, BPFBF_EBPFLE_INSN_JSET32RLE, BPFBF_EBPFLE_INSN_JNEILE
|
||||
, BPFBF_EBPFLE_INSN_JNERLE, BPFBF_EBPFLE_INSN_JNE32ILE, BPFBF_EBPFLE_INSN_JNE32RLE, BPFBF_EBPFLE_INSN_JSGTILE
|
||||
, BPFBF_EBPFLE_INSN_JSGTRLE, BPFBF_EBPFLE_INSN_JSGT32ILE, BPFBF_EBPFLE_INSN_JSGT32RLE, BPFBF_EBPFLE_INSN_JSGEILE
|
||||
, BPFBF_EBPFLE_INSN_JSGERLE, BPFBF_EBPFLE_INSN_JSGE32ILE, BPFBF_EBPFLE_INSN_JSGE32RLE, BPFBF_EBPFLE_INSN_JSLTILE
|
||||
, BPFBF_EBPFLE_INSN_JSLTRLE, BPFBF_EBPFLE_INSN_JSLT32ILE, BPFBF_EBPFLE_INSN_JSLT32RLE, BPFBF_EBPFLE_INSN_JSLEILE
|
||||
, BPFBF_EBPFLE_INSN_JSLERLE, BPFBF_EBPFLE_INSN_JSLE32ILE, BPFBF_EBPFLE_INSN_JSLE32RLE, BPFBF_EBPFLE_INSN_CALLLE
|
||||
, BPFBF_EBPFLE_INSN_JA, BPFBF_EBPFLE_INSN_EXIT, BPFBF_EBPFLE_INSN_XADDDWLE, BPFBF_EBPFLE_INSN_XADDWLE
|
||||
, BPFBF_EBPFLE_INSN_BRKPT, BPFBF_EBPFLE_INSN__MAX
|
||||
} BPFBF_EBPFLE_INSN_TYPE;
|
||||
|
||||
/* Enum declaration for semantic formats in cpu family bpfbf. */
|
||||
typedef enum bpfbf_ebpfle_sfmt_type {
|
||||
BPFBF_EBPFLE_SFMT_EMPTY, BPFBF_EBPFLE_SFMT_ADDILE, BPFBF_EBPFLE_SFMT_ADDRLE, BPFBF_EBPFLE_SFMT_NEGLE
|
||||
, BPFBF_EBPFLE_SFMT_MOVILE, BPFBF_EBPFLE_SFMT_MOVRLE, BPFBF_EBPFLE_SFMT_ENDLELE, BPFBF_EBPFLE_SFMT_LDDWLE
|
||||
, BPFBF_EBPFLE_SFMT_LDABSW, BPFBF_EBPFLE_SFMT_LDABSH, BPFBF_EBPFLE_SFMT_LDABSB, BPFBF_EBPFLE_SFMT_LDABSDW
|
||||
, BPFBF_EBPFLE_SFMT_LDINDWLE, BPFBF_EBPFLE_SFMT_LDINDHLE, BPFBF_EBPFLE_SFMT_LDINDBLE, BPFBF_EBPFLE_SFMT_LDINDDWLE
|
||||
, BPFBF_EBPFLE_SFMT_LDXWLE, BPFBF_EBPFLE_SFMT_LDXHLE, BPFBF_EBPFLE_SFMT_LDXBLE, BPFBF_EBPFLE_SFMT_LDXDWLE
|
||||
, BPFBF_EBPFLE_SFMT_STXWLE, BPFBF_EBPFLE_SFMT_STXHLE, BPFBF_EBPFLE_SFMT_STXBLE, BPFBF_EBPFLE_SFMT_STXDWLE
|
||||
, BPFBF_EBPFLE_SFMT_STBLE, BPFBF_EBPFLE_SFMT_STHLE, BPFBF_EBPFLE_SFMT_STWLE, BPFBF_EBPFLE_SFMT_STDWLE
|
||||
, BPFBF_EBPFLE_SFMT_JEQILE, BPFBF_EBPFLE_SFMT_JEQRLE, BPFBF_EBPFLE_SFMT_CALLLE, BPFBF_EBPFLE_SFMT_JA
|
||||
, BPFBF_EBPFLE_SFMT_EXIT, BPFBF_EBPFLE_SFMT_XADDDWLE, BPFBF_EBPFLE_SFMT_XADDWLE
|
||||
} BPFBF_EBPFLE_SFMT_TYPE;
|
||||
|
||||
/* Function unit handlers (user written). */
|
||||
|
||||
extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
|
||||
/* Profiling before/after handlers (user written) */
|
||||
|
||||
extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
|
||||
extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
|
||||
|
||||
#endif /* BPFBF_EBPFLE_DECODE_H */
|
||||
383
sim/bpf/defs-be.h
Normal file
383
sim/bpf/defs-be.h
Normal file
@ -0,0 +1,383 @@
|
||||
/* ISA definitions header for ebpfbe.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2020 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef DEFS_BPFBF_EBPFBE_H
|
||||
#define DEFS_BPFBF_EBPFBE_H
|
||||
|
||||
/* Instruction argument buffer. */
|
||||
|
||||
union sem_fields {
|
||||
struct { /* no operands */
|
||||
int empty;
|
||||
} sfmt_empty;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_srcbe;
|
||||
} sfmt_ldindwbe;
|
||||
struct { /* */
|
||||
DI f_imm64;
|
||||
UINT f_dstbe;
|
||||
} sfmt_lddwbe;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_dstbe;
|
||||
HI f_offset16;
|
||||
} sfmt_stbbe;
|
||||
struct { /* */
|
||||
UINT f_dstbe;
|
||||
UINT f_srcbe;
|
||||
HI f_offset16;
|
||||
} sfmt_ldxwbe;
|
||||
#if WITH_SCACHE_PBB
|
||||
/* Writeback handler. */
|
||||
struct {
|
||||
/* Pointer to argbuf entry for insn whose results need writing back. */
|
||||
const struct argbuf *abuf;
|
||||
} write;
|
||||
/* x-before handler */
|
||||
struct {
|
||||
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
|
||||
int first_p;
|
||||
} before;
|
||||
/* x-after handler */
|
||||
struct {
|
||||
int empty;
|
||||
} after;
|
||||
/* This entry is used to terminate each pbb. */
|
||||
struct {
|
||||
/* Number of insns in pbb. */
|
||||
int insn_count;
|
||||
/* Next pbb to execute. */
|
||||
SCACHE *next;
|
||||
SCACHE *branch_target;
|
||||
} chain;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The ARGBUF struct. */
|
||||
struct argbuf {
|
||||
/* These are the baseclass definitions. */
|
||||
IADDR addr;
|
||||
const IDESC *idesc;
|
||||
char trace_p;
|
||||
char profile_p;
|
||||
/* ??? Temporary hack for skip insns. */
|
||||
char skip_count;
|
||||
char unused;
|
||||
/* cpu specific data follows */
|
||||
union sem semantic;
|
||||
int written;
|
||||
union sem_fields fields;
|
||||
};
|
||||
|
||||
/* A cached insn.
|
||||
|
||||
??? SCACHE used to contain more than just argbuf. We could delete the
|
||||
type entirely and always just use ARGBUF, but for future concerns and as
|
||||
a level of abstraction it is left in. */
|
||||
|
||||
struct scache {
|
||||
struct argbuf argbuf;
|
||||
};
|
||||
|
||||
/* Macros to simplify extraction, reading and semantic code.
|
||||
These define and assign the local vars that contain the insn's fields. */
|
||||
|
||||
#define EXTRACT_IFMT_EMPTY_VARS \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EMPTY_CODE \
|
||||
length = 0; \
|
||||
|
||||
#define EXTRACT_IFMT_ADDIBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDIBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ADDRBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDRBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_NEGBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_NEGBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ENDLEBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ENDLEBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDDWBE_VARS \
|
||||
UINT f_imm64_a; \
|
||||
UINT f_imm64_b; \
|
||||
UINT f_imm64_c; \
|
||||
DI f_imm64; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
/* Contents of trailing part of insn. */ \
|
||||
UINT word_1; \
|
||||
UINT word_2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDDWBE_CODE \
|
||||
length = 16; \
|
||||
word_1 = GETIMEMUSI (current_cpu, pc + 8); \
|
||||
word_2 = GETIMEMUSI (current_cpu, pc + 12); \
|
||||
f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
|
||||
f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \
|
||||
{\
|
||||
f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\
|
||||
}\
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDABSW_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDABSW_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDINDWBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDINDWBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDXWBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDXWBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_STBBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_STBBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQIBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQIBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQRBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQRBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_CALLBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_CALLBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JA_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JA_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_EXIT_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EXIT_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#endif /* DEFS_BPFBF_EBPFBE_H */
|
||||
383
sim/bpf/defs-le.h
Normal file
383
sim/bpf/defs-le.h
Normal file
@ -0,0 +1,383 @@
|
||||
/* ISA definitions header for ebpfle.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2020 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef DEFS_BPFBF_EBPFLE_H
|
||||
#define DEFS_BPFBF_EBPFLE_H
|
||||
|
||||
/* Instruction argument buffer. */
|
||||
|
||||
union sem_fields {
|
||||
struct { /* no operands */
|
||||
int empty;
|
||||
} sfmt_empty;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_srcle;
|
||||
} sfmt_ldindwle;
|
||||
struct { /* */
|
||||
DI f_imm64;
|
||||
UINT f_dstle;
|
||||
} sfmt_lddwle;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_dstle;
|
||||
HI f_offset16;
|
||||
} sfmt_stble;
|
||||
struct { /* */
|
||||
UINT f_dstle;
|
||||
UINT f_srcle;
|
||||
HI f_offset16;
|
||||
} sfmt_ldxwle;
|
||||
#if WITH_SCACHE_PBB
|
||||
/* Writeback handler. */
|
||||
struct {
|
||||
/* Pointer to argbuf entry for insn whose results need writing back. */
|
||||
const struct argbuf *abuf;
|
||||
} write;
|
||||
/* x-before handler */
|
||||
struct {
|
||||
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
|
||||
int first_p;
|
||||
} before;
|
||||
/* x-after handler */
|
||||
struct {
|
||||
int empty;
|
||||
} after;
|
||||
/* This entry is used to terminate each pbb. */
|
||||
struct {
|
||||
/* Number of insns in pbb. */
|
||||
int insn_count;
|
||||
/* Next pbb to execute. */
|
||||
SCACHE *next;
|
||||
SCACHE *branch_target;
|
||||
} chain;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The ARGBUF struct. */
|
||||
struct argbuf {
|
||||
/* These are the baseclass definitions. */
|
||||
IADDR addr;
|
||||
const IDESC *idesc;
|
||||
char trace_p;
|
||||
char profile_p;
|
||||
/* ??? Temporary hack for skip insns. */
|
||||
char skip_count;
|
||||
char unused;
|
||||
/* cpu specific data follows */
|
||||
union sem semantic;
|
||||
int written;
|
||||
union sem_fields fields;
|
||||
};
|
||||
|
||||
/* A cached insn.
|
||||
|
||||
??? SCACHE used to contain more than just argbuf. We could delete the
|
||||
type entirely and always just use ARGBUF, but for future concerns and as
|
||||
a level of abstraction it is left in. */
|
||||
|
||||
struct scache {
|
||||
struct argbuf argbuf;
|
||||
};
|
||||
|
||||
/* Macros to simplify extraction, reading and semantic code.
|
||||
These define and assign the local vars that contain the insn's fields. */
|
||||
|
||||
#define EXTRACT_IFMT_EMPTY_VARS \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EMPTY_CODE \
|
||||
length = 0; \
|
||||
|
||||
#define EXTRACT_IFMT_ADDILE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDILE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ADDRLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDRLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_NEGLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_NEGLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ENDLELE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ENDLELE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDDWLE_VARS \
|
||||
UINT f_imm64_a; \
|
||||
UINT f_imm64_b; \
|
||||
UINT f_imm64_c; \
|
||||
DI f_imm64; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
/* Contents of trailing part of insn. */ \
|
||||
UINT word_1; \
|
||||
UINT word_2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDDWLE_CODE \
|
||||
length = 16; \
|
||||
word_1 = GETIMEMUSI (current_cpu, pc + 8); \
|
||||
word_2 = GETIMEMUSI (current_cpu, pc + 12); \
|
||||
f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
|
||||
f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \
|
||||
{\
|
||||
f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\
|
||||
}\
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDABSW_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDABSW_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDINDWLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDINDWLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDXWLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDXWLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_STBLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_STBLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQILE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQILE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQRLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQRLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_CALLLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_CALLLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JA_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JA_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_EXIT_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EXIT_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#endif /* DEFS_BPFBF_EBPFLE_H */
|
||||
3207
sim/bpf/sem-be.c
Normal file
3207
sim/bpf/sem-be.c
Normal file
File diff suppressed because it is too large
Load Diff
3207
sim/bpf/sem-le.c
Normal file
3207
sim/bpf/sem-le.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user