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Arm64: correct uzp{1,2} mnemonics

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According to the specification, and in line with the pre-existing
predicate forms, the mnemonics do not include an 'i'.
This commit is contained in:
Jan Beulich 2020-01-03 10:13:31 +01:00
parent f4950f76fa
commit 8c45011acd
6 changed files with 23 additions and 12 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
2020-01-03 Jan Beulich <jbeulich@suse.com> 2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.d, * testsuite/gas/aarch64/f64mm.d,

8
gas/testsuite/gas/aarch64/f64mm.d
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@ -52,10 +52,10 @@ Disassembly of section \.text:
*[0-9a-f]+: 05a00000 zip1 z0\.q, z0\.q, z0\.q *[0-9a-f]+: 05a00000 zip1 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a506b1 zip2 z17\.q, z21\.q, z5\.q *[0-9a-f]+: 05a506b1 zip2 z17\.q, z21\.q, z5\.q
*[0-9a-f]+: 05a00400 zip2 z0\.q, z0\.q, z0\.q *[0-9a-f]+: 05a00400 zip2 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a50ab1 uzip1 z17\.q, z21\.q, z5\.q *[0-9a-f]+: 05a50ab1 uzp1 z17\.q, z21\.q, z5\.q
*[0-9a-f]+: 05a00800 uzip1 z0\.q, z0\.q, z0\.q *[0-9a-f]+: 05a00800 uzp1 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a50eb1 uzip2 z17\.q, z21\.q, z5\.q *[0-9a-f]+: 05a50eb1 uzp2 z17\.q, z21\.q, z5\.q
*[0-9a-f]+: 05a00c00 uzip2 z0\.q, z0\.q, z0\.q *[0-9a-f]+: 05a00c00 uzp2 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a51ab1 trn1 z17\.q, z21\.q, z5\.q *[0-9a-f]+: 05a51ab1 trn1 z17\.q, z21\.q, z5\.q
*[0-9a-f]+: 05a01800 trn1 z0\.q, z0\.q, z0\.q *[0-9a-f]+: 05a01800 trn1 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a51eb1 trn2 z17\.q, z21\.q, z5\.q *[0-9a-f]+: 05a51eb1 trn2 z17\.q, z21\.q, z5\.q

8
gas/testsuite/gas/aarch64/f64mm.s
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@ -60,10 +60,10 @@ zip1 z0.q, z0.q, z0.q
zip2 z17.q, z21.q, z5.q zip2 z17.q, z21.q, z5.q
zip2 z0.q, z0.q, z0.q zip2 z0.q, z0.q, z0.q
uzip1 z17.q, z21.q, z5.q uzp1 z17.q, z21.q, z5.q
uzip1 z0.q, z0.q, z0.q uzp1 z0.q, z0.q, z0.q
uzip2 z17.q, z21.q, z5.q uzp2 z17.q, z21.q, z5.q
uzip2 z0.q, z0.q, z0.q uzp2 z0.q, z0.q, z0.q
trn1 z17.q, z21.q, z5.q trn1 z17.q, z21.q, z5.q
trn1 z0.q, z0.q, z0.q trn1 z0.q, z0.q, z0.q

6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2020-01-03 Jan Beulich <jbeulich@suse.com>
* opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
uzip{1,2}.
* opcodes/aarch64-dis-2.c: Re-generate.
2020-01-03 Jan Beulich <jbeulich@suse.com> 2020-01-03 Jan Beulich <jbeulich@suse.com>
* opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit

4
opcodes/aarch64-dis-2.c
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@ -9913,7 +9913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
/* 33222222222211111111110000000000 /* 33222222222211111111110000000000
10987654321098765432109876543210 10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx 000001x1101xxxxx000010xxxxxxxxxx
uzip1. */ uzp1. */
return 2409; return 2409;
} }
else else
@ -9943,7 +9943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
/* 33222222222211111111110000000000 /* 33222222222211111111110000000000
10987654321098765432109876543210 10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx 000001x1101xxxxx000011xxxxxxxxxx
uzip2. */ uzp2. */
return 2410; return 2410;
} }
else else

4
opcodes/aarch64-tbl.h
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@ -5084,8 +5084,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0), F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0),
F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("uzip1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("uzp1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("uzip2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("uzp2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
/* Matrix Multiply advanced SIMD instructions. */ /* Matrix Multiply advanced SIMD instructions. */