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* frv-tdep.h (fsr0_regnum, acc0_regnum, acc7_regnum, accg0123_regnum)
(accg4567_regnum, msr0_regnum, msr1_regnum, gner0_regnum) (gner1_regnum, fner0_regnum, fner1_regnum, accg0_regnum) (accg7_regnum): New constants. (last_spr_regnum, last_pseudo_regnum): Update. * frv-tdep.c (new_variant): Initialize names for fsr0, acc0-acc7, accg0-accg7, msr0, msr1, gner0, gner1, fner0, and fner1. (frv_pseudo_register_read, frv_pseudo_register_write): Add support for accg registers. (frv_register_sim_regno): Update spr_map[].
This commit is contained in:
parent
973d1c04bc
commit
8b67aa36ea
@ -1,3 +1,16 @@
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2004-04-05 Kevin Buettner <kevinb@redhat.com>
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* frv-tdep.h (fsr0_regnum, acc0_regnum, acc7_regnum, accg0123_regnum)
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(accg4567_regnum, msr0_regnum, msr1_regnum, gner0_regnum)
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(gner1_regnum, fner0_regnum, fner1_regnum, accg0_regnum)
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(accg7_regnum): New constants.
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(last_spr_regnum, last_pseudo_regnum): Update.
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(new_variant): Initialize names for fsr0, acc0-acc7, accg0-accg7,
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msr0, msr1, gner0, gner1, fner0, and fner1.
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(frv_pseudo_register_read, frv_pseudo_register_write): Add support
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for accg registers.
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(frv_register_sim_regno): Update spr_map[].
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2004-04-04 Andrew Cagney <cagney@redhat.com>
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* config/mips/xm-riscos.h: Delete.
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@ -200,6 +200,44 @@ new_variant (void)
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var->register_names[iacc0l_regnum] = "iacc0l";
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var->register_names[iacc0_regnum] = "iacc0";
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/* fsr0 (Found on FR555 and FR501.) */
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var->register_names[fsr0_regnum] = "fsr0";
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/* acc0 - acc7. The architecture provides for the possibility of many
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more (up to 64 total), but we don't want to make that big of a hole
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in the G packet. If we need more in the future, we'll add them
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elsewhere. */
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for (r = acc0_regnum; r <= acc7_regnum; r++)
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{
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char *buf;
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xasprintf (&buf, "acc%d", r - acc0_regnum);
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var->register_names[r] = buf;
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}
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/* accg0 - accg7: These are one byte registers. The remote protocol
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provides the raw values packed four into a slot. accg0123 and
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accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
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We don't provide names for accg0123 and accg4567 since the user will
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likely not want to see these raw values. */
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for (r = accg0_regnum; r <= accg7_regnum; r++)
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{
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char *buf;
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xasprintf (&buf, "accg%d", r - accg0_regnum);
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var->register_names[r] = buf;
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}
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/* msr0 and msr1. */
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var->register_names[msr0_regnum] = "msr0";
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var->register_names[msr1_regnum] = "msr1";
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/* gner and fner registers. */
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var->register_names[gner0_regnum] = "gner0";
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var->register_names[gner1_regnum] = "gner1";
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var->register_names[fner0_regnum] = "fner0";
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var->register_names[fner1_regnum] = "fner1";
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return var;
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}
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@ -290,6 +328,21 @@ frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
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regcache_raw_read (regcache, iacc0h_regnum, buffer);
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regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
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}
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else if (accg0_regnum <= reg && reg <= accg7_regnum)
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{
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/* The accg raw registers have four values in each slot with the
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lowest register number occupying the first byte. */
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int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
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int byte_num = (reg - accg0_regnum) % 4;
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bfd_byte buf[4];
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regcache_raw_read (regcache, raw_regnum, buf);
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memset (buffer, 0, 4);
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/* FR-V is big endian, so put the requested byte in the first byte
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of the buffer allocated to hold the pseudo-register. */
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((bfd_byte *) buffer)[0] = buf[byte_num];
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}
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}
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static void
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@ -301,6 +354,19 @@ frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
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regcache_raw_write (regcache, iacc0h_regnum, buffer);
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regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
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}
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else if (accg0_regnum <= reg && reg <= accg7_regnum)
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{
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/* The accg raw registers have four values in each slot with the
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lowest register number occupying the first byte. */
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int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
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int byte_num = (reg - accg0_regnum) % 4;
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char buf[4];
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regcache_raw_read (regcache, raw_regnum, buf);
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buf[byte_num] = ((bfd_byte *) buffer)[0];
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regcache_raw_write (regcache, raw_regnum, buf);
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}
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}
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static int
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@ -311,8 +377,8 @@ frv_register_sim_regno (int reg)
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H_SPR_PSR, /* psr_regnum */
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H_SPR_CCR, /* ccr_regnum */
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H_SPR_CCCR, /* cccr_regnum */
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-1, /* 132 */
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-1, /* 133 */
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-1, /* fdpic_loadmap_exec_regnum */
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-1, /* fdpic_loadmap_interp_regnum */
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-1, /* 134 */
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H_SPR_TBR, /* tbr_regnum */
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H_SPR_BRR, /* brr_regnum */
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@ -320,14 +386,32 @@ frv_register_sim_regno (int reg)
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H_SPR_DBAR1, /* dbar1_regnum */
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H_SPR_DBAR2, /* dbar2_regnum */
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H_SPR_DBAR3, /* dbar3_regnum */
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-1, /* 141 */
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-1, /* 142 */
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-1, /* 143 */
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-1, /* 144 */
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H_SPR_SCR0, /* scr0_regnum */
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H_SPR_SCR1, /* scr1_regnum */
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H_SPR_SCR2, /* scr2_regnum */
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H_SPR_SCR3, /* scr3_regnum */
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H_SPR_LR, /* lr_regnum */
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H_SPR_LCR, /* lcr_regnum */
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H_SPR_IACC0H, /* iacc0h_regnum */
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H_SPR_IACC0L /* iacc0l_regnum */
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H_SPR_IACC0L, /* iacc0l_regnum */
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H_SPR_FSR0, /* fsr0_regnum */
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/* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
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-1, /* acc0_regnum */
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-1, /* acc1_regnum */
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-1, /* acc2_regnum */
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-1, /* acc3_regnum */
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-1, /* acc4_regnum */
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-1, /* acc5_regnum */
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-1, /* acc6_regnum */
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-1, /* acc7_regnum */
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-1, /* acc0123_regnum */
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-1, /* acc4567_regnum */
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H_SPR_MSR0, /* msr0_regnum */
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H_SPR_MSR1, /* msr1_regnum */
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H_SPR_GNER0, /* gner0_regnum */
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H_SPR_GNER1, /* gner1_regnum */
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H_SPR_FNER0, /* fner0_regnum */
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H_SPR_FNER1, /* fner1_regnum */
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};
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gdb_assert (reg >= 0 && reg < NUM_REGS);
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@ -66,7 +66,18 @@ enum {
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lcr_regnum = 146,
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iacc0h_regnum = 147,
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iacc0l_regnum = 148,
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last_spr_regnum = 148,
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fsr0_regnum = 149,
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acc0_regnum = 150,
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acc7_regnum = 157,
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accg0123_regnum = 158,
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accg4567_regnum = 159,
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msr0_regnum = 160,
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msr1_regnum = 161,
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gner0_regnum = 162,
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gner1_regnum = 163,
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fner0_regnum = 164,
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fner1_regnum = 165,
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last_spr_regnum = 165,
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/* The total number of registers we know exist. */
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frv_num_regs = last_spr_regnum + 1,
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@ -76,8 +87,10 @@ enum {
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/* iacc0 - the 64-bit concatenation of iacc0h and iacc0l. */
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iacc0_regnum = first_pseudo_regnum + 0,
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accg0_regnum = first_pseudo_regnum + 1,
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accg7_regnum = accg0_regnum + 7,
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last_pseudo_regnum = iacc0_regnum,
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last_pseudo_regnum = accg7_regnum,
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frv_num_pseudo_regs = last_pseudo_regnum - first_pseudo_regnum + 1,
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};
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