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[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2, ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support. (macro_build): Add case '2'. (macro): Expand M_BALIGN to nop, packrl.ph or balign. (validate_mips_insn): Add support for balign instruction. (mips_ip): Handle DSP R2 instructions. Support balign instruction. (OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE, md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2 command line options. (s_mipsset): Add support for .set dspr2 and .set nodspr2 directives. (md_show_usage): Add -mdspr2 and -mno-dspr2 help output. * doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2, .set dspr2, .set nodspr2. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for DSP R2. * gas/mips/mips.exp: Run new test. [ include/opcode/Changelog ] * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. (INSN_DSPR2): Add flag for DSP R2 instructions. (M_BALIGN): New macro. [ opcodes/ChangeLog ] * mips-dis.c (mips_arch_choices): Add DSP R2 support. (print_insn_args): Add support for balign instruction. * mips-opc.c (D33): New shortcut for DSP R2 instructions. (mips_builtin_opcodes): Add DSP R2 instructions. [ sim/mips/ChangeLog ] * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add dsp2 to sim_igen_machine. * configure: Regenerate. * dsp.igen (do_ph_op): Add MUL support when op = 2. (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. (mulq_rs.ph): Use do_ph_mulq. (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. * mips.igen: Add dsp2 model and include dsp2.igen. (MFHI, MFLO, MTHI, MTLO): Extend these instructions for for *mips32r2, *mips64r2, *dsp. (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions for *mips32r2, *mips64r2, *dsp2. * dsp2.igen: New file for MIPS DSP REV 2 ASE. [ sim/testsuite/sim/mips/ChangeLog ] * basic.exp: Run the dsp2 test. * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. * mips32-dsp2.s: New test.
This commit is contained in:
Thiemo Seufer
parent
cb5c8c3989
commit
8b082fb134
@ -1,3 +1,20 @@
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2007-02-20 Thiemo Seufer <ths@mips.com>
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Chao-Ying Fu <fu@mips.com>
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* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
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ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
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(macro_build): Add case '2'.
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(macro): Expand M_BALIGN to nop, packrl.ph or balign.
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(validate_mips_insn): Add support for balign instruction.
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(mips_ip): Handle DSP R2 instructions. Support balign instruction.
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(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
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md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
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command line options.
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(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
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(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
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* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
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.set dspr2, .set nodspr2.
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2007-02-20 Nathan Sidwell <nathan@codesourcery.com>
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* config/tc-m68k.c (mcf5210a_ctrl, mcf52235_ctrl, mcf5225_ctrl): New.
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@ -193,6 +193,7 @@ struct mips_set_options
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int ase_mdmx;
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int ase_smartmips;
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int ase_dsp;
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int ase_dspr2;
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int ase_mt;
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/* Whether we are assembling for the mips16 processor. 0 if we are
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not, 1 if we are, and -1 if the value has not been initialized.
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@ -244,7 +245,7 @@ static int file_mips_fp32 = -1;
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static struct mips_set_options mips_opts =
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{
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ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
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ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
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};
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/* These variables are filled in with the masks of registers used.
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@ -289,6 +290,13 @@ static int file_ase_dsp;
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#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
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/* True if -mdspr2 was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_dspr2;
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#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
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|| mips_opts.isa == ISA_MIPS64R2)
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/* True if -mmt was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_mt;
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@ -1052,6 +1060,7 @@ struct mips_cpu_info
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#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
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#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
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#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
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#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
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static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
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static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
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@ -3326,17 +3335,24 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
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assert (mo);
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assert (strcmp (name, mo->name) == 0);
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/* Search until we get a match for NAME. It is assumed here that
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macros will never generate MDMX, MIPS-3D, DSP or MT instructions. */
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while (strcmp (fmt, mo->args) != 0
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|| mo->pinfo == INSN_MACRO
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|| !OPCODE_IS_MEMBER (mo,
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while (1)
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{
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/* Search until we get a match for NAME. It is assumed here that
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macros will never generate MDMX, MIPS-3D, or MT instructions. */
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if (strcmp (fmt, mo->args) == 0
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&& mo->pinfo != INSN_MACRO
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&& OPCODE_IS_MEMBER (mo,
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(mips_opts.isa
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| (mips_opts.mips16 ? INSN_MIPS16 : 0)
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| (mips_opts.ase_dsp ? INSN_DSP : 0)
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| ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
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? INSN_DSP64 : 0)
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| (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
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| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
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mips_opts.arch)
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|| (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
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{
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&& (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
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break;
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++mo;
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assert (mo->name);
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assert (strcmp (name, mo->name) == 0);
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@ -3387,6 +3403,10 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
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}
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continue;
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case '2':
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INSERT_OPERAND (BP, insn, va_arg (args, int));
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continue;
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case 't':
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case 'w':
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case 'E':
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@ -4615,6 +4635,22 @@ macro (struct mips_cl_insn *ip)
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macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
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break;
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case M_BALIGN:
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switch (imm_expr.X_add_number)
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{
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case 0:
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macro_build (NULL, "nop", "");
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break;
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case 2:
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macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
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break;
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default:
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macro_build (NULL, "balign", "t,s,2", treg, sreg,
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(int)imm_expr.X_add_number);
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break;
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}
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break;
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case M_BEQ_I:
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s = "beq";
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goto beq_i;
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@ -8222,6 +8258,7 @@ validate_mips_insn (const struct mips_opcode *opc)
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case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
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case '[': break;
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case ']': break;
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case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
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case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
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case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
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case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
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@ -8399,6 +8436,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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| (mips_opts.ase_dsp ? INSN_DSP : 0)
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| ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
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? INSN_DSP64 : 0)
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| (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
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| (mips_opts.ase_mt ? INSN_MT : 0)
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| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
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| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
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@ -8454,6 +8492,20 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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return;
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break;
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case '2': /* dsp 2-bit unsigned immediate in bit 11 */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned long) imm_expr.X_add_number != 1
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&& (unsigned long) imm_expr.X_add_number != 3)
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{
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as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
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(unsigned long) imm_expr.X_add_number);
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}
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INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case '3': /* dsp 3-bit unsigned immediate in bit 21 */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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@ -10826,9 +10878,13 @@ struct option md_longopts[] =
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{"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
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#define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
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{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
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#define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
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{"mdspr2", no_argument, NULL, OPTION_DSPR2},
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#define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
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{"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
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/* Old-style architecture options. Don't add more of these. */
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#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
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#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
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#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
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{"m4650", no_argument, NULL, OPTION_M4650},
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#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
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@ -11079,9 +11135,21 @@ md_parse_option (int c, char *arg)
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case OPTION_DSP:
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mips_opts.ase_dsp = 1;
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mips_opts.ase_dspr2 = 0;
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break;
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case OPTION_NO_DSP:
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mips_opts.ase_dsp = 0;
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mips_opts.ase_dspr2 = 0;
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break;
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case OPTION_DSPR2:
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mips_opts.ase_dspr2 = 1;
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mips_opts.ase_dsp = 1;
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break;
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case OPTION_NO_DSPR2:
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mips_opts.ase_dspr2 = 0;
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mips_opts.ase_dsp = 0;
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break;
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@ -11497,10 +11565,19 @@ mips_after_parse_args (void)
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as_warn ("%s ISA does not support DSP ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_dspr2 == -1)
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{
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mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
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mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
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}
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if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
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as_warn ("%s ISA does not support DSP R2 ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_mt == -1)
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mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
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if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
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as_warn ("%s ISA does not support MT ASE",
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as_warn ("%s ISA does not support MT ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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file_mips_isa = mips_opts.isa;
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@ -11509,6 +11586,7 @@ mips_after_parse_args (void)
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file_ase_mdmx = mips_opts.ase_mdmx;
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file_ase_smartmips = mips_opts.ase_smartmips;
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file_ase_dsp = mips_opts.ase_dsp;
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file_ase_dspr2 = mips_opts.ase_dspr2;
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file_ase_mt = mips_opts.ase_mt;
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mips_opts.gp32 = file_mips_gp32;
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mips_opts.fp32 = file_mips_fp32;
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@ -12399,9 +12477,26 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
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as_warn ("%s ISA does not support DSP ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.ase_dsp = 1;
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mips_opts.ase_dspr2 = 0;
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}
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else if (strcmp (name, "nodsp") == 0)
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mips_opts.ase_dsp = 0;
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{
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mips_opts.ase_dsp = 0;
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mips_opts.ase_dspr2 = 0;
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}
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else if (strcmp (name, "dspr2") == 0)
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{
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if (!ISA_SUPPORTS_DSPR2_ASE)
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as_warn ("%s ISA does not support DSP R2 ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.ase_dspr2 = 1;
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mips_opts.ase_dsp = 1;
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}
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else if (strcmp (name, "nodspr2") == 0)
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{
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mips_opts.ase_dspr2 = 0;
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mips_opts.ase_dsp = 0;
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}
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else if (strcmp (name, "mt") == 0)
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{
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if (!ISA_SUPPORTS_MT_ASE)
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@ -14085,6 +14180,7 @@ mips_elf_final_processing (void)
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/* Set MIPS ELF flags for ASEs. */
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/* We may need to define a new flag for DSP ASE, and set this flag when
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file_ase_dsp is true. */
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/* Same for DSP R2. */
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/* We may need to define a new flag for MT ASE, and set this flag when
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file_ase_mt is true. */
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if (file_ase_mips16)
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@ -14825,6 +14921,9 @@ MIPS options:\n\
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-mdsp generate DSP instructions\n\
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-mno-dsp do not generate DSP instructions\n"));
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fprintf (stream, _("\
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-mdspr2 generate DSP R2 instructions\n\
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-mno-dspr2 do not generate DSP R2 instructions\n"));
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fprintf (stream, _("\
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-mmt generate MT instructions\n\
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-mno-mt do not generate MT instructions\n"));
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fprintf (stream, _("\
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@ -372,6 +372,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mips3d}] [@b{-no-mips3d}]
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[@b{-mdmx}] [@b{-no-mdmx}]
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[@b{-mdsp}] [@b{-mno-dsp}]
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[@b{-mdspr2}] [@b{-mno-dspr2}]
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[@b{-mmt}] [@b{-mno-mt}]
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[@b{-mdebug}] [@b{-no-mdebug}]
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[@b{-mpdr}] [@b{-mno-pdr}]
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@ -1036,10 +1037,17 @@ This tells the assembler to accept MDMX instructions.
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@item -mdsp
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@itemx -mno-dsp
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Generate code for the DSP Application Specific Extension.
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This tells the assembler to accept DSP instructions.
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Generate code for the DSP Release 1 Application Specific Extension.
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This tells the assembler to accept DSP Release 1 instructions.
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@samp{-mno-dsp} turns off this option.
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@item -mdspr2
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@itemx -mno-dspr2
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Generate code for the DSP Release 2 Application Specific Extension.
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This option implies -mdsp.
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This tells the assembler to accept DSP Release 2 instructions.
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@samp{-mno-dspr2} turns off this option.
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@item -mmt
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@itemx -mno-mt
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Generate code for the MT Application Specific Extension.
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@ -137,10 +137,17 @@ This tells the assembler to accept MDMX instructions.
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@item -mdsp
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@itemx -mno-dsp
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Generate code for the DSP Application Specific Extension.
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This tells the assembler to accept DSP instructions.
|
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Generate code for the DSP Release 1 Application Specific Extension.
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This tells the assembler to accept DSP Release 1 instructions.
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@samp{-mno-dsp} turns off this option.
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@item -mdspr2
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@itemx -mno-dspr2
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Generate code for the DSP Release 2 Application Specific Extension.
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This option implies -mdsp.
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This tells the assembler to accept DSP Release 2 instructions.
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@samp{-mno-dspr2} turns off this option.
|
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|
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@item -mmt
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@itemx -mno-mt
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Generate code for the MT Application Specific Extension.
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@ -520,13 +527,22 @@ from the MDMX Application Specific Extension from that point on
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in the assembly. The @code{.set nomdmx} directive prevents MDMX
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instructions from being accepted.
|
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@cindex MIPS DSP instruction generation override
|
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@cindex MIPS DSP Release 1 instruction generation override
|
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@kindex @code{.set dsp}
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@kindex @code{.set nodsp}
|
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The directive @code{.set dsp} makes the assembler accept instructions
|
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from the DSP Application Specific Extension from that point on
|
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in the assembly. The @code{.set nodsp} directive prevents DSP
|
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instructions from being accepted.
|
||||
from the DSP Release 1 Application Specific Extension from that point
|
||||
on in the assembly. The @code{.set nodsp} directive prevents DSP
|
||||
Release 1 instructions from being accepted.
|
||||
|
||||
@cindex MIPS DSP Release 2 instruction generation override
|
||||
@kindex @code{.set dspr2}
|
||||
@kindex @code{.set nodspr2}
|
||||
The directive @code{.set dspr2} makes the assembler accept instructions
|
||||
from the DSP Release 2 Application Specific Extension from that point
|
||||
on in the assembly. This dirctive implies @code{.set dsp}. The
|
||||
@code{.set nodspr2} directive prevents DSP Release 2 instructions from
|
||||
being accepted.
|
||||
|
||||
@cindex MIPS MT instruction generation override
|
||||
@kindex @code{.set mt}
|
||||
|
||||
@ -1,3 +1,10 @@
|
||||
2007-02-20 Thiemo Seufer <ths@mips.com>
|
||||
Chao-Ying Fu <fu@mips.com>
|
||||
|
||||
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
|
||||
DSP R2.
|
||||
* gas/mips/mips.exp: Run new test.
|
||||
|
||||
2007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
|
||||
|
||||
* gas/s390/esa-g5.d (cfxbr, cfebr, cfdbr): Exchanged floating
|
||||
|
||||
@ -772,6 +772,7 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
|
||||
run_dump_test_arches "smartmips" [mips_arch_list_matching mips32 !gpr64]
|
||||
run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "mips64-dsp" [mips_arch_list_matching mips64r2]
|
||||
run_dump_test_arches "mips32-mt" [mips_arch_list_matching mips32r2 !gpr64]
|
||||
|
||||
|
||||
72
gas/testsuite/gas/mips/mips32-dspr2.d
Normal file
72
gas/testsuite/gas/mips/mips32-dspr2.d
Normal file
@ -0,0 +1,72 @@
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: MIPS DSP ASE Rev2 for MIPS32
|
||||
#as: -mdspr2 -32
|
||||
|
||||
# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 7c010052 absq_s\.qb zero,at
|
||||
0+0004 <[^>]*> 7c430a10 addu\.ph at,v0,v1
|
||||
0+0008 <[^>]*> 7c641310 addu_s\.ph v0,v1,a0
|
||||
0+000c <[^>]*> 7c851818 adduh\.qb v1,a0,a1
|
||||
0+0010 <[^>]*> 7ca62098 adduh_r\.qb a0,a1,a2
|
||||
0+0014 <[^>]*> 7cc50031 append a1,a2,0x0
|
||||
0+0018 <[^>]*> 7cc5f831 append a1,a2,0x1f
|
||||
0+001c <[^>]*> 00000000 nop
|
||||
0+0020 <[^>]*> 7ce60c31 balign a2,a3,0x1
|
||||
0+0024 <[^>]*> 7cc73391 packrl.ph a2,a2,a3
|
||||
0+0028 <[^>]*> 7ce61c31 balign a2,a3,0x3
|
||||
0+002c <[^>]*> 7ce83611 cmpgdu\.eq\.qb a2,a3,t0
|
||||
0+0030 <[^>]*> 7d093e51 cmpgdu\.lt\.qb a3,t0,t1
|
||||
0+0034 <[^>]*> 7d2a4691 cmpgdu\.le\.qb t0,t1,t2
|
||||
0+0038 <[^>]*> 7d2a0030 dpa\.w\.ph \$ac0,t1,t2
|
||||
0+003c <[^>]*> 7d4b0870 dps\.w\.ph \$ac1,t2,t3
|
||||
0+0040 <[^>]*> 716c1000 madd \$ac2,t3,t4
|
||||
0+0044 <[^>]*> 718d1801 maddu \$ac3,t4,t5
|
||||
0+0048 <[^>]*> 71ae0004 msub t5,t6
|
||||
0+004c <[^>]*> 71cf0805 msubu \$ac1,t6,t7
|
||||
0+0050 <[^>]*> 7e117b18 mul\.ph t7,s0,s1
|
||||
0+0054 <[^>]*> 7e328398 mul_s\.ph s0,s1,s2
|
||||
0+0058 <[^>]*> 7e538dd8 mulq_rs\.w s1,s2,s3
|
||||
0+005c <[^>]*> 7e749790 mulq_s\.ph s2,s3,s4
|
||||
0+0060 <[^>]*> 7e959d98 mulq_s\.w s3,s4,s5
|
||||
0+0064 <[^>]*> 7e9510b0 mulsa\.w\.ph \$ac2,s4,s5
|
||||
0+0068 <[^>]*> 02b61818 mult \$ac3,s5,s6
|
||||
0+006c <[^>]*> 02d70019 multu s6,s7
|
||||
0+0070 <[^>]*> 7f19bb51 precr\.qb\.ph s7,t8,t9
|
||||
0+0074 <[^>]*> 7f380791 precr_sra\.ph\.w t8,t9,0x0
|
||||
0+0078 <[^>]*> 7f38ff91 precr_sra\.ph\.w t8,t9,0x1f
|
||||
0+007c <[^>]*> 7f5907d1 precr_sra_r\.ph\.w t9,k0,0x0
|
||||
0+0080 <[^>]*> 7f59ffd1 precr_sra_r\.ph\.w t9,k0,0x1f
|
||||
0+0084 <[^>]*> 7f7a0071 prepend k0,k1,0x0
|
||||
0+0088 <[^>]*> 7f7af871 prepend k0,k1,0x1f
|
||||
0+008c <[^>]*> 7c1cd913 shra\.qb k1,gp,0x0
|
||||
0+0090 <[^>]*> 7cfcd913 shra\.qb k1,gp,0x7
|
||||
0+0094 <[^>]*> 7c1de153 shra_r\.qb gp,sp,0x0
|
||||
0+0098 <[^>]*> 7cfde153 shra_r\.qb gp,sp,0x7
|
||||
0+009c <[^>]*> 7ffee993 shrav\.qb sp,s8,ra
|
||||
0+00a0 <[^>]*> 7c1ff1d3 shrav_r\.qb s8,ra,zero
|
||||
0+00a4 <[^>]*> 7c00fe53 shrl\.ph ra,zero,0x0
|
||||
0+00a8 <[^>]*> 7de0fe53 shrl\.ph ra,zero,0xf
|
||||
0+00ac <[^>]*> 7c4106d3 shrlv\.ph zero,at,v0
|
||||
0+00b0 <[^>]*> 7c430a50 subu\.ph at,v0,v1
|
||||
0+00b4 <[^>]*> 7c641350 subu_s\.ph v0,v1,a0
|
||||
0+00b8 <[^>]*> 7c851858 subuh\.qb v1,a0,a1
|
||||
0+00bc <[^>]*> 7ca620d8 subuh_r\.qb a0,a1,a2
|
||||
0+00c0 <[^>]*> 7cc72a18 addqh\.ph a1,a2,a3
|
||||
0+00c4 <[^>]*> 7ce83298 addqh_r\.ph a2,a3,t0
|
||||
0+00c8 <[^>]*> 7d093c18 addqh\.w a3,t0,t1
|
||||
0+00cc <[^>]*> 7d2a4498 addqh_r\.w t0,t1,t2
|
||||
0+00d0 <[^>]*> 7d4b4a58 subqh\.ph t1,t2,t3
|
||||
0+00d4 <[^>]*> 7d6c52d8 subqh_r\.ph t2,t3,t4
|
||||
0+00d8 <[^>]*> 7d8d5c58 subqh\.w t3,t4,t5
|
||||
0+00dc <[^>]*> 7dae64d8 subqh_r\.w t4,t5,t6
|
||||
0+00e0 <[^>]*> 7dae0a30 dpax\.w\.ph \$ac1,t5,t6
|
||||
0+00e4 <[^>]*> 7dcf1270 dpsx\.w\.ph \$ac2,t6,t7
|
||||
0+00e8 <[^>]*> 7df01e30 dpaqx_s\.w\.ph \$ac3,t7,s0
|
||||
0+00ec <[^>]*> 7e1106b0 dpaqx_sa\.w\.ph \$ac0,s0,s1
|
||||
0+00f0 <[^>]*> 7e320e70 dpsqx_s\.w\.ph \$ac1,s1,s2
|
||||
0+00f4 <[^>]*> 7e5316f0 dpsqx_sa\.w\.ph \$ac2,s2,s3
|
||||
\.\.\.
|
||||
73
gas/testsuite/gas/mips/mips32-dspr2.s
Normal file
73
gas/testsuite/gas/mips/mips32-dspr2.s
Normal file
@ -0,0 +1,73 @@
|
||||
# source file to test assembly of MIPS DSP ASE Rev2 for MIPS32 instructions
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.text
|
||||
text_label:
|
||||
|
||||
absq_s.qb $0,$1
|
||||
addu.ph $1,$2,$3
|
||||
addu_s.ph $2,$3,$4
|
||||
adduh.qb $3,$4,$5
|
||||
adduh_r.qb $4,$5,$6
|
||||
append $5,$6,0
|
||||
append $5,$6,31
|
||||
balign $6,$7,0
|
||||
balign $6,$7,1
|
||||
balign $6,$7,2
|
||||
balign $6,$7,3
|
||||
cmpgdu.eq.qb $6,$7,$8
|
||||
cmpgdu.lt.qb $7,$8,$9
|
||||
cmpgdu.le.qb $8,$9,$10
|
||||
dpa.w.ph $ac0,$9,$10
|
||||
dps.w.ph $ac1,$10,$11
|
||||
madd $ac2,$11,$12
|
||||
maddu $ac3,$12,$13
|
||||
msub $ac0,$13,$14
|
||||
msubu $ac1,$14,$15
|
||||
mul.ph $15,$16,$17
|
||||
mul_s.ph $16,$17,$18
|
||||
mulq_rs.w $17,$18,$19
|
||||
mulq_s.ph $18,$19,$20
|
||||
mulq_s.w $19,$20,$21
|
||||
mulsa.w.ph $ac2,$20,$21
|
||||
mult $ac3,$21,$22
|
||||
multu $ac0,$22,$23
|
||||
precr.qb.ph $23,$24,$25
|
||||
precr_sra.ph.w $24,$25,0
|
||||
precr_sra.ph.w $24,$25,31
|
||||
precr_sra_r.ph.w $25,$26,0
|
||||
precr_sra_r.ph.w $25,$26,31
|
||||
prepend $26,$27,0
|
||||
prepend $26,$27,31
|
||||
shra.qb $27,$28,0
|
||||
shra.qb $27,$28,7
|
||||
shra_r.qb $28,$29,0
|
||||
shra_r.qb $28,$29,7
|
||||
shrav.qb $29,$30,$31
|
||||
shrav_r.qb $30,$31,$0
|
||||
shrl.ph $31,$0,0
|
||||
shrl.ph $31,$0,15
|
||||
shrlv.ph $0,$1,$2
|
||||
subu.ph $1,$2,$3
|
||||
subu_s.ph $2,$3,$4
|
||||
subuh.qb $3,$4,$5
|
||||
subuh_r.qb $4,$5,$6
|
||||
addqh.ph $5,$6,$7
|
||||
addqh_r.ph $6,$7,$8
|
||||
addqh.w $7,$8,$9
|
||||
addqh_r.w $8,$9,$10
|
||||
subqh.ph $9,$10,$11
|
||||
subqh_r.ph $10,$11,$12
|
||||
subqh.w $11,$12,$13
|
||||
subqh_r.w $12,$13,$14
|
||||
dpax.w.ph $ac1,$13,$14
|
||||
dpsx.w.ph $ac2,$14,$15
|
||||
dpaqx_s.w.ph $ac3,$15,$16
|
||||
dpaqx_sa.w.ph $ac0,$16,$17
|
||||
dpsqx_s.w.ph $ac1,$17,$18
|
||||
dpsqx_sa.w.ph $ac2,$18,$19
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
@ -1,3 +1,10 @@
|
||||
2007-02-20 Thiemo Seufer <ths@mips.com>
|
||||
Chao-Ying Fu <fu@mips.com>
|
||||
|
||||
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
|
||||
(INSN_DSPR2): Add flag for DSP R2 instructions.
|
||||
(M_BALIGN): New macro.
|
||||
|
||||
2007-02-14 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
|
||||
|
||||
@ -169,6 +169,8 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
|
||||
#define OP_MASK_WRDSP 0x3f
|
||||
#define OP_SH_RDDSP 16
|
||||
#define OP_MASK_RDDSP 0x3f
|
||||
#define OP_SH_BP 11
|
||||
#define OP_MASK_BP 0x3
|
||||
|
||||
/* MIPS MT ASE */
|
||||
#define OP_SH_MT_U 5
|
||||
@ -340,6 +342,7 @@ struct mips_opcode
|
||||
"Z" MDMX source register (OP_*_FT)
|
||||
|
||||
DSP ASE usage:
|
||||
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
|
||||
"3" 3 bit unsigned immediate (OP_*_SA3)
|
||||
"4" 4 bit unsigned immediate (OP_*_SA4)
|
||||
"5" 8 bit unsigned immediate (OP_*_IMM8)
|
||||
@ -374,7 +377,7 @@ struct mips_opcode
|
||||
"+" Start of extension sequence.
|
||||
|
||||
Characters used so far, for quick reference when adding more:
|
||||
"34567890"
|
||||
"234567890"
|
||||
"%[]<>(),+:'@!$*&"
|
||||
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
|
||||
"abcdefghijklopqrstuvwxz"
|
||||
@ -485,7 +488,7 @@ struct mips_opcode
|
||||
#define INSN_ISA64R2 0x00000100
|
||||
|
||||
/* Masks used for MIPS-defined ASEs. */
|
||||
#define INSN_ASE_MASK 0x1c00f000
|
||||
#define INSN_ASE_MASK 0x3c00f000
|
||||
|
||||
/* DSP ASE */
|
||||
#define INSN_DSP 0x00001000
|
||||
@ -522,8 +525,10 @@ struct mips_opcode
|
||||
#define INSN_MDMX 0x04000000
|
||||
/* MT ASE */
|
||||
#define INSN_MT 0x08000000
|
||||
/* SmartMIPS ASE. */
|
||||
/* SmartMIPS ASE */
|
||||
#define INSN_SMARTMIPS 0x10000000
|
||||
/* DSP R2 ASE */
|
||||
#define INSN_DSPR2 0x20000000
|
||||
|
||||
/* MIPS ISA defines, use instead of hardcoding ISA level. */
|
||||
|
||||
@ -608,6 +613,7 @@ enum
|
||||
M_ADD_I,
|
||||
M_ADDU_I,
|
||||
M_AND_I,
|
||||
M_BALIGN,
|
||||
M_BEQ,
|
||||
M_BEQ_I,
|
||||
M_BEQL_I,
|
||||
|
||||
@ -1,3 +1,11 @@
|
||||
2007-02-20 Thiemo Seufer <ths@mips.com>
|
||||
Chao-Ying Fu <fu@mips.com>
|
||||
|
||||
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
|
||||
(print_insn_args): Add support for balign instruction.
|
||||
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
|
||||
(mips_builtin_opcodes): Add DSP R2 instructions.
|
||||
|
||||
2007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
|
||||
|
||||
* s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed.
|
||||
|
||||
@ -400,8 +400,8 @@ const struct mips_arch_choice mips_arch_choices[] =
|
||||
mips_hwr_names_numeric },
|
||||
|
||||
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
|
||||
(ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_MIPS3D
|
||||
| INSN_MT),
|
||||
(ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
|
||||
| INSN_MIPS3D | INSN_MT),
|
||||
mips_cp0_names_mips3264r2,
|
||||
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
|
||||
mips_hwr_names_mips3264r2 },
|
||||
@ -414,8 +414,8 @@ const struct mips_arch_choice mips_arch_choices[] =
|
||||
mips_hwr_names_numeric },
|
||||
|
||||
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
|
||||
(ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSP64
|
||||
| INSN_MT | INSN_MDMX),
|
||||
(ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
|
||||
| INSN_DSP64 | INSN_MT | INSN_MDMX),
|
||||
mips_cp0_names_mips3264r2,
|
||||
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
|
||||
mips_hwr_names_mips3264r2 },
|
||||
@ -855,6 +855,11 @@ print_insn_args (const char *d,
|
||||
}
|
||||
break;
|
||||
|
||||
case '2':
|
||||
(*info->fprintf_func) (info->stream, "0x%lx",
|
||||
(l >> OP_SH_BP) & OP_MASK_BP);
|
||||
break;
|
||||
|
||||
case '3':
|
||||
(*info->fprintf_func) (info->stream, "0x%lx",
|
||||
(l >> OP_SH_SA3) & OP_MASK_SA3);
|
||||
|
||||
@ -148,6 +148,7 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
|
||||
#define MOD_a WR_a|RD_a
|
||||
#define DSP_VOLA INSN_TRAP
|
||||
#define D32 INSN_DSP
|
||||
#define D33 INSN_DSPR2
|
||||
#define D64 INSN_DSP64
|
||||
|
||||
/* MIPS MT ASE support. */
|
||||
@ -764,11 +765,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
|
||||
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
|
||||
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
|
||||
{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
|
||||
{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
|
||||
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
|
||||
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
|
||||
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
|
||||
{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
|
||||
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
|
||||
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
|
||||
@ -857,8 +860,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
|
||||
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
|
||||
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
|
||||
{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
|
||||
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
|
||||
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
|
||||
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
|
||||
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
|
||||
@ -939,9 +944,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
|
||||
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
|
||||
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
|
||||
{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
|
||||
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
|
||||
{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
|
||||
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
|
||||
{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
|
||||
{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
|
||||
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
|
||||
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
|
||||
@ -1631,6 +1638,54 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
|
||||
{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
|
||||
{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
|
||||
/* MIPS DSP ASE Rev2 */
|
||||
{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 },
|
||||
{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
|
||||
{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
|
||||
{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 },
|
||||
{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
|
||||
{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
|
||||
{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
|
||||
{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
|
||||
{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
|
||||
{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
|
||||
{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
|
||||
{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
|
||||
{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 },
|
||||
{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 },
|
||||
{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 },
|
||||
{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
|
||||
{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
/* Move bc0* after mftr and mttr to avoid opcode collision. */
|
||||
{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
||||
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
||||
|
||||
@ -1,3 +1,21 @@
|
||||
2007-02-20 Thiemo Seufer <ths@mips.com>
|
||||
Chao-Ying Fu <fu@mips.com>
|
||||
|
||||
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
|
||||
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
|
||||
Add dsp2 to sim_igen_machine.
|
||||
* configure: Regenerate.
|
||||
* dsp.igen (do_ph_op): Add MUL support when op = 2.
|
||||
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
|
||||
(mulq_rs.ph): Use do_ph_mulq.
|
||||
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
|
||||
* mips.igen: Add dsp2 model and include dsp2.igen.
|
||||
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
|
||||
for *mips32r2, *mips64r2, *dsp.
|
||||
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
|
||||
for *mips32r2, *mips64r2, *dsp2.
|
||||
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
|
||||
|
||||
2007-02-19 Thiemo Seufer <ths@mips.com>
|
||||
Nigel Stephens <nigel@mips.com>
|
||||
|
||||
|
||||
@ -99,6 +99,7 @@ IGEN_INCLUDE=\
|
||||
$(srcdir)/tx.igen \
|
||||
$(srcdir)/vr.igen \
|
||||
$(srcdir)/dsp.igen \
|
||||
$(srcdir)/dsp2.igen \
|
||||
$(srcdir)/mips3264r2.igen \
|
||||
|
||||
# NB: Since these can be built by a number of generators, care
|
||||
|
||||
6
sim/mips/configure
vendored
6
sim/mips/configure
vendored
@ -5129,7 +5129,7 @@ case "${target}" in
|
||||
sim_multi_default=mips5000
|
||||
;;
|
||||
mips*-sde-elf*) sim_gen=M16
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,smartmips"
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
|
||||
sim_m16_machine="-M mips16,mips16e,mips64r2"
|
||||
sim_igen_filter="32,64,f"
|
||||
sim_mach_default="mipsisa64r2"
|
||||
@ -5142,7 +5142,7 @@ case "${target}" in
|
||||
sim_m16_filter="16"
|
||||
;;
|
||||
mipsisa32r2*-*-*) sim_gen=M16
|
||||
sim_igen_machine="-M mips32r2,mips16,mips16e,mdmx,dsp,smartmips"
|
||||
sim_igen_machine="-M mips32r2,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
|
||||
sim_m16_machine="-M mips16,mips16e,mips32r2"
|
||||
sim_igen_filter="32,f"
|
||||
sim_mach_default="mipsisa32r2"
|
||||
@ -5154,7 +5154,7 @@ case "${target}" in
|
||||
sim_mach_default="mipsisa32"
|
||||
;;
|
||||
mipsisa64r2*-*-*) sim_gen=M16
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp"
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2"
|
||||
sim_m16_machine="-M mips16,mips16e,mips64r2"
|
||||
sim_igen_filter="32,64,f"
|
||||
sim_mach_default="mipsisa64r2"
|
||||
|
||||
@ -140,7 +140,7 @@ case "${target}" in
|
||||
sim_multi_default=mips5000
|
||||
;;
|
||||
mips*-sde-elf*) sim_gen=M16
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,smartmips"
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
|
||||
sim_m16_machine="-M mips16,mips16e,mips64r2"
|
||||
sim_igen_filter="32,64,f"
|
||||
sim_mach_default="mipsisa64r2"
|
||||
@ -153,7 +153,7 @@ case "${target}" in
|
||||
sim_m16_filter="16"
|
||||
;;
|
||||
mipsisa32r2*-*-*) sim_gen=M16
|
||||
sim_igen_machine="-M mips32r2,mips16,mips16e,mdmx,dsp,smartmips"
|
||||
sim_igen_machine="-M mips32r2,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
|
||||
sim_m16_machine="-M mips16,mips16e,mips32r2"
|
||||
sim_igen_filter="32,f"
|
||||
sim_mach_default="mipsisa32r2"
|
||||
@ -165,7 +165,7 @@ case "${target}" in
|
||||
sim_mach_default="mipsisa32"
|
||||
;;
|
||||
mipsisa64r2*-*-*) sim_gen=M16
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp"
|
||||
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2"
|
||||
sim_m16_machine="-M mips16,mips16e,mips64r2"
|
||||
sim_igen_filter="32,64,f"
|
||||
sim_mach_default="mipsisa64r2"
|
||||
|
||||
@ -21,12 +21,12 @@
|
||||
// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
|
||||
// op: 0 = ADD, 1 = SUB
|
||||
// op: 0 = ADD, 1 = SUB, 2 = MUL
|
||||
// sat: 0 = no saturation, 1 = saturation
|
||||
:function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat
|
||||
{
|
||||
int i;
|
||||
signed32 h0;
|
||||
signed32 h0 = 0;
|
||||
signed16 h1, h2;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
@ -37,17 +37,22 @@
|
||||
h2 = (signed16)(v2 & 0xffff);
|
||||
if (op == 0) // ADD
|
||||
h0 = (signed32)h1 + (signed32)h2;
|
||||
else // SUB
|
||||
else if (op == 1) // SUB
|
||||
h0 = (signed32)h1 - (signed32)h2;
|
||||
if (((h0 & 0x10000) >> 1) != (h0 & 0x8000))
|
||||
else // MUL
|
||||
h0 = (signed32)h1 * (signed32)h2;
|
||||
if (h0 > (signed32)0x7fff || h0 < (signed32)0xffff8000)
|
||||
{
|
||||
DSPCR |= DSPCR_OUFLAG4;
|
||||
if (op == 0 || op == 1) // ADD, SUB
|
||||
DSPCR |= DSPCR_OUFLAG4;
|
||||
else if (op == 2) // MUL
|
||||
DSPCR |= DSPCR_OUFLAG5;
|
||||
if (sat == 1)
|
||||
{
|
||||
if (h0 & 0x10000)
|
||||
h0 = 0x8000;
|
||||
else
|
||||
if (h0 > (signed32)0x7fff)
|
||||
h0 = 0x7fff;
|
||||
else
|
||||
h0 = 0x8000;
|
||||
}
|
||||
}
|
||||
result |= ((unsigned32)((unsigned16)h0) << i);
|
||||
@ -775,14 +780,13 @@
|
||||
do_qb_muleu (SD_, RD, RS, RT, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,11111,010000:SPECIAL3:32::MULQ_RS.PH
|
||||
"mulq_rs.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp:
|
||||
// round: 0 = no rounding, 1 = rounding
|
||||
:function:::void:do_ph_mulq:int rd, int rs, int rt, int round
|
||||
{
|
||||
int i;
|
||||
unsigned32 result = 0;
|
||||
unsigned32 v1 = GPR[RS];
|
||||
unsigned32 v2 = GPR[RT];
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
signed16 h1, h2;
|
||||
signed32 prod;
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
|
||||
@ -795,11 +799,21 @@
|
||||
prod = 0x7fffffff;
|
||||
}
|
||||
else
|
||||
prod = (((signed32)h1 * (signed32)h2) << 1) + (signed32)0x8000;
|
||||
|
||||
{
|
||||
prod = ((signed32)h1 * (signed32)h2) << 1;
|
||||
if (round == 1)
|
||||
prod += (signed32)0x8000;
|
||||
}
|
||||
result |= (((unsigned32)prod >> 16) << i);
|
||||
}
|
||||
GPR[RD] = EXTEND32 (result);
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,11111,010000:SPECIAL3:32::MULQ_RS.PH
|
||||
"mulq_rs.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp:
|
||||
{
|
||||
do_ph_mulq (SD_, RD, RS, RT, 1);
|
||||
}
|
||||
|
||||
// loc: 0 = phl, 1 = phr
|
||||
@ -1651,64 +1665,6 @@
|
||||
DSPCR |= (pos & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;
|
||||
}
|
||||
|
||||
000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHIdsp
|
||||
"mfhi r<RD>":AC == 0
|
||||
"mfhi r<RD>, ac<AC>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
do_mfhi (SD_, RD);
|
||||
else
|
||||
GPR[RD] = DSPHI(AC);
|
||||
}
|
||||
|
||||
000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLOdsp
|
||||
"mflo r<RD>":AC == 0
|
||||
"mflo r<RD>, ac<AC>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
do_mflo (SD_, RD);
|
||||
else
|
||||
GPR[RD] = DSPLO(AC);
|
||||
}
|
||||
|
||||
000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHIdsp
|
||||
"mthi r<RS>":AC == 0
|
||||
"mthi r<RS>, ac<AC>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
check_mt_hilo (SD_, HIHISTORY);
|
||||
DSPHI(AC) = GPR[RS];
|
||||
}
|
||||
|
||||
000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLOdsp
|
||||
"mtlo r<RS>":AC == 0
|
||||
"mtlo r<RS>, ac<AC>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
check_mt_hilo (SD_, LOHISTORY);
|
||||
DSPLO(AC) = GPR[RS];
|
||||
}
|
||||
|
||||
011111,5.RS,10.MASK10,10011,111000:SPECIAL3:32::WRDSP
|
||||
"wrdsp r<RS>":MASK10 == 1111111111
|
||||
"wrdsp r<RS>, <MASK10>"
|
||||
|
||||
738
sim/mips/dsp2.igen
Normal file
738
sim/mips/dsp2.igen
Normal file
@ -0,0 +1,738 @@
|
||||
// -*- C -*-
|
||||
|
||||
// Simulator definition for the MIPS DSP REV 2 ASE.
|
||||
// Copyright (C) 2006 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
// Contributed by Chao-ying Fu (fu@mips.com).
|
||||
//
|
||||
// This file is part of GDB, the GNU debugger.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with GAS; see the file COPYING. If not, write to the Free
|
||||
// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
// 02110-1301, USA.
|
||||
|
||||
|
||||
// op: 0 = ADD, 1 = SUB
|
||||
// sat: 0 = no saturation, 1 = saturation
|
||||
:function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat
|
||||
{
|
||||
int i;
|
||||
unsigned32 h0;
|
||||
unsigned16 h1, h2;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
unsigned32 result = 0;
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
|
||||
{
|
||||
h1 = (unsigned16)(v1 & 0xffff);
|
||||
h2 = (unsigned16)(v2 & 0xffff);
|
||||
if (op == 0) // ADD
|
||||
h0 = (unsigned32)h1 + (unsigned32)h2;
|
||||
else // SUB
|
||||
h0 = (unsigned32)h1 - (unsigned32)h2;
|
||||
if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT
|
||||
{
|
||||
DSPCR |= DSPCR_OUFLAG4;
|
||||
if (sat == 1)
|
||||
h0 = 0xffff;
|
||||
}
|
||||
else if (op == 1 && h1 < h2) // SUB SAT
|
||||
{
|
||||
DSPCR |= DSPCR_OUFLAG4;
|
||||
if (sat == 1)
|
||||
h0 = 0x0;
|
||||
}
|
||||
result |= ((unsigned32)((unsigned16)h0) << i);
|
||||
}
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
// op: 0 = ADD, 1 = SUB
|
||||
// round: 0 = no rounding, 1 = rounding
|
||||
:function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round
|
||||
{
|
||||
int i;
|
||||
unsigned32 h0;
|
||||
unsigned8 h1, h2;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
unsigned32 result = 0;
|
||||
for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
|
||||
{
|
||||
h1 = (unsigned8)(v1 & 0xff);
|
||||
h2 = (unsigned8)(v2 & 0xff);
|
||||
if (op == 0) // ADD
|
||||
h0 = (unsigned32)h1 + (unsigned32)h2;
|
||||
else // SUB
|
||||
h0 = (unsigned32)h1 - (unsigned32)h2;
|
||||
if (round == 1)
|
||||
h0 = (h0 + 1) >> 1;
|
||||
else
|
||||
h0 = h0 >> 1;
|
||||
result |= ((unsigned32)((unsigned8)h0) << i);
|
||||
}
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
// op: 0 = EQ, 1 = LT, 2 = LE
|
||||
:function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op
|
||||
{
|
||||
int i, j;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
unsigned8 h1, h2;
|
||||
unsigned32 result = 0;
|
||||
unsigned32 mask;
|
||||
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
|
||||
{
|
||||
h1 = (unsigned8)(v1 & 0xff);
|
||||
h2 = (unsigned8)(v2 & 0xff);
|
||||
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
|
||||
DSPCR &= mask;
|
||||
if (op == 0) // EQ
|
||||
{
|
||||
result |= ((h1 == h2) << j);
|
||||
DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
|
||||
}
|
||||
else if (op == 1) // LT
|
||||
{
|
||||
result |= ((h1 < h2) << j);
|
||||
DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
|
||||
}
|
||||
else // LE
|
||||
{
|
||||
result |= ((h1 <= h2) << j);
|
||||
DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
|
||||
}
|
||||
}
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
// op: 0 = DPA 1 = DPS
|
||||
:function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op
|
||||
{
|
||||
int i;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
signed16 h1, h2;
|
||||
signed32 result;
|
||||
unsigned32 lo = DSPLO(ac);
|
||||
unsigned32 hi = DSPHI(ac);
|
||||
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
|
||||
{
|
||||
h1 = (signed16)(v1 & 0xffff);
|
||||
h2 = (signed16)(v2 & 0xffff);
|
||||
result = (signed32)h1 * (signed32)h2;
|
||||
if (op == 0) // DPA
|
||||
prod += (signed64)result;
|
||||
else // DPS
|
||||
prod -= (signed64)result;
|
||||
}
|
||||
DSPLO(ac) = EXTEND32 (prod);
|
||||
DSPHI(ac) = EXTEND32 (prod >> 32);
|
||||
}
|
||||
|
||||
// round: 0 = no rounding, 1 = rounding
|
||||
:function:::void:do_w_mulq:int rd, int rs, int rt, int round
|
||||
{
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
signed32 w1, w2;
|
||||
signed64 prod;
|
||||
unsigned32 result;
|
||||
w1 = (signed32) v1;
|
||||
w2 = (signed32 )v2;
|
||||
if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000)
|
||||
{
|
||||
DSPCR |= DSPCR_OUFLAG5;
|
||||
prod = 0x7fffffff;
|
||||
}
|
||||
else
|
||||
{
|
||||
prod = ((signed64) w1 * (signed64) w2) << 1;
|
||||
if (round == 1)
|
||||
prod += 0x0000000080000000LL;
|
||||
prod = prod >> 32;
|
||||
}
|
||||
result = (unsigned32) prod;
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
// round: 0 = no rounding, 1 = rounding
|
||||
:function:::void:do_precr_sra:int rt, int rs, int sa, int round
|
||||
{
|
||||
unsigned32 v1 = GPR[rt];
|
||||
unsigned32 v2 = GPR[rs];
|
||||
signed32 w1 = (signed32) v1;
|
||||
signed32 w2 = (signed32) v2;
|
||||
signed32 result;
|
||||
if (sa != 0)
|
||||
{
|
||||
if (round == 1 && (w1 & (1 << (sa - 1))))
|
||||
w1 = (w1 >> sa) + 1;
|
||||
else
|
||||
w1 = w1 >> sa;
|
||||
|
||||
if (round == 1 && (w2 & (1 << (sa - 1))))
|
||||
w2 = (w2 >> sa) + 1;
|
||||
else
|
||||
w2 = w2 >> sa;
|
||||
}
|
||||
result = (w1 << 16) | (w2 & 0xffff);
|
||||
GPR[rt] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
// round: 0 = no rounding, 1 = rounding
|
||||
:function:::void:do_qb_shra:int rd, int rt, int shift, int round
|
||||
{
|
||||
int i, j;
|
||||
signed8 q0;
|
||||
unsigned32 v1 = GPR[rt];
|
||||
unsigned32 result = 0;
|
||||
for (i = 0; i < 32; i += 8, v1 >>= 8)
|
||||
{
|
||||
q0 = (signed8)(v1 & 0xff);
|
||||
if (shift != 0)
|
||||
{
|
||||
if (round == 1 && (q0 & (1 << (shift - 1))))
|
||||
q0 = (q0 >> shift) + 1;
|
||||
else
|
||||
q0 = q0 >> shift;
|
||||
}
|
||||
result |= ((unsigned32)((unsigned8)q0) << i);
|
||||
}
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
:function:::void:do_ph_shrl:int rd, int rt, int shift
|
||||
{
|
||||
int i, j;
|
||||
unsigned16 h0;
|
||||
unsigned32 v1 = GPR[rt];
|
||||
unsigned32 result = 0;
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16)
|
||||
{
|
||||
h0 = (unsigned16)(v1 & 0xffff);
|
||||
h0 = h0 >> shift;
|
||||
result |= ((unsigned32)h0 << i);
|
||||
}
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
// op: 0 = ADD, 1 = SUB
|
||||
// round: 0 = no rounding, 1 = rounding
|
||||
:function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round
|
||||
{
|
||||
int i;
|
||||
signed32 h0;
|
||||
signed16 h1, h2;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
unsigned32 result = 0;
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
|
||||
{
|
||||
h1 = (signed16)(v1 & 0xffff);
|
||||
h2 = (signed16)(v2 & 0xffff);
|
||||
if (op == 0) // ADD
|
||||
h0 = (signed32)h1 + (signed32)h2;
|
||||
else // SUB
|
||||
h0 = (signed32)h1 - (signed32)h2;
|
||||
if (round == 1)
|
||||
h0 = (h0 + 1) >> 1;
|
||||
else
|
||||
h0 = h0 >> 1;
|
||||
result |= ((unsigned32)((unsigned16)h0) << i);
|
||||
}
|
||||
GPR[rd] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
// op: 0 = ADD, 1 = SUB
|
||||
// round: 0 = no rounding, 1 = rounding
|
||||
:function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round
|
||||
{
|
||||
int i;
|
||||
signed64 v0;
|
||||
signed32 v1 = (signed32)GPR[rs];
|
||||
signed32 v2 = (signed32)GPR[rt];
|
||||
if (op == 0) // ADD
|
||||
v0 = (signed64)v1 + (signed64)v2;
|
||||
else // SUB
|
||||
v0 = (signed64)v1 - (signed64)v2;
|
||||
if (round == 1)
|
||||
v0 = (v0 + 1) >> 1;
|
||||
else
|
||||
v0 = v0 >> 1;
|
||||
GPR[rd] = EXTEND32 (v0);
|
||||
}
|
||||
|
||||
// op: 0 = DPAX, 1 = DPSX
|
||||
:function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op
|
||||
{
|
||||
int i;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
signed16 h1, h2;
|
||||
signed32 result;
|
||||
unsigned32 lo = DSPLO(ac);
|
||||
unsigned32 hi = DSPHI(ac);
|
||||
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
|
||||
{
|
||||
h1 = (signed16)(v1 & 0xffff);
|
||||
h2 = (signed16)((v2 & 0xffff0000) >> 16);
|
||||
result = (signed32)h1 * (signed32)h2;
|
||||
if (op == 0) // DPAX
|
||||
prod += (signed64)result;
|
||||
else // DPSX
|
||||
prod -= (signed64)result;
|
||||
}
|
||||
DSPLO(ac) = EXTEND32 (prod);
|
||||
DSPHI(ac) = EXTEND32 (prod >> 32);
|
||||
}
|
||||
|
||||
// op: 0 = DPAQX, 1 = DPSQX
|
||||
// sat: 0 = no saturation, 1 = saturation of the accumulator
|
||||
:function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat
|
||||
{
|
||||
int i;
|
||||
unsigned32 v1 = GPR[rs];
|
||||
unsigned32 v2 = GPR[rt];
|
||||
signed16 h1, h2;
|
||||
signed32 result;
|
||||
unsigned32 lo = DSPLO(ac);
|
||||
unsigned32 hi = DSPHI(ac);
|
||||
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
|
||||
signed64 max, min;
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
|
||||
{
|
||||
h1 = (signed16)(v1 & 0xffff);
|
||||
h2 = (signed16)((v2 & 0xffff0000) >> 16);
|
||||
if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
|
||||
{
|
||||
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
|
||||
result = 0x7fffffff;
|
||||
}
|
||||
else
|
||||
result = ((signed32)h1 * (signed32)h2) << 1;
|
||||
if (op == 0) // DPAQX
|
||||
prod += (signed64)result;
|
||||
else // DPSQX
|
||||
prod -= (signed64)result;
|
||||
}
|
||||
// Saturation on the accumulator.
|
||||
if (sat == 1)
|
||||
{
|
||||
max = (signed64) 0x7fffffffLL;
|
||||
min = (signed64) 0xffffffff80000000LL;
|
||||
if (prod > max)
|
||||
{
|
||||
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
|
||||
prod = max;
|
||||
}
|
||||
else if (prod < min)
|
||||
{
|
||||
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
|
||||
prod = min;
|
||||
}
|
||||
}
|
||||
DSPLO(ac) = EXTEND32 (prod);
|
||||
DSPHI(ac) = EXTEND32 (prod >> 32);
|
||||
}
|
||||
|
||||
011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB
|
||||
"absq_s.qb r<RD>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
int i;
|
||||
signed8 q0;
|
||||
unsigned32 v1 = GPR[RT];
|
||||
unsigned32 result = 0;
|
||||
for (i = 0; i < 32; i += 8, v1 >>= 8)
|
||||
{
|
||||
q0 = (signed8)(v1 & 0xff);
|
||||
if (q0 == (signed8)0x80)
|
||||
{
|
||||
DSPCR |= DSPCR_OUFLAG4;
|
||||
q0 = 0x7f;
|
||||
}
|
||||
else if (q0 & 0x80)
|
||||
q0 = -q0;
|
||||
result |= ((unsigned32)((unsigned8)q0) << i);
|
||||
}
|
||||
GPR[RD] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH
|
||||
"addu.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_u_ph_op (SD_, RD, RS, RT, 0, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH
|
||||
"addu_s.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_u_ph_op (SD_, RD, RS, RT, 0, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB
|
||||
"adduh.qb r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_uh_qb_op (SD_, RD, RS, RT, 0, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB
|
||||
"adduh_r.qb r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_uh_qb_op (SD_, RD, RS, RT, 0, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND
|
||||
"append r<RT>, r<RS>, <SA>"
|
||||
*dsp2:
|
||||
{
|
||||
unsigned32 v0 = GPR[RS];
|
||||
unsigned32 v1 = GPR[RT];
|
||||
unsigned32 result;
|
||||
unsigned32 mask = (1 << SA) - 1;
|
||||
result = (v1 << SA) | (v0 & mask);
|
||||
GPR[RT] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN
|
||||
"balign r<RT>, r<RS>, <BP>"
|
||||
*dsp2:
|
||||
{
|
||||
unsigned32 v0 = GPR[RS];
|
||||
unsigned32 v1 = GPR[RT];
|
||||
unsigned32 result;
|
||||
if (BP == 0)
|
||||
result = v1;
|
||||
else
|
||||
result = (v1 << 8 * BP) | (v0 >> 8 * (4 - BP));
|
||||
GPR[RT] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB
|
||||
"cmpgdu.eq.qb r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qb_cmpgdu (SD_, RD, RS, RT, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB
|
||||
"cmpgdu.lt.qb r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qb_cmpgdu (SD_, RD, RS, RT, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB
|
||||
"cmpgdu.le.qb r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qb_cmpgdu (SD_, RD, RS, RT, 2);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH
|
||||
"dpa.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_w_ph_dot_product (SD_, AC, RS, RT, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH
|
||||
"dps.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_w_ph_dot_product (SD_, AC, RS, RT, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH
|
||||
"mul.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_ph_op (SD_, RD, RS, RT, 2, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH
|
||||
"mul_s.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_ph_op (SD_, RD, RS, RT, 2, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W
|
||||
"mulq_rs.w r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_w_mulq (SD_, RD, RS, RT, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH
|
||||
"mulq_s.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_ph_mulq (SD_, RD, RS, RT, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W
|
||||
"mulq_s.w r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_w_mulq (SD_, RD, RS, RT, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH
|
||||
"mulsa.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
int i;
|
||||
unsigned32 v1 = GPR[RS];
|
||||
unsigned32 v2 = GPR[RT];
|
||||
signed16 h1, h2;
|
||||
signed32 result;
|
||||
unsigned32 lo = DSPLO(AC);
|
||||
unsigned32 hi = DSPHI(AC);
|
||||
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
|
||||
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
|
||||
{
|
||||
h1 = (signed16)(v1 & 0xffff);
|
||||
h2 = (signed16)(v2 & 0xffff);
|
||||
result = (signed32)h1 * (signed32)h2;
|
||||
|
||||
if (i == 0)
|
||||
prod -= (signed64) result;
|
||||
else
|
||||
prod += (signed64) result;
|
||||
}
|
||||
DSPLO(AC) = EXTEND32 (prod);
|
||||
DSPHI(AC) = EXTEND32 (prod >> 32);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH
|
||||
"precr.qb.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
unsigned32 v1 = GPR[RS];
|
||||
unsigned32 v2 = GPR[RT];
|
||||
unsigned32 tempu = (v1 & 0xff0000) >> 16;
|
||||
unsigned32 tempv = (v1 & 0xff);
|
||||
unsigned32 tempw = (v2 & 0xff0000) >> 16;
|
||||
unsigned32 tempx = (v2 & 0xff);
|
||||
GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W
|
||||
"precr_sra.ph.w r<RT>, r<RS>, <SA>"
|
||||
*dsp2:
|
||||
{
|
||||
do_precr_sra (SD_, RT, RS, SA, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W
|
||||
"precr_sra_r.ph.w r<RT>, r<RS>, <SA>"
|
||||
*dsp2:
|
||||
{
|
||||
do_precr_sra (SD_, RT, RS, SA, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND
|
||||
"prepend r<RT>, r<RS>, <SA>"
|
||||
*dsp2:
|
||||
{
|
||||
unsigned32 v0 = GPR[RS];
|
||||
unsigned32 v1 = GPR[RT];
|
||||
unsigned32 result;
|
||||
if (SA == 0)
|
||||
result = v1;
|
||||
else
|
||||
result = (v0 << (32 - SA)) | (v1 >> SA);
|
||||
GPR[RT] = EXTEND32 (result);
|
||||
}
|
||||
|
||||
011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB
|
||||
"shra.qb r<RD>, r<RT>, <SHIFT3>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qb_shra (SD_, RD, RT, SHIFT3, 0);
|
||||
}
|
||||
|
||||
011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB
|
||||
"shra_r.qb r<RD>, r<RT>, <SHIFT3>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qb_shra (SD_, RD, RT, SHIFT3, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB
|
||||
"shrav.qb r<RD>, r<RT>, r<RS>"
|
||||
*dsp2:
|
||||
{
|
||||
unsigned32 shift = GPR[RS] & 0x7;
|
||||
do_qb_shra (SD_, RD, RT, shift, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB
|
||||
"shrav_r.qb r<RD>, r<RT>, r<RS>"
|
||||
*dsp2:
|
||||
{
|
||||
unsigned32 shift = GPR[RS] & 0x7;
|
||||
do_qb_shra (SD_, RD, RT, shift, 1);
|
||||
}
|
||||
|
||||
011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH
|
||||
"shrl.ph r<RD>, r<RT>, <SHIFT4>"
|
||||
*dsp2:
|
||||
{
|
||||
do_ph_shrl (SD_, RD, RT, SHIFT4);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH
|
||||
"shrlv.ph r<RD>, r<RT>, r<RS>"
|
||||
*dsp2:
|
||||
{
|
||||
unsigned32 shift = GPR[RS] & 0xf;
|
||||
do_ph_shrl (SD_, RD, RT, shift);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH
|
||||
"subu.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_u_ph_op (SD_, RD, RS, RT, 1, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH
|
||||
"subu_s.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_u_ph_op (SD_, RD, RS, RT, 1, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB
|
||||
"subuh.qb r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_uh_qb_op (SD_, RD, RS, RT, 1, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB
|
||||
"subuh_r.qb r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_uh_qb_op (SD_, RD, RS, RT, 1, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH
|
||||
"addqh.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_ph_op (SD_, RD, RS, RT, 0, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH
|
||||
"addqh_r.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_ph_op (SD_, RD, RS, RT, 0, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W
|
||||
"addqh.w r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_w_op (SD_, RD, RS, RT, 0, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W
|
||||
"addqh_r.w r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_w_op (SD_, RD, RS, RT, 0, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH
|
||||
"subqh.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_ph_op (SD_, RD, RS, RT, 1, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH
|
||||
"subqh_r.ph r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_ph_op (SD_, RD, RS, RT, 1, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W
|
||||
"subqh.w r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_w_op (SD_, RD, RS, RT, 1, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W
|
||||
"subqh_r.w r<RD>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qh_w_op (SD_, RD, RS, RT, 1, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH
|
||||
"dpax.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_x_w_ph_dot_product (SD_, AC, RS, RT, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH
|
||||
"dpsx.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_x_w_ph_dot_product (SD_, AC, RS, RT, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH
|
||||
"dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH
|
||||
"dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH
|
||||
"dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0);
|
||||
}
|
||||
|
||||
011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH
|
||||
"dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
|
||||
*dsp2:
|
||||
{
|
||||
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1);
|
||||
}
|
||||
@ -72,6 +72,7 @@
|
||||
:model:::mips3d:mips3d: // mips3d.igen
|
||||
:model:::mdmx:mdmx: // mdmx.igen
|
||||
:model:::dsp:dsp: // dsp.igen
|
||||
:model:::dsp2:dsp2: // dsp2.igen
|
||||
:model:::smartmips:smartmips: // smartmips.igen
|
||||
|
||||
// Vendor Extensions
|
||||
@ -2430,9 +2431,7 @@
|
||||
011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
|
||||
"madd r<RS>, r<RT>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*vr5500:
|
||||
{
|
||||
signed64 temp;
|
||||
@ -2448,13 +2447,32 @@
|
||||
}
|
||||
|
||||
|
||||
011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
|
||||
"madd r<RS>, r<RT>":AC == 0
|
||||
"madd ac<AC>, r<RS>, r<RT>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp2:
|
||||
{
|
||||
signed64 temp;
|
||||
if (AC == 0)
|
||||
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
||||
Unpredictable ();
|
||||
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
||||
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
||||
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
||||
DSPLO(AC) = EXTEND32 (temp);
|
||||
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
||||
if (AC == 0)
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
|
||||
|
||||
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
|
||||
"maddu r<RS>, r<RT>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*vr5500:
|
||||
{
|
||||
unsigned64 temp;
|
||||
@ -2471,6 +2489,30 @@
|
||||
}
|
||||
|
||||
|
||||
011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
|
||||
"maddu r<RS>, r<RT>":AC == 0
|
||||
"maddu ac<AC>, r<RS>, r<RT>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp2:
|
||||
{
|
||||
unsigned64 temp;
|
||||
if (AC == 0)
|
||||
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
||||
Unpredictable ();
|
||||
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
||||
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
||||
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
||||
if (AC == 0)
|
||||
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
|
||||
DSPLO(AC) = EXTEND32 (temp);
|
||||
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
||||
if (AC == 0)
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
|
||||
|
||||
:function:::void:do_mfhi:int rd
|
||||
{
|
||||
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
@ -2494,6 +2536,19 @@
|
||||
}
|
||||
|
||||
|
||||
000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
|
||||
"mfhi r<RD>":AC == 0
|
||||
"mfhi r<RD>, ac<AC>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
do_mfhi (SD_, RD);
|
||||
else
|
||||
GPR[RD] = DSPHI(AC);
|
||||
}
|
||||
|
||||
|
||||
:function:::void:do_mflo:int rd
|
||||
{
|
||||
@ -2518,6 +2573,19 @@
|
||||
}
|
||||
|
||||
|
||||
000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
|
||||
"mflo r<RD>":AC == 0
|
||||
"mflo r<RD>, ac<AC>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
do_mflo (SD_, RD);
|
||||
else
|
||||
GPR[RD] = DSPLO(AC);
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
|
||||
"movn r<RD>, r<RS>, r<RT>"
|
||||
@ -2560,9 +2628,7 @@
|
||||
011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
|
||||
"msub r<RS>, r<RT>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*vr5500:
|
||||
{
|
||||
signed64 temp;
|
||||
@ -2578,13 +2644,32 @@
|
||||
}
|
||||
|
||||
|
||||
011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
|
||||
"msub r<RS>, r<RT>":AC == 0
|
||||
"msub ac<AC>, r<RS>, r<RT>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp2:
|
||||
{
|
||||
signed64 temp;
|
||||
if (AC == 0)
|
||||
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
||||
Unpredictable ();
|
||||
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
||||
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
||||
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
||||
DSPLO(AC) = EXTEND32 (temp);
|
||||
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
||||
if (AC == 0)
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
|
||||
|
||||
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
|
||||
"msubu r<RS>, r<RT>"
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*vr5500:
|
||||
{
|
||||
unsigned64 temp;
|
||||
@ -2600,6 +2685,27 @@
|
||||
}
|
||||
|
||||
|
||||
011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
|
||||
"msubu r<RS>, r<RT>":AC == 0
|
||||
"msubu ac<AC>, r<RS>, r<RT>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp2:
|
||||
{
|
||||
unsigned64 temp;
|
||||
if (AC == 0)
|
||||
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
||||
Unpredictable ();
|
||||
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
||||
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
||||
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
||||
DSPLO(AC) = EXTEND32 (temp);
|
||||
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
||||
if (AC == 0)
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
|
||||
"mthi r<RS>"
|
||||
@ -2617,6 +2723,18 @@
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
|
||||
"mthi r<RS>":AC == 0
|
||||
"mthi r<RS>, ac<AC>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
check_mt_hilo (SD_, HIHISTORY);
|
||||
DSPHI(AC) = GPR[RS];
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
|
||||
"mtlo r<RS>"
|
||||
@ -2634,6 +2752,18 @@
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
|
||||
"mtlo r<RS>":AC == 0
|
||||
"mtlo r<RS>, ac<AC>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp:
|
||||
{
|
||||
if (AC == 0)
|
||||
check_mt_hilo (SD_, LOHISTORY);
|
||||
DSPLO(AC) = GPR[RS];
|
||||
}
|
||||
|
||||
|
||||
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
|
||||
"mul r<RD>, r<RS>, r<RT>"
|
||||
@ -2680,15 +2810,38 @@
|
||||
*mipsIV:
|
||||
*mipsV:
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*vr4100:
|
||||
{
|
||||
do_mult (SD_, RS, RT, 0);
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
|
||||
"mult r<RS>, r<RT>":AC == 0
|
||||
"mult ac<AC>, r<RS>, r<RT>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp2:
|
||||
{
|
||||
signed64 prod;
|
||||
if (AC == 0)
|
||||
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
||||
Unpredictable ();
|
||||
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
||||
prod = ((signed64)(signed32) GPR[RS])
|
||||
* ((signed64)(signed32) GPR[RT]);
|
||||
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
||||
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
||||
if (AC == 0)
|
||||
{
|
||||
ACX = 0; /* SmartMIPS */
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
|
||||
"mult r<RS>, r<RT>":RD == 0
|
||||
"mult r<RD>, r<RS>, r<RT>"
|
||||
@ -2723,14 +2876,35 @@
|
||||
*mipsIV:
|
||||
*mipsV:
|
||||
*mips32:
|
||||
*mips32r2:
|
||||
*mips64:
|
||||
*mips64r2:
|
||||
*vr4100:
|
||||
{
|
||||
do_multu (SD_, RS, RT, 0);
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
|
||||
"multu r<RS>, r<RT>":AC == 0
|
||||
"multu r<RS>, r<RT>"
|
||||
*mips32r2:
|
||||
*mips64r2:
|
||||
*dsp2:
|
||||
{
|
||||
unsigned64 prod;
|
||||
if (AC == 0)
|
||||
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
||||
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
||||
Unpredictable ();
|
||||
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
||||
prod = ((unsigned64)(unsigned32) GPR[RS])
|
||||
* ((unsigned64)(unsigned32) GPR[RT]);
|
||||
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
||||
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
||||
if (AC == 0)
|
||||
TRACE_ALU_RESULT2 (HI, LO);
|
||||
}
|
||||
|
||||
|
||||
000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
|
||||
"multu r<RS>, r<RT>":RD == 0
|
||||
"multu r<RD>, r<RS>, r<RT>"
|
||||
@ -5694,5 +5868,6 @@
|
||||
:include:::tx.igen
|
||||
:include:::vr.igen
|
||||
:include:::dsp.igen
|
||||
:include:::dsp2.igen
|
||||
:include:::smartmips.igen
|
||||
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2007-02-20 Thiemo Seufer <ths@mips.com>
|
||||
Chao-Ying Fu <fu@mips.com>
|
||||
* basic.exp: Run the dsp2 test.
|
||||
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
|
||||
* mips32-dsp2.s: New test.
|
||||
|
||||
2007-02-17 Thiemo Seufer <ths@mips.com>
|
||||
|
||||
* basic.exp: Add case for mips*-sde-elf*.
|
||||
|
||||
@ -86,4 +86,5 @@ if {[istarget mips*-*-elf] && [board_info target exists is_simulator]} {
|
||||
run_sim_test mdmx-ob-sb1.s $mdmxmodels
|
||||
|
||||
run_sim_test mips32-dsp.s $dspmodels
|
||||
run_sim_test mips32-dsp2.s $dspmodels
|
||||
}
|
||||
|
||||
12361
sim/testsuite/sim/mips/mips32-dsp2.s
Normal file
12361
sim/testsuite/sim/mips/mips32-dsp2.s
Normal file
File diff suppressed because it is too large
Load Diff
@ -187,6 +187,34 @@
|
||||
dsp_assert $4, $5
|
||||
.endm
|
||||
|
||||
# Set dsp control register <= crin
|
||||
# Set acc <= {hiin, loin}
|
||||
# (inst acc, s, t)
|
||||
# Check if {hiou, loou} == acc
|
||||
# Check if (crout & 0x80000) == (dsp control register & 0x80000)
|
||||
.macro dspckacc_astio inst, acc, hiin, loin, hiou, loou, s, t, crin, crout
|
||||
li $4, \crin
|
||||
wrdsp $4
|
||||
li $4, \hiin
|
||||
mthi $4, \acc
|
||||
li $4, \loin
|
||||
mtlo $4, \acc
|
||||
li $4, \s
|
||||
li $5, \t
|
||||
\inst \acc, $4, $5
|
||||
li $4, \hiou
|
||||
mfhi $5, \acc
|
||||
dsp_assert $4, $5
|
||||
li $4, \loou
|
||||
mflo $5, \acc
|
||||
dsp_assert $4, $5
|
||||
li $4, \crout
|
||||
and $4, $4, 0x80000
|
||||
rddsp $5
|
||||
and $5, $5, 0x80000
|
||||
dsp_assert $4, $5
|
||||
.endm
|
||||
|
||||
# Set dsp control register <= crin
|
||||
# Set $ac1 <= {hi, lo}
|
||||
# Check if t == (inst ? $ac1, s)
|
||||
@ -405,3 +433,12 @@
|
||||
li $6, \r
|
||||
dsp_assert $5, $6
|
||||
.endm
|
||||
|
||||
# Check if tou == (inst tin, s)
|
||||
.macro dspck_tsimm inst, tou, tin, s, sa
|
||||
li $4, \s
|
||||
li $5, \tin
|
||||
\inst $5, $4, \sa
|
||||
li $6, \tou
|
||||
dsp_assert $5, $6
|
||||
.endm
|
||||
|
||||
Loading…
Reference in New Issue
Block a user