mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-23 18:14:13 +08:00
cpu/
* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
(rstb, rsth, rst, rstd, rstq): Delete.
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
gas/testsuite/
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
* gas/frv/allinsn.d: Update accordingly.
opcodes/
* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
sim/frv/
* decode.c, decode.h, model.c, sem.c: Regenerate.
sim/testsuite/
* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
This commit is contained in:
Richard Sandiford
parent
3ce2bf1815
commit
8ae0baa268
@ -1,3 +1,9 @@
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
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(rstb, rsth, rst, rstd, rstq): Delete.
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(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
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2004-02-23 Nick Clifton <nickc@redhat.com>
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* Apply these patches from Renesas:
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69
cpu/frv.cpu
69
cpu/frv.cpu
@ -4469,36 +4469,6 @@
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(store-r-r stc SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word")
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(define-pmacro (r-store name mode op ope reg size is_float profile comment)
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(dni name
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(comment)
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((UNIT STORE) (FR500-MAJOR I-3) (MACH frv))
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(.str name "$pack $" reg "k,@($GRi,$GRj)")
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(+ pack (.sym reg k) op GRi ope GRj)
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(sequence ((WI address))
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(set address (add GRi GRj))
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(c-call VOID (.str "@cpu@_write_mem_" mode)
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pc address (.sym reg k))
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(c-call VOID "@cpu@_check_recovering_store"
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address (index-of (.sym reg k)) size is_float))
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profile
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)
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)
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(r-store rstb QI OP_03 OPE1_20 GR 1 0
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((fr500 (unit u-gr-r-store))) "Store unsigned byte")
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(r-store rsth HI OP_03 OPE1_21 GR 2 0
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((fr500 (unit u-gr-r-store))) "Store unsigned half")
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(r-store rst SI OP_03 OPE1_22 GR 4 0
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((fr500 (unit u-gr-r-store))) "Store word")
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(r-store rstbf QI OP_03 OPE1_28 FRint 1 1
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((fr500 (unit u-fr-r-store))) "Store byte float")
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(r-store rsthf HI OP_03 OPE1_29 FRint 2 1
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((fr500 (unit u-fr-r-store))) "Store half float")
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(r-store rstf SI OP_03 OPE1_2A FRint 4 1
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((fr500 (unit u-fr-r-store))) "Store word float")
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; Semantics for a store-double insn
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;
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(define-pmacro (store-double-semantics mode regtype address arg)
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@ -4530,26 +4500,6 @@
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(store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv)
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() "Store coprocessor double word")
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(define-pmacro (r-store-double
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name mode op ope regtype is_float attr profile comment)
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(dni name
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(comment)
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((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr)
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(.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
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(+ pack (.sym regtype doublek) op GRi ope GRj)
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(sequence ((WI address))
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(store-double-semantics mode regtype address GRj)
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(c-call VOID "@cpu@_check_recovering_store"
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address (index-of (.sym regtype doublek)) 8 is_float))
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profile
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)
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)
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(r-store-double rstd DI OP_03 OPE1_23 GR 0 NA
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((fr500 (unit u-gr-r-store))) "Store double word")
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(r-store-double rstdf DF OP_03 OPE1_2B FR 1 FR-ACCESS
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((fr500 (unit u-fr-r-store))) "Store double float")
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; Semantics for a store-quad insn
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;
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(define-pmacro (store-quad-semantics regtype address arg)
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@ -4579,25 +4529,6 @@
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(store-quad-r-r stqc OP_03 OPE1_27 CPR NA
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() "Store coprocessor quad word")
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(define-pmacro (r-store-quad name op ope regtype is_float attr profile comment)
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(dni name
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(comment)
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((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr)
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(.str name "$pack $" regtype "k,@($GRi,$GRj)")
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(+ pack (.sym regtype k) op GRi ope GRj)
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(sequence ((WI address))
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(store-quad-semantics regtype address GRj)
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(c-call VOID "@cpu@_check_recovering_store"
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address (index-of (.sym regtype k)) 16 is_float))
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profile
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)
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)
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(r-store-quad rstq OP_03 OPE1_24 GR 0 NA
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((fr500 (unit u-gr-r-store))) "Store quad word")
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(r-store-quad rstqf OP_03 OPE1_2C FRint 1 FR-ACCESS
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((fr500 (unit u-fr-r-store))) "Store quad float")
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(define-pmacro (store-r-r-u name mode op ope regtype attr profile comment)
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(dni name
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(comment)
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@ -1,3 +1,9 @@
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
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(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
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* gas/frv/allinsn.d: Update accordingly.
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2004-02-17 Petko Manolov <petkan@nucleusys.com>
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* gas/arm/maverick.c: DSPSC to/from opcode fixes.
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@ -514,22 +514,22 @@ Disassembly of section .text:
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2a0: 80 0c 19 41 stc cpr0,@\(sp,sp\)
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000002a4 <rstb>:
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2a4: 82 0c 18 01 rstb sp,@\(sp,sp\)
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2a4: 80 88 00 00 nop
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000002a8 <rsth>:
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2a8: 82 0c 18 41 rsth sp,@\(sp,sp\)
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2a8: 80 88 00 00 nop
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000002ac <rst>:
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2ac: 82 0c 18 81 rst sp,@\(sp,sp\)
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2ac: 80 88 00 00 nop
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000002b0 <rstbf>:
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2b0: 80 0c 1a 01 rstbf fr0,@\(sp,sp\)
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2b0: 80 88 00 00 nop
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000002b4 <rsthf>:
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2b4: 80 0c 1a 41 rsthf fr0,@\(sp,sp\)
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2b4: 80 88 00 00 nop
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000002b8 <rstf>:
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2b8: 80 0c 1a 81 rstf fr0,@\(sp,sp\)
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2b8: 80 88 00 00 nop
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000002bc <std>:
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2bc: 84 0c 10 c1 std fp,@\(sp,sp\)
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@ -541,10 +541,10 @@ Disassembly of section .text:
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2c4: 80 0c 19 81 stdc cpr0,@\(sp,sp\)
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000002c8 <rstd>:
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2c8: 84 0c 18 c1 rstd fp,@\(sp,sp\)
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2c8: 80 88 00 00 nop
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000002cc <rstdf>:
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2cc: 80 0c 1a c1 rstdf fr0,@\(sp,sp\)
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2cc: 80 88 00 00 nop
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000002d0 <stq>:
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2d0: 82 0c 11 01 stq sp,@\(sp,sp\)
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@ -556,10 +556,10 @@ Disassembly of section .text:
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2d8: 80 0c 19 c1 stqc cpr0,@\(sp,sp\)
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000002dc <rstq>:
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2dc: 82 0c 19 01 rstq sp,@\(sp,sp\)
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2dc: 80 88 00 00 nop
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000002e0 <rstqf>:
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2e0: 80 0c 1b 01 rstqf fr0,@\(sp,sp\)
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2e0: 80 88 00 00 nop
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000002e4 <stbu>:
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2e4: 82 0c 14 01 stbu sp,@\(sp,sp\)
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@ -681,27 +681,27 @@ stc:
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.text
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.global rstb
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rstb:
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rstb sp,@(sp,sp)
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nop
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.text
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.global rsth
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rsth:
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rsth sp,@(sp,sp)
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nop
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.text
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.global rst
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rst:
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rst sp,@(sp,sp)
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nop
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.text
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.global rstbf
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rstbf:
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rstbf fr0,@(sp,sp)
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nop
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.text
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.global rsthf
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rsthf:
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rsthf fr0,@(sp,sp)
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nop
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.text
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.global rstf
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rstf:
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rstf fr0,@(sp,sp)
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nop
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.text
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.global std
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std:
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@ -717,11 +717,11 @@ stdc:
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.text
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.global rstd
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rstd:
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rstd fp,@(sp,sp)
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nop
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.text
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.global rstdf
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rstdf:
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rstdf fr0,@(sp,sp)
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nop
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.text
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.global stq
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stq:
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@ -737,11 +737,11 @@ stqc:
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.text
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.global rstq
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rstq:
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rstq sp,@(sp,sp)
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nop
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.text
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.global rstqf
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rstqf:
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rstqf fr0,@(sp,sp)
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nop
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.text
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.global stbu
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stbu:
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@ -1,3 +1,7 @@
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
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2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
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* sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
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@ -3220,36 +3220,6 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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FRV_INSN_STC, "stc", "stc", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
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},
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/* rstb$pack $GRk,@($GRi,$GRj) */
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{
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FRV_INSN_RSTB, "rstb", "rstb", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rsth$pack $GRk,@($GRi,$GRj) */
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{
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FRV_INSN_RSTH, "rsth", "rsth", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rst$pack $GRk,@($GRi,$GRj) */
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{
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FRV_INSN_RST, "rst", "rst", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rstbf$pack $FRintk,@($GRi,$GRj) */
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{
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FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rsthf$pack $FRintk,@($GRi,$GRj) */
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{
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FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rstf$pack $FRintk,@($GRi,$GRj) */
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{
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FRV_INSN_RSTF, "rstf", "rstf", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* std$pack $GRdoublek,@($GRi,$GRj) */
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{
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FRV_INSN_STD, "std", "std", 32,
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@ -3265,16 +3235,6 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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FRV_INSN_STDC, "stdc", "stdc", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
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},
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/* rstd$pack $GRdoublek,@($GRi,$GRj) */
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{
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FRV_INSN_RSTD, "rstd", "rstd", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rstdf$pack $FRdoublek,@($GRi,$GRj) */
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{
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FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
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{ 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* stq$pack $GRk,@($GRi,$GRj) */
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{
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FRV_INSN_STQ, "stq", "stq", 32,
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@ -3290,16 +3250,6 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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FRV_INSN_STQC, "stqc", "stqc", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rstq$pack $GRk,@($GRi,$GRj) */
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{
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FRV_INSN_RSTQ, "rstq", "rstq", 32,
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{ 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* rstqf$pack $FRintk,@($GRi,$GRj) */
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{
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FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
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{ 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
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},
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/* stbu$pack $GRk,@($GRi,$GRj) */
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{
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FRV_INSN_STBU, "stbu", "stbu", 32,
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@ -2486,42 +2486,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
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{ { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
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& ifmt_ldc, { 0xc0940 }
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},
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/* rstb$pack $GRk,@($GRi,$GRj) */
|
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{
|
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{ 0, 0, 0, 0 },
|
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{ { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
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& ifmt_slass, { 0xc0800 }
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},
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/* rsth$pack $GRk,@($GRi,$GRj) */
|
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{
|
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{ 0, 0, 0, 0 },
|
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{ { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
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& ifmt_slass, { 0xc0840 }
|
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},
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/* rst$pack $GRk,@($GRi,$GRj) */
|
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{
|
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{ 0, 0, 0, 0 },
|
||||
{ { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
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& ifmt_slass, { 0xc0880 }
|
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},
|
||||
/* rstbf$pack $FRintk,@($GRi,$GRj) */
|
||||
{
|
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{ 0, 0, 0, 0 },
|
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{ { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_ldbf, { 0xc0a00 }
|
||||
},
|
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/* rsthf$pack $FRintk,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
{ { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_ldbf, { 0xc0a40 }
|
||||
},
|
||||
/* rstf$pack $FRintk,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
{ { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_ldbf, { 0xc0a80 }
|
||||
},
|
||||
/* std$pack $GRdoublek,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
@ -2540,18 +2504,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
|
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{ { MNEM, OP (PACK), ' ', OP (CPRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_lddc, { 0xc0980 }
|
||||
},
|
||||
/* rstd$pack $GRdoublek,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
{ { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_ldd, { 0xc08c0 }
|
||||
},
|
||||
/* rstdf$pack $FRdoublek,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
{ { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_lddf, { 0xc0ac0 }
|
||||
},
|
||||
/* stq$pack $GRk,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
@ -2570,18 +2522,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
|
||||
{ { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_ldc, { 0xc09c0 }
|
||||
},
|
||||
/* rstq$pack $GRk,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
{ { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_slass, { 0xc0900 }
|
||||
},
|
||||
/* rstqf$pack $FRintk,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
{ { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
|
||||
& ifmt_ldbf, { 0xc0b00 }
|
||||
},
|
||||
/* stbu$pack $GRk,@($GRi,$GRj) */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
|
||||
@ -108,149 +108,147 @@ typedef enum cgen_insn_type {
|
||||
, FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI, FRV_INSN_NLDDFI
|
||||
, FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQFI, FRV_INSN_STB
|
||||
, FRV_INSN_STH, FRV_INSN_ST, FRV_INSN_STBF, FRV_INSN_STHF
|
||||
, FRV_INSN_STF, FRV_INSN_STC, FRV_INSN_RSTB, FRV_INSN_RSTH
|
||||
, FRV_INSN_RST, FRV_INSN_RSTBF, FRV_INSN_RSTHF, FRV_INSN_RSTF
|
||||
, FRV_INSN_STD, FRV_INSN_STDF, FRV_INSN_STDC, FRV_INSN_RSTD
|
||||
, FRV_INSN_RSTDF, FRV_INSN_STQ, FRV_INSN_STQF, FRV_INSN_STQC
|
||||
, FRV_INSN_RSTQ, FRV_INSN_RSTQF, FRV_INSN_STBU, FRV_INSN_STHU
|
||||
, FRV_INSN_STU, FRV_INSN_STBFU, FRV_INSN_STHFU, FRV_INSN_STFU
|
||||
, FRV_INSN_STCU, FRV_INSN_STDU, FRV_INSN_STDFU, FRV_INSN_STDCU
|
||||
, FRV_INSN_STQU, FRV_INSN_STQFU, FRV_INSN_STQCU, FRV_INSN_CLDSB
|
||||
, FRV_INSN_CLDUB, FRV_INSN_CLDSH, FRV_INSN_CLDUH, FRV_INSN_CLD
|
||||
, FRV_INSN_CLDBF, FRV_INSN_CLDHF, FRV_INSN_CLDF, FRV_INSN_CLDD
|
||||
, FRV_INSN_CLDDF, FRV_INSN_CLDQ, FRV_INSN_CLDSBU, FRV_INSN_CLDUBU
|
||||
, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU, FRV_INSN_CLDU, FRV_INSN_CLDBFU
|
||||
, FRV_INSN_CLDHFU, FRV_INSN_CLDFU, FRV_INSN_CLDDU, FRV_INSN_CLDDFU
|
||||
, FRV_INSN_CLDQU, FRV_INSN_CSTB, FRV_INSN_CSTH, FRV_INSN_CST
|
||||
, FRV_INSN_CSTBF, FRV_INSN_CSTHF, FRV_INSN_CSTF, FRV_INSN_CSTD
|
||||
, FRV_INSN_CSTDF, FRV_INSN_CSTQ, FRV_INSN_CSTBU, FRV_INSN_CSTHU
|
||||
, FRV_INSN_CSTU, FRV_INSN_CSTBFU, FRV_INSN_CSTHFU, FRV_INSN_CSTFU
|
||||
, FRV_INSN_CSTDU, FRV_INSN_CSTDFU, FRV_INSN_STBI, FRV_INSN_STHI
|
||||
, FRV_INSN_STI, FRV_INSN_STBFI, FRV_INSN_STHFI, FRV_INSN_STFI
|
||||
, FRV_INSN_STDI, FRV_INSN_STDFI, FRV_INSN_STQI, FRV_INSN_STQFI
|
||||
, FRV_INSN_SWAP, FRV_INSN_SWAPI, FRV_INSN_CSWAP, FRV_INSN_MOVGF
|
||||
, FRV_INSN_MOVFG, FRV_INSN_MOVGFD, FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ
|
||||
, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF, FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD
|
||||
, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS, FRV_INSN_MOVSG, FRV_INSN_BRA
|
||||
, FRV_INSN_BNO, FRV_INSN_BEQ, FRV_INSN_BNE, FRV_INSN_BLE
|
||||
, FRV_INSN_BGT, FRV_INSN_BLT, FRV_INSN_BGE, FRV_INSN_BLS
|
||||
, FRV_INSN_BHI, FRV_INSN_BC, FRV_INSN_BNC, FRV_INSN_BN
|
||||
, FRV_INSN_BP, FRV_INSN_BV, FRV_INSN_BNV, FRV_INSN_FBRA
|
||||
, FRV_INSN_FBNO, FRV_INSN_FBNE, FRV_INSN_FBEQ, FRV_INSN_FBLG
|
||||
, FRV_INSN_FBUE, FRV_INSN_FBUL, FRV_INSN_FBGE, FRV_INSN_FBLT
|
||||
, FRV_INSN_FBUGE, FRV_INSN_FBUG, FRV_INSN_FBLE, FRV_INSN_FBGT
|
||||
, FRV_INSN_FBULE, FRV_INSN_FBU, FRV_INSN_FBO, FRV_INSN_BCTRLR
|
||||
, FRV_INSN_BRALR, FRV_INSN_BNOLR, FRV_INSN_BEQLR, FRV_INSN_BNELR
|
||||
, FRV_INSN_BLELR, FRV_INSN_BGTLR, FRV_INSN_BLTLR, FRV_INSN_BGELR
|
||||
, FRV_INSN_BLSLR, FRV_INSN_BHILR, FRV_INSN_BCLR, FRV_INSN_BNCLR
|
||||
, FRV_INSN_BNLR, FRV_INSN_BPLR, FRV_INSN_BVLR, FRV_INSN_BNVLR
|
||||
, FRV_INSN_FBRALR, FRV_INSN_FBNOLR, FRV_INSN_FBEQLR, FRV_INSN_FBNELR
|
||||
, FRV_INSN_FBLGLR, FRV_INSN_FBUELR, FRV_INSN_FBULLR, FRV_INSN_FBGELR
|
||||
, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR, FRV_INSN_FBUGLR, FRV_INSN_FBLELR
|
||||
, FRV_INSN_FBGTLR, FRV_INSN_FBULELR, FRV_INSN_FBULR, FRV_INSN_FBOLR
|
||||
, FRV_INSN_BCRALR, FRV_INSN_BCNOLR, FRV_INSN_BCEQLR, FRV_INSN_BCNELR
|
||||
, FRV_INSN_BCLELR, FRV_INSN_BCGTLR, FRV_INSN_BCLTLR, FRV_INSN_BCGELR
|
||||
, FRV_INSN_BCLSLR, FRV_INSN_BCHILR, FRV_INSN_BCCLR, FRV_INSN_BCNCLR
|
||||
, FRV_INSN_BCNLR, FRV_INSN_BCPLR, FRV_INSN_BCVLR, FRV_INSN_BCNVLR
|
||||
, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR, FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR
|
||||
, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR, FRV_INSN_FCBULLR, FRV_INSN_FCBGELR
|
||||
, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR, FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR
|
||||
, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR, FRV_INSN_FCBULR, FRV_INSN_FCBOLR
|
||||
, FRV_INSN_JMPL, FRV_INSN_CALLL, FRV_INSN_JMPIL, FRV_INSN_CALLIL
|
||||
, FRV_INSN_CALL, FRV_INSN_RETT, FRV_INSN_REI, FRV_INSN_TRA
|
||||
, FRV_INSN_TNO, FRV_INSN_TEQ, FRV_INSN_TNE, FRV_INSN_TLE
|
||||
, FRV_INSN_TGT, FRV_INSN_TLT, FRV_INSN_TGE, FRV_INSN_TLS
|
||||
, FRV_INSN_THI, FRV_INSN_TC, FRV_INSN_TNC, FRV_INSN_TN
|
||||
, FRV_INSN_TP, FRV_INSN_TV, FRV_INSN_TNV, FRV_INSN_FTRA
|
||||
, FRV_INSN_FTNO, FRV_INSN_FTNE, FRV_INSN_FTEQ, FRV_INSN_FTLG
|
||||
, FRV_INSN_FTUE, FRV_INSN_FTUL, FRV_INSN_FTGE, FRV_INSN_FTLT
|
||||
, FRV_INSN_FTUGE, FRV_INSN_FTUG, FRV_INSN_FTLE, FRV_INSN_FTGT
|
||||
, FRV_INSN_FTULE, FRV_INSN_FTU, FRV_INSN_FTO, FRV_INSN_TIRA
|
||||
, FRV_INSN_TINO, FRV_INSN_TIEQ, FRV_INSN_TINE, FRV_INSN_TILE
|
||||
, FRV_INSN_TIGT, FRV_INSN_TILT, FRV_INSN_TIGE, FRV_INSN_TILS
|
||||
, FRV_INSN_TIHI, FRV_INSN_TIC, FRV_INSN_TINC, FRV_INSN_TIN
|
||||
, FRV_INSN_TIP, FRV_INSN_TIV, FRV_INSN_TINV, FRV_INSN_FTIRA
|
||||
, FRV_INSN_FTINO, FRV_INSN_FTINE, FRV_INSN_FTIEQ, FRV_INSN_FTILG
|
||||
, FRV_INSN_FTIUE, FRV_INSN_FTIUL, FRV_INSN_FTIGE, FRV_INSN_FTILT
|
||||
, FRV_INSN_FTIUGE, FRV_INSN_FTIUG, FRV_INSN_FTILE, FRV_INSN_FTIGT
|
||||
, FRV_INSN_FTIULE, FRV_INSN_FTIU, FRV_INSN_FTIO, FRV_INSN_BREAK
|
||||
, FRV_INSN_MTRAP, FRV_INSN_ANDCR, FRV_INSN_ORCR, FRV_INSN_XORCR
|
||||
, FRV_INSN_NANDCR, FRV_INSN_NORCR, FRV_INSN_ANDNCR, FRV_INSN_ORNCR
|
||||
, FRV_INSN_NANDNCR, FRV_INSN_NORNCR, FRV_INSN_NOTCR, FRV_INSN_CKRA
|
||||
, FRV_INSN_CKNO, FRV_INSN_CKEQ, FRV_INSN_CKNE, FRV_INSN_CKLE
|
||||
, FRV_INSN_CKGT, FRV_INSN_CKLT, FRV_INSN_CKGE, FRV_INSN_CKLS
|
||||
, FRV_INSN_CKHI, FRV_INSN_CKC, FRV_INSN_CKNC, FRV_INSN_CKN
|
||||
, FRV_INSN_CKP, FRV_INSN_CKV, FRV_INSN_CKNV, FRV_INSN_FCKRA
|
||||
, FRV_INSN_FCKNO, FRV_INSN_FCKNE, FRV_INSN_FCKEQ, FRV_INSN_FCKLG
|
||||
, FRV_INSN_FCKUE, FRV_INSN_FCKUL, FRV_INSN_FCKGE, FRV_INSN_FCKLT
|
||||
, FRV_INSN_FCKUGE, FRV_INSN_FCKUG, FRV_INSN_FCKLE, FRV_INSN_FCKGT
|
||||
, FRV_INSN_FCKULE, FRV_INSN_FCKU, FRV_INSN_FCKO, FRV_INSN_CCKRA
|
||||
, FRV_INSN_CCKNO, FRV_INSN_CCKEQ, FRV_INSN_CCKNE, FRV_INSN_CCKLE
|
||||
, FRV_INSN_CCKGT, FRV_INSN_CCKLT, FRV_INSN_CCKGE, FRV_INSN_CCKLS
|
||||
, FRV_INSN_CCKHI, FRV_INSN_CCKC, FRV_INSN_CCKNC, FRV_INSN_CCKN
|
||||
, FRV_INSN_CCKP, FRV_INSN_CCKV, FRV_INSN_CCKNV, FRV_INSN_CFCKRA
|
||||
, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE, FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG
|
||||
, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL, FRV_INSN_CFCKGE, FRV_INSN_CFCKLT
|
||||
, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG, FRV_INSN_CFCKLE, FRV_INSN_CFCKGT
|
||||
, FRV_INSN_CFCKULE, FRV_INSN_CFCKU, FRV_INSN_CFCKO, FRV_INSN_CJMPL
|
||||
, FRV_INSN_CCALLL, FRV_INSN_ICI, FRV_INSN_DCI, FRV_INSN_ICEI
|
||||
, FRV_INSN_DCEI, FRV_INSN_DCF, FRV_INSN_DCEF, FRV_INSN_WITLB
|
||||
, FRV_INSN_WDTLB, FRV_INSN_ITLBI, FRV_INSN_DTLBI, FRV_INSN_ICPL
|
||||
, FRV_INSN_DCPL, FRV_INSN_ICUL, FRV_INSN_DCUL, FRV_INSN_BAR
|
||||
, FRV_INSN_MEMBAR, FRV_INSN_COP1, FRV_INSN_COP2, FRV_INSN_CLRGR
|
||||
, FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA, FRV_INSN_COMMITGR
|
||||
, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA, FRV_INSN_FITOS
|
||||
, FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI, FRV_INSN_FDITOS
|
||||
, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI, FRV_INSN_CFITOS
|
||||
, FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI, FRV_INSN_FMOVS
|
||||
, FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS, FRV_INSN_FNEGS
|
||||
, FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS, FRV_INSN_FABSS
|
||||
, FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS, FRV_INSN_FSQRTS
|
||||
, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS
|
||||
, FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS, FRV_INSN_FMULS
|
||||
, FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD, FRV_INSN_FMULD
|
||||
, FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS, FRV_INSN_CFMULS
|
||||
, FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS, FRV_INSN_NFMULS
|
||||
, FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD, FRV_INSN_CFCMPS
|
||||
, FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS, FRV_INSN_FMADDD
|
||||
, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS
|
||||
, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS, FRV_INSN_FMAS
|
||||
, FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS, FRV_INSN_NFDMAS
|
||||
, FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS, FRV_INSN_FMAD
|
||||
, FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS, FRV_INSN_FDADDS
|
||||
, FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS, FRV_INSN_FDSADS
|
||||
, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS
|
||||
, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS
|
||||
, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH
|
||||
, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND, FRV_INSN_MOR
|
||||
, FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR, FRV_INSN_CMXOR
|
||||
, FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI, FRV_INSN_MROTRI
|
||||
, FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT, FRV_INSN_MCUTI
|
||||
, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH
|
||||
, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI, FRV_INSN_MDROTLI
|
||||
, FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS, FRV_INSN_MQSATHS
|
||||
, FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH, FRV_INSN_MABSHS
|
||||
, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS
|
||||
, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS
|
||||
, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS
|
||||
, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS
|
||||
, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS
|
||||
, FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS, FRV_INSN_MMULHU
|
||||
, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS, FRV_INSN_CMMULHU
|
||||
, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU
|
||||
, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS, FRV_INSN_MMACHU
|
||||
, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS, FRV_INSN_CMMACHU
|
||||
, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU
|
||||
, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS
|
||||
, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS
|
||||
, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS
|
||||
, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW
|
||||
, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH
|
||||
, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH
|
||||
, FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB, FRV_INSN_MBTOHE
|
||||
, FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1
|
||||
, FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC, FRV_INSN_MWTACCG
|
||||
, FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
|
||||
, FRV_INSN_STF, FRV_INSN_STC, FRV_INSN_STD, FRV_INSN_STDF
|
||||
, FRV_INSN_STDC, FRV_INSN_STQ, FRV_INSN_STQF, FRV_INSN_STQC
|
||||
, FRV_INSN_STBU, FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU
|
||||
, FRV_INSN_STHFU, FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU
|
||||
, FRV_INSN_STDFU, FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU
|
||||
, FRV_INSN_STQCU, FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH
|
||||
, FRV_INSN_CLDUH, FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF
|
||||
, FRV_INSN_CLDF, FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ
|
||||
, FRV_INSN_CLDSBU, FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU
|
||||
, FRV_INSN_CLDU, FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU
|
||||
, FRV_INSN_CLDDU, FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB
|
||||
, FRV_INSN_CSTH, FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF
|
||||
, FRV_INSN_CSTF, FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ
|
||||
, FRV_INSN_CSTBU, FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU
|
||||
, FRV_INSN_CSTHFU, FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU
|
||||
, FRV_INSN_STBI, FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI
|
||||
, FRV_INSN_STHFI, FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI
|
||||
, FRV_INSN_STQI, FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI
|
||||
, FRV_INSN_CSWAP, FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD
|
||||
, FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF
|
||||
, FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS
|
||||
, FRV_INSN_MOVSG, FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ
|
||||
, FRV_INSN_BNE, FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT
|
||||
, FRV_INSN_BGE, FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC
|
||||
, FRV_INSN_BNC, FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV
|
||||
, FRV_INSN_BNV, FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE
|
||||
, FRV_INSN_FBEQ, FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL
|
||||
, FRV_INSN_FBGE, FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG
|
||||
, FRV_INSN_FBLE, FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU
|
||||
, FRV_INSN_FBO, FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR
|
||||
, FRV_INSN_BEQLR, FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR
|
||||
, FRV_INSN_BLTLR, FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR
|
||||
, FRV_INSN_BCLR, FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR
|
||||
, FRV_INSN_BVLR, FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR
|
||||
, FRV_INSN_FBEQLR, FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR
|
||||
, FRV_INSN_FBULLR, FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR
|
||||
, FRV_INSN_FBUGLR, FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR
|
||||
, FRV_INSN_FBULR, FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR
|
||||
, FRV_INSN_BCEQLR, FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR
|
||||
, FRV_INSN_BCLTLR, FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR
|
||||
, FRV_INSN_BCCLR, FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR
|
||||
, FRV_INSN_BCVLR, FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR
|
||||
, FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR
|
||||
, FRV_INSN_FCBULLR, FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR
|
||||
, FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR
|
||||
, FRV_INSN_FCBULR, FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL
|
||||
, FRV_INSN_JMPIL, FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT
|
||||
, FRV_INSN_REI, FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ
|
||||
, FRV_INSN_TNE, FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT
|
||||
, FRV_INSN_TGE, FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC
|
||||
, FRV_INSN_TNC, FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV
|
||||
, FRV_INSN_TNV, FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE
|
||||
, FRV_INSN_FTEQ, FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL
|
||||
, FRV_INSN_FTGE, FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG
|
||||
, FRV_INSN_FTLE, FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU
|
||||
, FRV_INSN_FTO, FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ
|
||||
, FRV_INSN_TINE, FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT
|
||||
, FRV_INSN_TIGE, FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC
|
||||
, FRV_INSN_TINC, FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV
|
||||
, FRV_INSN_TINV, FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE
|
||||
, FRV_INSN_FTIEQ, FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL
|
||||
, FRV_INSN_FTIGE, FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG
|
||||
, FRV_INSN_FTILE, FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU
|
||||
, FRV_INSN_FTIO, FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR
|
||||
, FRV_INSN_ORCR, FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR
|
||||
, FRV_INSN_ANDNCR, FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR
|
||||
, FRV_INSN_NOTCR, FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ
|
||||
, FRV_INSN_CKNE, FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT
|
||||
, FRV_INSN_CKGE, FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC
|
||||
, FRV_INSN_CKNC, FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV
|
||||
, FRV_INSN_CKNV, FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE
|
||||
, FRV_INSN_FCKEQ, FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL
|
||||
, FRV_INSN_FCKGE, FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG
|
||||
, FRV_INSN_FCKLE, FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU
|
||||
, FRV_INSN_FCKO, FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ
|
||||
, FRV_INSN_CCKNE, FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT
|
||||
, FRV_INSN_CCKGE, FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC
|
||||
, FRV_INSN_CCKNC, FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV
|
||||
, FRV_INSN_CCKNV, FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE
|
||||
, FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL
|
||||
, FRV_INSN_CFCKGE, FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG
|
||||
, FRV_INSN_CFCKLE, FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU
|
||||
, FRV_INSN_CFCKO, FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI
|
||||
, FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF
|
||||
, FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI
|
||||
, FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL
|
||||
, FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1
|
||||
, FRV_INSN_COP2, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA
|
||||
, FRV_INSN_CLRFA, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA
|
||||
, FRV_INSN_COMMITFA, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD
|
||||
, FRV_INSN_FDTOI, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS
|
||||
, FRV_INSN_NFDSTOI, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS
|
||||
, FRV_INSN_NFSTOI, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS
|
||||
, FRV_INSN_CFMOVS, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS
|
||||
, FRV_INSN_CFNEGS, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS
|
||||
, FRV_INSN_CFABSS, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS
|
||||
, FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS
|
||||
, FRV_INSN_FSUBS, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD
|
||||
, FRV_INSN_FSUBD, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS
|
||||
, FRV_INSN_CFSUBS, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS
|
||||
, FRV_INSN_NFSUBS, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS
|
||||
, FRV_INSN_FCMPD, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS
|
||||
, FRV_INSN_FMSUBS, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS
|
||||
, FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS
|
||||
, FRV_INSN_NFMSUBS, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS
|
||||
, FRV_INSN_FDMSS, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS
|
||||
, FRV_INSN_CFMSS, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS
|
||||
, FRV_INSN_NFMSS, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS
|
||||
, FRV_INSN_FDDIVS, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS
|
||||
, FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS
|
||||
, FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS
|
||||
, FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH
|
||||
, FRV_INSN_MAND, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND
|
||||
, FRV_INSN_CMOR, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT
|
||||
, FRV_INSN_MROTLI, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI
|
||||
, FRV_INSN_MCUT, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI
|
||||
, FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI
|
||||
, FRV_INSN_MSRAHI, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI
|
||||
, FRV_INSN_MSATHS, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH
|
||||
, FRV_INSN_MCMPUH, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS
|
||||
, FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS
|
||||
, FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS
|
||||
, FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS
|
||||
, FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS
|
||||
, FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS
|
||||
, FRV_INSN_MMULHS, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU
|
||||
, FRV_INSN_CMMULHS, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU
|
||||
, FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU
|
||||
, FRV_INSN_MMACHS, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU
|
||||
, FRV_INSN_CMMACHS, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU
|
||||
, FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS
|
||||
, FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS
|
||||
, FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS
|
||||
, FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS
|
||||
, FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD
|
||||
, FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH
|
||||
, FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB
|
||||
, FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP
|
||||
, FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG
|
||||
, FRV_INSN_MWTACC, FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2
|
||||
, FRV_INSN_FNOP
|
||||
} CGEN_INSN_TYPE;
|
||||
|
||||
/* Index of `invalid' insn place holder. */
|
||||
|
||||
@ -1,3 +1,7 @@
|
||||
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* decode.c, decode.h, model.c, sem.c: Regenerate.
|
||||
|
||||
2003-11-24 Kevin Buettner <kevinb@redhat.com>
|
||||
|
||||
* frv-sim.h (GR_REGNUM_MAX, FR_REGNUM_MAX, PC_REGNUM, SPR_REGNUM_MIN)
|
||||
|
||||
148
sim/frv/decode.c
148
sim/frv/decode.c
@ -223,22 +223,12 @@ static const struct insn_sem frvbf_insn_sem[] =
|
||||
{ FRV_INSN_STHF, FRVBF_INSN_STHF, FRVBF_SFMT_STBF },
|
||||
{ FRV_INSN_STF, FRVBF_INSN_STF, FRVBF_SFMT_STBF },
|
||||
{ FRV_INSN_STC, FRVBF_INSN_STC, FRVBF_SFMT_STC },
|
||||
{ FRV_INSN_RSTB, FRVBF_INSN_RSTB, FRVBF_SFMT_RSTB },
|
||||
{ FRV_INSN_RSTH, FRVBF_INSN_RSTH, FRVBF_SFMT_RSTB },
|
||||
{ FRV_INSN_RST, FRVBF_INSN_RST, FRVBF_SFMT_RSTB },
|
||||
{ FRV_INSN_RSTBF, FRVBF_INSN_RSTBF, FRVBF_SFMT_RSTBF },
|
||||
{ FRV_INSN_RSTHF, FRVBF_INSN_RSTHF, FRVBF_SFMT_RSTBF },
|
||||
{ FRV_INSN_RSTF, FRVBF_INSN_RSTF, FRVBF_SFMT_RSTBF },
|
||||
{ FRV_INSN_STD, FRVBF_INSN_STD, FRVBF_SFMT_STD },
|
||||
{ FRV_INSN_STDF, FRVBF_INSN_STDF, FRVBF_SFMT_STDF },
|
||||
{ FRV_INSN_STDC, FRVBF_INSN_STDC, FRVBF_SFMT_STDC },
|
||||
{ FRV_INSN_RSTD, FRVBF_INSN_RSTD, FRVBF_SFMT_RSTD },
|
||||
{ FRV_INSN_RSTDF, FRVBF_INSN_RSTDF, FRVBF_SFMT_RSTDF },
|
||||
{ FRV_INSN_STQ, FRVBF_INSN_STQ, FRVBF_SFMT_LDQ },
|
||||
{ FRV_INSN_STQF, FRVBF_INSN_STQF, FRVBF_SFMT_LDQF },
|
||||
{ FRV_INSN_STQC, FRVBF_INSN_STQC, FRVBF_SFMT_LDQC },
|
||||
{ FRV_INSN_RSTQ, FRVBF_INSN_RSTQ, FRVBF_SFMT_LDQ },
|
||||
{ FRV_INSN_RSTQF, FRVBF_INSN_RSTQF, FRVBF_SFMT_LDQF },
|
||||
{ FRV_INSN_STBU, FRVBF_INSN_STBU, FRVBF_SFMT_STBU },
|
||||
{ FRV_INSN_STHU, FRVBF_INSN_STHU, FRVBF_SFMT_STBU },
|
||||
{ FRV_INSN_STU, FRVBF_INSN_STU, FRVBF_SFMT_STBU },
|
||||
@ -1014,19 +1004,9 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
|
||||
case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu;
|
||||
case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu;
|
||||
case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu;
|
||||
case 32 : itype = FRVBF_INSN_RSTB; goto extract_sfmt_rstb;
|
||||
case 33 : itype = FRVBF_INSN_RSTH; goto extract_sfmt_rstb;
|
||||
case 34 : itype = FRVBF_INSN_RST; goto extract_sfmt_rstb;
|
||||
case 35 : itype = FRVBF_INSN_RSTD; goto extract_sfmt_rstd;
|
||||
case 36 : itype = FRVBF_INSN_RSTQ; goto extract_sfmt_ldq;
|
||||
case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc;
|
||||
case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc;
|
||||
case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc;
|
||||
case 40 : itype = FRVBF_INSN_RSTBF; goto extract_sfmt_rstbf;
|
||||
case 41 : itype = FRVBF_INSN_RSTHF; goto extract_sfmt_rstbf;
|
||||
case 42 : itype = FRVBF_INSN_RSTF; goto extract_sfmt_rstbf;
|
||||
case 43 : itype = FRVBF_INSN_RSTDF; goto extract_sfmt_rstdf;
|
||||
case 44 : itype = FRVBF_INSN_RSTQF; goto extract_sfmt_ldqf;
|
||||
case 45 : itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu;
|
||||
case 46 : itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu;
|
||||
case 47 : itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu;
|
||||
@ -4613,70 +4593,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
|
||||
FLD (in_GRj) = f_GRj;
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
return idesc;
|
||||
}
|
||||
|
||||
extract_sfmt_rstb:
|
||||
{
|
||||
const IDESC *idesc = &frvbf_insn_data[itype];
|
||||
CGEN_INSN_INT insn = entire_insn;
|
||||
#define FLD(f) abuf->fields.sfmt_cswap.f
|
||||
UINT f_GRk;
|
||||
UINT f_GRi;
|
||||
UINT f_GRj;
|
||||
|
||||
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
|
||||
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
|
||||
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_GRi) = f_GRi;
|
||||
FLD (f_GRj) = f_GRj;
|
||||
FLD (f_GRk) = f_GRk;
|
||||
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
/* Record the fields for profiling. */
|
||||
if (PROFILE_MODEL_P (current_cpu))
|
||||
{
|
||||
FLD (in_GRi) = f_GRi;
|
||||
FLD (in_GRj) = f_GRj;
|
||||
FLD (in_GRk) = f_GRk;
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
return idesc;
|
||||
}
|
||||
|
||||
extract_sfmt_rstbf:
|
||||
{
|
||||
const IDESC *idesc = &frvbf_insn_data[itype];
|
||||
CGEN_INSN_INT insn = entire_insn;
|
||||
#define FLD(f) abuf->fields.sfmt_cstbfu.f
|
||||
UINT f_FRk;
|
||||
UINT f_GRi;
|
||||
UINT f_GRj;
|
||||
|
||||
f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
|
||||
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
|
||||
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_FRk) = f_FRk;
|
||||
FLD (f_GRi) = f_GRi;
|
||||
FLD (f_GRj) = f_GRj;
|
||||
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
/* Record the fields for profiling. */
|
||||
if (PROFILE_MODEL_P (current_cpu))
|
||||
{
|
||||
FLD (in_FRintk) = f_FRk;
|
||||
FLD (in_GRi) = f_GRi;
|
||||
FLD (in_GRj) = f_GRj;
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
return idesc;
|
||||
}
|
||||
@ -4773,70 +4689,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
|
||||
FLD (in_GRj) = f_GRj;
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
return idesc;
|
||||
}
|
||||
|
||||
extract_sfmt_rstd:
|
||||
{
|
||||
const IDESC *idesc = &frvbf_insn_data[itype];
|
||||
CGEN_INSN_INT insn = entire_insn;
|
||||
#define FLD(f) abuf->fields.sfmt_cstdu.f
|
||||
UINT f_GRk;
|
||||
UINT f_GRi;
|
||||
UINT f_GRj;
|
||||
|
||||
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
|
||||
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
|
||||
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_GRk) = f_GRk;
|
||||
FLD (f_GRi) = f_GRi;
|
||||
FLD (f_GRj) = f_GRj;
|
||||
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstd", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
/* Record the fields for profiling. */
|
||||
if (PROFILE_MODEL_P (current_cpu))
|
||||
{
|
||||
FLD (in_GRdoublek) = f_GRk;
|
||||
FLD (in_GRi) = f_GRi;
|
||||
FLD (in_GRj) = f_GRj;
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
return idesc;
|
||||
}
|
||||
|
||||
extract_sfmt_rstdf:
|
||||
{
|
||||
const IDESC *idesc = &frvbf_insn_data[itype];
|
||||
CGEN_INSN_INT insn = entire_insn;
|
||||
#define FLD(f) abuf->fields.sfmt_cstdfu.f
|
||||
UINT f_FRk;
|
||||
UINT f_GRi;
|
||||
UINT f_GRj;
|
||||
|
||||
f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
|
||||
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
|
||||
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_FRk) = f_FRk;
|
||||
FLD (f_GRi) = f_GRi;
|
||||
FLD (f_GRj) = f_GRj;
|
||||
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
/* Record the fields for profiling. */
|
||||
if (PROFILE_MODEL_P (current_cpu))
|
||||
{
|
||||
FLD (in_FRdoublek) = f_FRk;
|
||||
FLD (in_GRi) = f_GRi;
|
||||
FLD (in_GRj) = f_GRj;
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
return idesc;
|
||||
}
|
||||
|
||||
288
sim/frv/decode.h
288
sim/frv/decode.h
@ -79,150 +79,147 @@ typedef enum frvbf_insn_type {
|
||||
, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI, FRVBF_INSN_NLDDI
|
||||
, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI, FRVBF_INSN_NLDQFI
|
||||
, FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST, FRVBF_INSN_STBF
|
||||
, FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_RSTB
|
||||
, FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF
|
||||
, FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF, FRVBF_INSN_STDC
|
||||
, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ, FRVBF_INSN_STQF
|
||||
, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF, FRVBF_INSN_STBU
|
||||
, FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU
|
||||
, FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU, FRVBF_INSN_STDFU
|
||||
, FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU
|
||||
, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH
|
||||
, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF
|
||||
, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU
|
||||
, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU
|
||||
, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU
|
||||
, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH
|
||||
, FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF
|
||||
, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU
|
||||
, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU
|
||||
, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI
|
||||
, FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI
|
||||
, FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI, FRVBF_INSN_STQI
|
||||
, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP
|
||||
, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD
|
||||
, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG
|
||||
, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG
|
||||
, FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ, FRVBF_INSN_BNE
|
||||
, FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT, FRVBF_INSN_BGE
|
||||
, FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC, FRVBF_INSN_BNC
|
||||
, FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV, FRVBF_INSN_BNV
|
||||
, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ
|
||||
, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE
|
||||
, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE
|
||||
, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU, FRVBF_INSN_FBO
|
||||
, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR
|
||||
, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR
|
||||
, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR
|
||||
, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR
|
||||
, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR
|
||||
, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR
|
||||
, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR
|
||||
, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR
|
||||
, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR
|
||||
, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR
|
||||
, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR
|
||||
, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR
|
||||
, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR
|
||||
, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR
|
||||
, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR
|
||||
, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR
|
||||
, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL
|
||||
, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT, FRVBF_INSN_REI
|
||||
, FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ, FRVBF_INSN_TNE
|
||||
, FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT, FRVBF_INSN_TGE
|
||||
, FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC, FRVBF_INSN_TNC
|
||||
, FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV, FRVBF_INSN_TNV
|
||||
, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ
|
||||
, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE
|
||||
, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE
|
||||
, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU, FRVBF_INSN_FTO
|
||||
, FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE
|
||||
, FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT, FRVBF_INSN_TIGE
|
||||
, FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC, FRVBF_INSN_TINC
|
||||
, FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV, FRVBF_INSN_TINV
|
||||
, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ
|
||||
, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE
|
||||
, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE
|
||||
, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO
|
||||
, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR
|
||||
, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR
|
||||
, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR
|
||||
, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE
|
||||
, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE
|
||||
, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC, FRVBF_INSN_CKNC
|
||||
, FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV, FRVBF_INSN_CKNV
|
||||
, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ
|
||||
, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE
|
||||
, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE
|
||||
, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO
|
||||
, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE
|
||||
, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE
|
||||
, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC
|
||||
, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV
|
||||
, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ
|
||||
, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE
|
||||
, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE
|
||||
, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO
|
||||
, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI, FRVBF_INSN_DCI
|
||||
, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF, FRVBF_INSN_DCEF
|
||||
, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI
|
||||
, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL
|
||||
, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1, FRVBF_INSN_COP2
|
||||
, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA
|
||||
, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA
|
||||
, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI
|
||||
, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI
|
||||
, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI
|
||||
, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS
|
||||
, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS
|
||||
, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS
|
||||
, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD
|
||||
, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS
|
||||
, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD
|
||||
, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS
|
||||
, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS
|
||||
, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD
|
||||
, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS
|
||||
, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS
|
||||
, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS
|
||||
, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS
|
||||
, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS
|
||||
, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS
|
||||
, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS
|
||||
, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS
|
||||
, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS
|
||||
, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS
|
||||
, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND
|
||||
, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR
|
||||
, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI
|
||||
, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT
|
||||
, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI
|
||||
, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI
|
||||
, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS
|
||||
, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH
|
||||
, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS
|
||||
, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS
|
||||
, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS
|
||||
, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS
|
||||
, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS
|
||||
, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS
|
||||
, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS
|
||||
, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS
|
||||
, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS
|
||||
, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS
|
||||
, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS
|
||||
, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS
|
||||
, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU
|
||||
, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU
|
||||
, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU
|
||||
, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD
|
||||
, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH
|
||||
, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB
|
||||
, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0
|
||||
, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC
|
||||
, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP
|
||||
, FRVBF_INSN__MAX
|
||||
, FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_STD
|
||||
, FRVBF_INSN_STDF, FRVBF_INSN_STDC, FRVBF_INSN_STQ, FRVBF_INSN_STQF
|
||||
, FRVBF_INSN_STQC, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU
|
||||
, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU
|
||||
, FRVBF_INSN_STDU, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU
|
||||
, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB
|
||||
, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF
|
||||
, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF
|
||||
, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU
|
||||
, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU
|
||||
, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU
|
||||
, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF
|
||||
, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF
|
||||
, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU
|
||||
, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU
|
||||
, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI
|
||||
, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI
|
||||
, FRVBF_INSN_STDFI, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP
|
||||
, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG
|
||||
, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ
|
||||
, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD
|
||||
, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO
|
||||
, FRVBF_INSN_BEQ, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT
|
||||
, FRVBF_INSN_BLT, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI
|
||||
, FRVBF_INSN_BC, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP
|
||||
, FRVBF_INSN_BV, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO
|
||||
, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE
|
||||
, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE
|
||||
, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE
|
||||
, FRVBF_INSN_FBU, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR
|
||||
, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR
|
||||
, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR
|
||||
, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR
|
||||
, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR
|
||||
, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR
|
||||
, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR
|
||||
, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR
|
||||
, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR
|
||||
, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR
|
||||
, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR
|
||||
, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR
|
||||
, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR
|
||||
, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR
|
||||
, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR
|
||||
, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR
|
||||
, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL
|
||||
, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL
|
||||
, FRVBF_INSN_RETT, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO
|
||||
, FRVBF_INSN_TEQ, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT
|
||||
, FRVBF_INSN_TLT, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI
|
||||
, FRVBF_INSN_TC, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP
|
||||
, FRVBF_INSN_TV, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO
|
||||
, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE
|
||||
, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE
|
||||
, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE
|
||||
, FRVBF_INSN_FTU, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO
|
||||
, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT
|
||||
, FRVBF_INSN_TILT, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI
|
||||
, FRVBF_INSN_TIC, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP
|
||||
, FRVBF_INSN_TIV, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO
|
||||
, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE
|
||||
, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE
|
||||
, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE
|
||||
, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP
|
||||
, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR
|
||||
, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR
|
||||
, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO
|
||||
, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT
|
||||
, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI
|
||||
, FRVBF_INSN_CKC, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP
|
||||
, FRVBF_INSN_CKV, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO
|
||||
, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE
|
||||
, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE
|
||||
, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE
|
||||
, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO
|
||||
, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT
|
||||
, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI
|
||||
, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP
|
||||
, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO
|
||||
, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE
|
||||
, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE
|
||||
, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE
|
||||
, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL
|
||||
, FRVBF_INSN_ICI, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI
|
||||
, FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB
|
||||
, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL
|
||||
, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR
|
||||
, FRVBF_INSN_COP1, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR
|
||||
, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR
|
||||
, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI
|
||||
, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI
|
||||
, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI
|
||||
, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD
|
||||
, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD
|
||||
, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD
|
||||
, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS
|
||||
, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS
|
||||
, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS
|
||||
, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD
|
||||
, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS
|
||||
, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS
|
||||
, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS
|
||||
, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD
|
||||
, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS
|
||||
, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS
|
||||
, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS
|
||||
, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD
|
||||
, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS
|
||||
, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS
|
||||
, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS
|
||||
, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS
|
||||
, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH
|
||||
, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR
|
||||
, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT
|
||||
, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT
|
||||
, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS
|
||||
, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI
|
||||
, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI
|
||||
, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU
|
||||
, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS
|
||||
, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS
|
||||
, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS
|
||||
, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS
|
||||
, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS
|
||||
, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS
|
||||
, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS
|
||||
, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS
|
||||
, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS
|
||||
, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS
|
||||
, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS
|
||||
, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS
|
||||
, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU
|
||||
, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU
|
||||
, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU
|
||||
, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW
|
||||
, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH
|
||||
, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH
|
||||
, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE
|
||||
, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC
|
||||
, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1
|
||||
, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
|
||||
} FRVBF_INSN_TYPE;
|
||||
|
||||
/* Enum declaration for semantic formats in cpu family frvbf. */
|
||||
@ -245,8 +242,7 @@ typedef enum frvbf_sfmt_type {
|
||||
, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI, FRVBF_SFMT_LDDI
|
||||
, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI, FRVBF_SFMT_LDQI
|
||||
, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB, FRVBF_SFMT_STBF
|
||||
, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD
|
||||
, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF
|
||||
, FRVBF_SFMT_STC, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC
|
||||
, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU, FRVBF_SFMT_STDU
|
||||
, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB
|
||||
, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ
|
||||
|
||||
1116
sim/frv/model.c
1116
sim/frv/model.c
File diff suppressed because it is too large
Load Diff
238
sim/frv/sem.c
238
sim/frv/sem.c
@ -5630,138 +5630,6 @@ frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FL
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rstb: rstb$pack $GRk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cswap.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 1, 0);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rsth: rsth$pack $GRk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cswap.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 2, 0);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rst: rst$pack $GRk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cswap.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 4, 0);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rstbf: rstbf$pack $FRintk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cstbfu.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 1, 1);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rsthf: rsthf$pack $FRintk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rsthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cstbfu.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 2, 1);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rstf: rstf$pack $FRintk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cstbfu.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 4, 1);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* std: std$pack $GRdoublek,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
@ -5831,54 +5699,6 @@ frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk)
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rstd: rstd$pack $GRdoublek,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cstdu.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
{
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
|
||||
}
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 8, 0);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rstdf: rstdf$pack $FRdoublek,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cstdfu.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
{
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
|
||||
}
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 8, 1);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* stq: stq$pack $GRk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
@ -5948,54 +5768,6 @@ frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk));
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rstq: rstq$pack $GRk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_smulcc.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
{
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
|
||||
}
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 16, 0);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* rstqf: rstqf$pack $FRintk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
SEM_FN_NAME (frvbf,rstqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.sfmt_cstdfu.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
||||
{
|
||||
SI tmp_address;
|
||||
{
|
||||
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
|
||||
frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
|
||||
}
|
||||
frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 16, 1);
|
||||
}
|
||||
|
||||
return vpc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
/* stbu: stbu$pack $GRk,@($GRi,$GRj) */
|
||||
|
||||
static SEM_PC
|
||||
@ -28264,22 +28036,12 @@ static const struct sem_fn_desc sem_fns[] = {
|
||||
{ FRVBF_INSN_STHF, SEM_FN_NAME (frvbf,sthf) },
|
||||
{ FRVBF_INSN_STF, SEM_FN_NAME (frvbf,stf) },
|
||||
{ FRVBF_INSN_STC, SEM_FN_NAME (frvbf,stc) },
|
||||
{ FRVBF_INSN_RSTB, SEM_FN_NAME (frvbf,rstb) },
|
||||
{ FRVBF_INSN_RSTH, SEM_FN_NAME (frvbf,rsth) },
|
||||
{ FRVBF_INSN_RST, SEM_FN_NAME (frvbf,rst) },
|
||||
{ FRVBF_INSN_RSTBF, SEM_FN_NAME (frvbf,rstbf) },
|
||||
{ FRVBF_INSN_RSTHF, SEM_FN_NAME (frvbf,rsthf) },
|
||||
{ FRVBF_INSN_RSTF, SEM_FN_NAME (frvbf,rstf) },
|
||||
{ FRVBF_INSN_STD, SEM_FN_NAME (frvbf,std) },
|
||||
{ FRVBF_INSN_STDF, SEM_FN_NAME (frvbf,stdf) },
|
||||
{ FRVBF_INSN_STDC, SEM_FN_NAME (frvbf,stdc) },
|
||||
{ FRVBF_INSN_RSTD, SEM_FN_NAME (frvbf,rstd) },
|
||||
{ FRVBF_INSN_RSTDF, SEM_FN_NAME (frvbf,rstdf) },
|
||||
{ FRVBF_INSN_STQ, SEM_FN_NAME (frvbf,stq) },
|
||||
{ FRVBF_INSN_STQF, SEM_FN_NAME (frvbf,stqf) },
|
||||
{ FRVBF_INSN_STQC, SEM_FN_NAME (frvbf,stqc) },
|
||||
{ FRVBF_INSN_RSTQ, SEM_FN_NAME (frvbf,rstq) },
|
||||
{ FRVBF_INSN_RSTQF, SEM_FN_NAME (frvbf,rstqf) },
|
||||
{ FRVBF_INSN_STBU, SEM_FN_NAME (frvbf,stbu) },
|
||||
{ FRVBF_INSN_STHU, SEM_FN_NAME (frvbf,sthu) },
|
||||
{ FRVBF_INSN_STU, SEM_FN_NAME (frvbf,stu) },
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
|
||||
* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
|
||||
|
||||
2004-01-26 Chris Demetriou <cgd@broadcom.com>
|
||||
|
||||
* sim/mips: New directory. Tests for the MIPS simulator.
|
||||
|
||||
@ -1,107 +0,0 @@
|
||||
# frv testcase for rst $GRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global rst
|
||||
rst:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr10
|
||||
set_gr_gr sp,gr24
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_gr_gr gr24,gr27
|
||||
inc_gr_immed -4,gr27
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_gr_gr gr27,gr26
|
||||
inc_gr_immed -4,gr26
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_gr_gr gr26,gr25
|
||||
inc_gr_immed -4,gr25
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_gr_immed 0,gr7
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
rst gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
nldi @(sp,0),gr20
|
||||
test_spr_gr neear0,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
set_gr_immed -4,gr7
|
||||
rst gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr24
|
||||
test_mem_limmed 0xffff,0xffff,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -4,gr10
|
||||
nldfi @(sp,-4),fr20
|
||||
test_spr_gr neear1,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 4,gr7
|
||||
rst gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
inc_gr_immed -4,gr10
|
||||
nldi @(sp,-4),gr20
|
||||
test_spr_gr neear2,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 0,gr7
|
||||
rst gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_gr_limmed 0xffff,0xffff,gr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
inc_gr_immed -4,gr10
|
||||
nldfi @(sp,-4),fr20
|
||||
test_spr_gr neear3,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
set_gr_immed -4,gr7
|
||||
rst gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0xffff,0xffff,gr25
|
||||
test_fr_limmed 0xffff,0xffff,fr20
|
||||
|
||||
pass
|
||||
@ -1,72 +0,0 @@
|
||||
# frv testcase for rstb $GRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr21
|
||||
set_gr_gr gr21,gr22
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_gr_immed 0,gr7
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
rstb gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xff22,0x2222,sp
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
inc_gr_immed 3,gr22
|
||||
nldubi @(sp,3),gr20
|
||||
test_spr_gr neear0,gr22
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
inc_gr_immed 1,gr7
|
||||
rstb gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x22ff,0x2222,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -1,gr22
|
||||
nldbfi @(sp,2),fr20
|
||||
test_spr_gr neear1,gr22
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
inc_gr_immed 4,sp
|
||||
set_gr_immed -1,gr7
|
||||
rstb gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x22ff,gr21
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
inc_gr_immed -1,gr22
|
||||
nldubi @(sp,-3),gr20
|
||||
test_spr_gr neear2,gr22
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 1,gr7
|
||||
rstb gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x22ff,0x2222,gr21
|
||||
test_gr_limmed 0x0000,0x00ff,gr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
inc_gr_immed -1,gr22
|
||||
nldbfi @(sp,0),fr20
|
||||
test_spr_gr neear3,gr22
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
set_gr_immed 0,gr7
|
||||
rstb gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xff22,0x2222,gr21
|
||||
test_fr_limmed 0x0000,0x00ff,fr20
|
||||
|
||||
pass
|
||||
@ -1,76 +0,0 @@
|
||||
# frv testcase for rstbf $FRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr21
|
||||
set_gr_gr gr21,gr22
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_gr_immed 0,gr7
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
rstbf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xff22,0x2222,sp
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
inc_gr_immed 1,gr22
|
||||
nldubi @(sp,1),gr20
|
||||
test_spr_gr neear0,gr22
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
inc_gr_immed 2,gr7
|
||||
rstbf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0xff22,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -1,gr22
|
||||
nldbfi @(sp,0),fr20
|
||||
test_spr_gr neear1,gr22
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
inc_gr_immed 4,sp
|
||||
set_gr_immed -1,gr7
|
||||
rstbf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x22ff,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 1,gr7
|
||||
rstbf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x22ff,0x2222,gr21
|
||||
test_gr_limmed 0x0000,0x00ff,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_mem_limmed 0x2222,0x2222,gr21
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
set_gr_immed 0,gr7
|
||||
rstbf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xff22,0x2222,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x0000,0x00ff,fr20
|
||||
|
||||
pass
|
||||
@ -1,171 +0,0 @@
|
||||
# frv testcase for rstd $GRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr20
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_gr_gr gr20,gr27
|
||||
inc_gr_immed -4,gr27
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_gr_gr gr27,gr26
|
||||
inc_gr_immed -4,gr26
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_gr_gr gr26,gr25
|
||||
inc_gr_immed -4,gr25
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_gr gr25,gr24
|
||||
inc_gr_immed -4,gr24
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_gr_gr gr24,gr23
|
||||
inc_gr_immed -4,gr23
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_gr_gr gr23,gr22
|
||||
inc_gr_immed -4,gr22
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_gr_gr gr22,gr21
|
||||
inc_gr_immed -4,gr21
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 0,gr7
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
rstd gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr20
|
||||
test_mem_limmed 0xeeee,0xeeee,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
set_gr_gr sp,gr10
|
||||
nlddi @(sp,0),gr40
|
||||
test_spr_gr neear0,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_immed -8,gr7
|
||||
rstd gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr20
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0xeeee,0xeeee,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -8,gr10
|
||||
nlddfi @(sp,-8),fr40
|
||||
test_spr_gr neear1,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
inc_gr_immed -8,sp
|
||||
set_gr_immed 8,gr7
|
||||
rstd gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr20
|
||||
test_mem_limmed 0xeeee,0xeeee,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
inc_gr_immed -8,gr10
|
||||
nlddi @(sp,-8),gr40
|
||||
test_spr_gr neear2,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
inc_gr_immed -8,sp
|
||||
set_gr_immed 0,gr7
|
||||
rstd gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr20
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0xffff,0xffff,gr24
|
||||
test_mem_limmed 0xeeee,0xeeee,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_gr_limmed 0xffff,0xffff,gr41
|
||||
test_gr_limmed 0xeeee,0xeeee,gr40
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
inc_gr_immed -8,gr10
|
||||
nlddfi @(sp,-8),fr40
|
||||
test_spr_gr neear3,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_gr_immed -8,gr7
|
||||
rstd gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr20
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0xffff,0xffff,gr22
|
||||
test_mem_limmed 0xeeee,0xeeee,gr21
|
||||
test_fr_limmed 0xffff,0xffff,fr41
|
||||
test_fr_limmed 0xeeee,0xeeee,fr40
|
||||
|
||||
pass
|
||||
@ -1,186 +0,0 @@
|
||||
# frv testcase for rstdf $FRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr20
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_gr_gr gr20,gr27
|
||||
inc_gr_immed -4,gr27
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_gr_gr gr27,gr26
|
||||
inc_gr_immed -4,gr26
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_gr_gr gr26,gr25
|
||||
inc_gr_immed -4,gr25
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_gr gr25,gr24
|
||||
inc_gr_immed -4,gr24
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_gr_gr gr24,gr23
|
||||
inc_gr_immed -4,gr23
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_gr_gr gr23,gr22
|
||||
inc_gr_immed -4,gr22
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_gr_gr gr22,gr21
|
||||
inc_gr_immed -4,gr21
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 0,gr7
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
rstdf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr20
|
||||
test_mem_limmed 0xeeee,0xeeee,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
set_gr_gr sp,gr10
|
||||
inc_gr_immed -16,gr10
|
||||
nlddi @(sp,-16),gr40
|
||||
test_spr_gr neear0,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_gr_immed -8,gr7
|
||||
rstdf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr20
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0xeeee,0xeeee,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -8,gr10
|
||||
nlddfi @(sp,-24),fr40
|
||||
test_spr_gr neear1,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
inc_gr_immed -8,sp
|
||||
set_gr_immed 8,gr7
|
||||
rstdf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr20
|
||||
test_mem_limmed 0xeeee,0xeeee,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
inc_gr_immed -8,sp
|
||||
set_gr_immed 0,gr7
|
||||
rstdf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr20
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0xffff,0xffff,gr24
|
||||
test_mem_limmed 0xeeee,0xeeee,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_gr_limmed 0xffff,0xffff,gr41
|
||||
test_gr_limmed 0xeeee,0xeeee,gr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
set_mem_limmed 0x2222,0x2222,gr20
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_gr_immed -8,gr7
|
||||
rstdf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr20
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0xffff,0xffff,gr22
|
||||
test_mem_limmed 0xeeee,0xeeee,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_fr_limmed 0xffff,0xffff,fr41
|
||||
test_fr_limmed 0xeeee,0xeeee,fr40
|
||||
|
||||
pass
|
||||
@ -1,112 +0,0 @@
|
||||
# frv testcase for rstf $FRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr10
|
||||
set_gr_gr sp,gr24
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_gr_gr gr24,gr27
|
||||
inc_gr_immed -4,gr27
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_gr_gr gr27,gr26
|
||||
inc_gr_immed -4,gr26
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_gr_gr gr26,gr25
|
||||
inc_gr_immed -4,gr25
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_gr_immed 0,gr7
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
rstf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
inc_gr_immed -8,gr10
|
||||
nldi @(sp,-8),gr20
|
||||
test_spr_gr neear0,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
set_gr_immed -4,gr7
|
||||
rstf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr24
|
||||
test_mem_limmed 0xffff,0xffff,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -4,gr10
|
||||
nldfi @(sp,-12),fr20
|
||||
test_spr_gr neear1,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 4,gr7
|
||||
rstf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0xffff,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed 0,gr7
|
||||
rstf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_gr_limmed 0xffff,0xffff,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
set_mem_limmed 0x2222,0x2222,gr24
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
set_gr_immed -4,gr7
|
||||
rstf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr24
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0xffff,0xffff,gr25
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0xffff,0xffff,fr20
|
||||
|
||||
pass
|
||||
@ -1,83 +0,0 @@
|
||||
# frv testcase for rsth $GRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr22
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_gr_gr gr22,gr21
|
||||
inc_gr_immed -4,gr21
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_gr gr22,gr23
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_gr_immed 0,gr7
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
rsth gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0x2222,gr22
|
||||
test_mem_limmed 0x3333,0x3333,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
nlduhi @(sp,0),gr20
|
||||
test_spr_gr neear0,gr23
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
set_gr_immed 2,gr7
|
||||
rsth gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0xffff,gr22
|
||||
test_mem_limmed 0x3333,0x3333,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed 2,gr23
|
||||
nldhfi @(sp,2),fr20
|
||||
test_spr_gr neear1,gr23
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
inc_gr_immed 4,sp
|
||||
set_gr_immed -4,gr7
|
||||
rsth gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0x2222,gr22
|
||||
test_mem_limmed 0x3333,0x3333,gr21
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
inc_gr_immed -4,gr23
|
||||
nlduhi @(sp,-6),gr20
|
||||
test_spr_gr neear2,gr23
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed -2,gr7
|
||||
rsth gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr22
|
||||
test_mem_limmed 0x3333,0xffff,gr21
|
||||
test_gr_limmed 0x0000,0xffff,gr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
inc_gr_immed -2,gr23
|
||||
nldhfi @(sp,-4),fr20
|
||||
test_spr_gr neear3,gr23
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_gr_limmed 0xffff,0xffff,gr8
|
||||
set_gr_immed -4,gr7
|
||||
rsth gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr22
|
||||
test_mem_limmed 0xffff,0x3333,gr21
|
||||
test_fr_limmed 0x0000,0xffff,fr20
|
||||
|
||||
pass
|
||||
@ -1,87 +0,0 @@
|
||||
# frv testcase for rsthf $FRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr22
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_gr_gr gr22,gr21
|
||||
inc_gr_immed -4,gr21
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_gr gr22,gr23
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_gr_immed 0,gr7
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
rsthf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0x2222,gr22
|
||||
test_mem_limmed 0x3333,0x3333,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
inc_gr_immed -2,gr23
|
||||
nlduhi @(sp,-2),gr20
|
||||
test_spr_gr neear0,gr23
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
set_gr_immed 2,gr7
|
||||
rsthf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0xffff,gr22
|
||||
test_mem_limmed 0x3333,0x3333,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -2,gr23
|
||||
nldhfi @(sp,-4),fr20
|
||||
test_spr_gr neear1,gr23
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
inc_gr_immed 4,sp
|
||||
set_gr_immed -4,gr7
|
||||
rsthf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xffff,0x2222,gr22
|
||||
test_mem_limmed 0x3333,0x3333,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
inc_gr_immed -4,sp
|
||||
set_gr_immed -2,gr7
|
||||
rsthf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr22
|
||||
test_mem_limmed 0x3333,0xffff,gr21
|
||||
test_gr_limmed 0x0000,0xffff,gr20
|
||||
test_fr_limmed 0x1111,0x1111,fr20
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
set_mem_limmed 0x2222,0x2222,gr22
|
||||
set_mem_limmed 0x3333,0x3333,gr21
|
||||
set_gr_limmed 0x1111,0x1111,gr20
|
||||
set_fr_iimmed 0x1111,0x1111,fr20
|
||||
set_fr_iimmed 0xffff,0xffff,fr8
|
||||
set_gr_immed -4,gr7
|
||||
rsthf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr22
|
||||
test_mem_limmed 0xffff,0x3333,gr21
|
||||
test_gr_limmed 0x1111,0x1111,gr20
|
||||
test_fr_limmed 0x0000,0xffff,fr20
|
||||
|
||||
pass
|
||||
@ -1,297 +0,0 @@
|
||||
# frv testcase for rstq $GRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr6
|
||||
set_mem_limmed 0x2222,0x2222,gr6
|
||||
set_gr_gr gr6,gr27
|
||||
inc_gr_immed -4,gr27
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_gr_gr gr27,gr26
|
||||
inc_gr_immed -4,gr26
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_gr_gr gr26,gr25
|
||||
inc_gr_immed -4,gr25
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_gr gr25,gr24
|
||||
inc_gr_immed -4,gr24
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_gr_gr gr24,gr23
|
||||
inc_gr_immed -4,gr23
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_gr_gr gr23,gr22
|
||||
inc_gr_immed -4,gr22
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_gr_gr gr22,gr21
|
||||
inc_gr_immed -4,gr21
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_gr gr21,gr20
|
||||
inc_gr_immed -4,gr20
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_gr_gr gr20,gr19
|
||||
inc_gr_immed -4,gr19
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_gr_gr gr19,gr18
|
||||
inc_gr_immed -4,gr18
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_gr_gr gr18,gr17
|
||||
inc_gr_immed -4,gr17
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_gr_gr gr17,gr16
|
||||
inc_gr_immed -4,gr16
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_gr_gr gr16,gr15
|
||||
inc_gr_immed -4,gr15
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_gr_gr gr15,gr14
|
||||
inc_gr_immed -4,gr14
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_gr_gr gr14,gr13
|
||||
inc_gr_immed -4,gr13
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
inc_gr_immed -12,sp
|
||||
set_gr_immed 0,gr7
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_gr_limmed 0xcccc,0xcccc,gr10
|
||||
set_gr_limmed 0xdddd,0xdddd,gr11
|
||||
rstq gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xdddd,0xdddd,gr6
|
||||
test_mem_limmed 0xcccc,0xcccc,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0xeeee,0xeeee,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_gr_limmed 0x1111,0x1111,gr42
|
||||
test_gr_limmed 0x1111,0x1111,gr43
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
set_gr_gr sp,gr12
|
||||
nldq @(sp,gr0),gr40
|
||||
test_spr_gr neear0,gr12
|
||||
set_mem_limmed 0x2222,0x2222,gr6
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_gr_limmed 0xcccc,0xcccc,gr10
|
||||
set_gr_limmed 0xdddd,0xdddd,gr11
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
set_gr_immed -16,gr7
|
||||
rstq gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr6
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0xdddd,0xdddd,gr24
|
||||
test_mem_limmed 0xcccc,0xcccc,gr23
|
||||
test_mem_limmed 0xffff,0xffff,gr22
|
||||
test_mem_limmed 0xeeee,0xeeee,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_gr_limmed 0x1111,0x1111,gr42
|
||||
test_gr_limmed 0x1111,0x1111,gr43
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -16,gr12
|
||||
nlddfi @(sp,-16),fr40
|
||||
test_spr_gr neear1,gr12
|
||||
set_mem_limmed 0x2222,0x2222,gr6
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_gr_limmed 0xcccc,0xcccc,gr10
|
||||
set_gr_limmed 0xdddd,0xdddd,gr11
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr42
|
||||
set_fr_iimmed 0x1111,0x1111,fr43
|
||||
inc_gr_immed -16,sp
|
||||
set_gr_immed 16,gr7
|
||||
rstq gr8,@(sp,gr7)
|
||||
test_mem_limmed 0xdddd,0xdddd,gr6
|
||||
test_mem_limmed 0xcccc,0xcccc,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0xeeee,0xeeee,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
test_fr_limmed 0x1111,0x1111,fr42
|
||||
test_fr_limmed 0x1111,0x1111,fr43
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
inc_gr_immed -16,gr12
|
||||
nlddi @(sp,-16),gr40
|
||||
test_spr_gr neear2,gr12
|
||||
set_mem_limmed 0x2222,0x2222,gr6
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_gr_limmed 0xcccc,0xcccc,gr10
|
||||
set_gr_limmed 0xdddd,0xdddd,gr11
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
inc_gr_immed -16,sp
|
||||
set_gr_immed 0,gr7
|
||||
rstq gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr6
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xdddd,0xdddd,gr20
|
||||
test_mem_limmed 0xcccc,0xcccc,gr19
|
||||
test_mem_limmed 0xffff,0xffff,gr18
|
||||
test_mem_limmed 0xeeee,0xeeee,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_gr_limmed 0xeeee,0xeeee,gr40
|
||||
test_gr_limmed 0xffff,0xffff,gr41
|
||||
test_gr_limmed 0xcccc,0xcccc,gr42
|
||||
test_gr_limmed 0xdddd,0xdddd,gr43
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
inc_gr_immed -16,gr12
|
||||
nlddfi @(sp,-16),fr40
|
||||
test_spr_gr neear3,gr12
|
||||
set_mem_limmed 0x2222,0x2222,gr6
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_gr_limmed 0xeeee,0xeeee,gr8
|
||||
set_gr_limmed 0xffff,0xffff,gr9
|
||||
set_gr_limmed 0xcccc,0xcccc,gr10
|
||||
set_gr_limmed 0xdddd,0xdddd,gr11
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr42
|
||||
set_fr_iimmed 0x1111,0x1111,fr43
|
||||
set_gr_immed -16,gr7
|
||||
rstq gr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr6
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xdddd,0xdddd,gr16
|
||||
test_mem_limmed 0xcccc,0xcccc,gr15
|
||||
test_mem_limmed 0xffff,0xffff,gr14
|
||||
test_mem_limmed 0xeeee,0xeeee,gr13
|
||||
test_fr_limmed 0xeeee,0xeeee,fr40
|
||||
test_fr_limmed 0xffff,0xffff,fr41
|
||||
test_fr_limmed 0xcccc,0xcccc,fr42
|
||||
test_fr_limmed 0xdddd,0xdddd,fr43
|
||||
|
||||
pass
|
||||
@ -1,333 +0,0 @@
|
||||
# frv testcase for rstqf $FRk,@($GRi,$GRj)
|
||||
# mach: frv
|
||||
# as(frv): -mcpu=frv
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
|
||||
.global add
|
||||
add:
|
||||
; No nesr's active
|
||||
set_gr_gr sp,gr12
|
||||
set_mem_limmed 0x2222,0x2222,gr12
|
||||
set_gr_gr gr12,gr27
|
||||
inc_gr_immed -4,gr27
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_gr_gr gr27,gr26
|
||||
inc_gr_immed -4,gr26
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_gr_gr gr26,gr25
|
||||
inc_gr_immed -4,gr25
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_gr_gr gr25,gr24
|
||||
inc_gr_immed -4,gr24
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_gr_gr gr24,gr23
|
||||
inc_gr_immed -4,gr23
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_gr_gr gr23,gr22
|
||||
inc_gr_immed -4,gr22
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_gr_gr gr22,gr21
|
||||
inc_gr_immed -4,gr21
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_gr_gr gr21,gr20
|
||||
inc_gr_immed -4,gr20
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_gr_gr gr20,gr19
|
||||
inc_gr_immed -4,gr19
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_gr_gr gr19,gr18
|
||||
inc_gr_immed -4,gr18
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_gr_gr gr18,gr17
|
||||
inc_gr_immed -4,gr17
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_gr_gr gr17,gr16
|
||||
inc_gr_immed -4,gr16
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_gr_gr gr16,gr15
|
||||
inc_gr_immed -4,gr15
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_gr_gr gr15,gr14
|
||||
inc_gr_immed -4,gr14
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_gr_gr gr14,gr13
|
||||
inc_gr_immed -4,gr13
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr42
|
||||
set_fr_iimmed 0x1111,0x1111,fr43
|
||||
inc_gr_immed -12,sp
|
||||
set_gr_immed 0,gr7
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_fr_iimmed 0xcccc,0xcccc,fr10
|
||||
set_fr_iimmed 0xdddd,0xdddd,fr11
|
||||
rstqf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xdddd,0xdddd,gr12
|
||||
test_mem_limmed 0xcccc,0xcccc,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0xeeee,0xeeee,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_gr_limmed 0x1111,0x1111,gr42
|
||||
test_gr_limmed 0x1111,0x1111,gr43
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
test_fr_limmed 0x1111,0x1111,fr42
|
||||
test_fr_limmed 0x1111,0x1111,fr43
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for gr
|
||||
set_gr_gr sp,gr10
|
||||
inc_gr_immed -32,gr10
|
||||
set_gr_immed -32,gr9
|
||||
nldq @(sp,gr9),gr40
|
||||
test_spr_gr neear0,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr12
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_fr_iimmed 0xcccc,0xcccc,fr10
|
||||
set_fr_iimmed 0xdddd,0xdddd,fr11
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr42
|
||||
set_fr_iimmed 0x1111,0x1111,fr43
|
||||
set_gr_immed -16,gr7
|
||||
rstqf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr12
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0xdddd,0xdddd,gr24
|
||||
test_mem_limmed 0xcccc,0xcccc,gr23
|
||||
test_mem_limmed 0xffff,0xffff,gr22
|
||||
test_mem_limmed 0xeeee,0xeeee,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_gr_limmed 0x1111,0x1111,gr42
|
||||
test_gr_limmed 0x1111,0x1111,gr43
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
test_fr_limmed 0x1111,0x1111,fr42
|
||||
test_fr_limmed 0x1111,0x1111,fr43
|
||||
|
||||
; 1 nesr active with the incorrect address in neear for fr
|
||||
inc_gr_immed -16,gr10
|
||||
nlddfi @(sp,-48),fr40
|
||||
test_spr_gr neear1,gr10
|
||||
set_mem_limmed 0x2222,0x2222,gr12
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_fr_iimmed 0xcccc,0xcccc,fr10
|
||||
set_fr_iimmed 0xdddd,0xdddd,fr11
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr42
|
||||
set_fr_iimmed 0x1111,0x1111,fr43
|
||||
inc_gr_immed -16,sp
|
||||
set_gr_immed 16,gr7
|
||||
rstqf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0xdddd,0xdddd,gr12
|
||||
test_mem_limmed 0xcccc,0xcccc,gr27
|
||||
test_mem_limmed 0xffff,0xffff,gr26
|
||||
test_mem_limmed 0xeeee,0xeeee,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_gr_limmed 0x1111,0x1111,gr42
|
||||
test_gr_limmed 0x1111,0x1111,gr43
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
test_fr_limmed 0x1111,0x1111,fr42
|
||||
test_fr_limmed 0x1111,0x1111,fr43
|
||||
|
||||
; 1 nesr active with the correct address in neear for gr
|
||||
set_mem_limmed 0x2222,0x2222,gr12
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_fr_iimmed 0xcccc,0xcccc,fr10
|
||||
set_fr_iimmed 0xdddd,0xdddd,fr11
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr42
|
||||
set_fr_iimmed 0x1111,0x1111,fr43
|
||||
inc_gr_immed -16,sp
|
||||
set_gr_immed 0,gr7
|
||||
rstqf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr12
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xdddd,0xdddd,gr20
|
||||
test_mem_limmed 0xcccc,0xcccc,gr19
|
||||
test_mem_limmed 0xffff,0xffff,gr18
|
||||
test_mem_limmed 0xeeee,0xeeee,gr17
|
||||
test_mem_limmed 0xeeee,0xeeee,gr16
|
||||
test_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
test_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
test_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
test_gr_limmed 0xeeee,0xeeee,gr40
|
||||
test_gr_limmed 0xffff,0xffff,gr41
|
||||
test_gr_limmed 0xcccc,0xcccc,gr42
|
||||
test_gr_limmed 0xdddd,0xdddd,gr43
|
||||
test_fr_limmed 0x1111,0x1111,fr40
|
||||
test_fr_limmed 0x1111,0x1111,fr41
|
||||
test_fr_limmed 0x1111,0x1111,fr42
|
||||
test_fr_limmed 0x1111,0x1111,fr43
|
||||
|
||||
; 1 nesr active with the correct address in neear for fr
|
||||
set_mem_limmed 0x2222,0x2222,gr12
|
||||
set_mem_limmed 0x3333,0x3333,gr27
|
||||
set_mem_limmed 0x4444,0x4444,gr26
|
||||
set_mem_limmed 0x5555,0x5555,gr25
|
||||
set_mem_limmed 0x6666,0x6666,gr24
|
||||
set_mem_limmed 0x7777,0x7777,gr23
|
||||
set_mem_limmed 0x8888,0x8888,gr22
|
||||
set_mem_limmed 0x9999,0x9999,gr21
|
||||
set_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
set_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
set_mem_limmed 0xcccc,0xcccc,gr18
|
||||
set_mem_limmed 0xdddd,0xdddd,gr17
|
||||
set_mem_limmed 0xeeee,0xeeee,gr16
|
||||
set_mem_limmed 0xf0f0,0xf0f0,gr15
|
||||
set_mem_limmed 0xf1f1,0xf1f1,gr14
|
||||
set_mem_limmed 0xf2f2,0xf2f2,gr13
|
||||
set_fr_iimmed 0xeeee,0xeeee,fr8
|
||||
set_fr_iimmed 0xffff,0xffff,fr9
|
||||
set_fr_iimmed 0xcccc,0xcccc,fr10
|
||||
set_fr_iimmed 0xdddd,0xdddd,fr11
|
||||
set_gr_limmed 0x1111,0x1111,gr40
|
||||
set_gr_limmed 0x1111,0x1111,gr41
|
||||
set_gr_limmed 0x1111,0x1111,gr42
|
||||
set_gr_limmed 0x1111,0x1111,gr43
|
||||
set_fr_iimmed 0x1111,0x1111,fr40
|
||||
set_fr_iimmed 0x1111,0x1111,fr41
|
||||
set_fr_iimmed 0x1111,0x1111,fr42
|
||||
set_fr_iimmed 0x1111,0x1111,fr43
|
||||
set_gr_immed -16,gr7
|
||||
rstqf fr8,@(sp,gr7)
|
||||
test_mem_limmed 0x2222,0x2222,gr12
|
||||
test_mem_limmed 0x3333,0x3333,gr27
|
||||
test_mem_limmed 0x4444,0x4444,gr26
|
||||
test_mem_limmed 0x5555,0x5555,gr25
|
||||
test_mem_limmed 0x6666,0x6666,gr24
|
||||
test_mem_limmed 0x7777,0x7777,gr23
|
||||
test_mem_limmed 0x8888,0x8888,gr22
|
||||
test_mem_limmed 0x9999,0x9999,gr21
|
||||
test_mem_limmed 0xaaaa,0xaaaa,gr20
|
||||
test_mem_limmed 0xbbbb,0xbbbb,gr19
|
||||
test_mem_limmed 0xcccc,0xcccc,gr18
|
||||
test_mem_limmed 0xdddd,0xdddd,gr17
|
||||
test_mem_limmed 0xdddd,0xdddd,gr16
|
||||
test_mem_limmed 0xcccc,0xcccc,gr15
|
||||
test_mem_limmed 0xffff,0xffff,gr14
|
||||
test_mem_limmed 0xeeee,0xeeee,gr13
|
||||
test_gr_limmed 0x1111,0x1111,gr40
|
||||
test_gr_limmed 0x1111,0x1111,gr41
|
||||
test_gr_limmed 0x1111,0x1111,gr42
|
||||
test_gr_limmed 0x1111,0x1111,gr43
|
||||
test_fr_limmed 0xeeee,0xeeee,fr40
|
||||
test_fr_limmed 0xffff,0xffff,fr41
|
||||
test_fr_limmed 0xcccc,0xcccc,fr42
|
||||
test_fr_limmed 0xdddd,0xdddd,fr43
|
||||
|
||||
pass
|
||||
Loading…
Reference in New Issue
Block a user