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* run.c (main): Add -h flag to enable h8/300h emulation.
* compile.c: Rename Hmode to HMODE (consistency with gdb). (set_h8300h): New function. (sim_resume): Add support for extu,exts insns. (sim_resume): Fix logical right shifting. (sim_resume, label alu32): Fix setting of carry flag.
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@ -1,3 +1,12 @@
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Fri Jul 9 14:36:48 1993 Doug Evans (dje@canuck.cygnus.com)
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* run.c (main): Add -h flag to enable h8/300h emulation.
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* compile.c: Rename Hmode to HMODE (consistency with gdb).
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(set_h8300h): New function.
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(sim_resume): Add support for extu,exts insns.
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(sim_resume): Fix logical right shifting.
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(sim_resume, label alu32): Fix setting of carry flag.
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Sun Jul 4 00:35:41 1993 Doug Evans (dje@canuck.cygnus.com)
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* compile.c (sim_csize): Initialize cpu.cache.
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@ -15,7 +15,6 @@
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* CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
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* SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#include <signal.h>
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@ -29,7 +28,7 @@ int debug;
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#define X(op, size) op*4+size
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#define SP (Hmode ? SL:SW)
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#define SP (HMODE ? SL:SW)
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#define SB 0
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#define SW 1
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#define SL 2
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@ -74,7 +73,7 @@ int debug;
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static cpu_state_type cpu;
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int Hmode;
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int HMODE = 1;
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static int
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@ -95,7 +94,6 @@ now_persec ()
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static int
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bitfrom (x)
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{
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switch (x & SIZE)
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{
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case L_8:
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@ -105,9 +103,8 @@ bitfrom (x)
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case L_32:
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return SL;
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case L_P:
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return Hmode ? SL : SW;
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return HMODE ? SL : SW;
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}
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}
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static
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@ -497,7 +494,7 @@ static unsigned int *lreg[18];
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#define GET_MEMORY_B(x) (cpu.memory[x])
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int
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fetch (arg, n)
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fetch (arg, n)
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ea_type *arg;
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{
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int rn = arg->reg;
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@ -608,6 +605,7 @@ int n;
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case X (OP_DEC, SL):
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t = (GET_L_REG(rn) -4 ) & cpu.mask;
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SET_L_REG (rn, t);
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SET_MEMORY_L (t,n);
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break;
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@ -1058,13 +1056,13 @@ case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how;
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OSHIFTS(O_NOT, rd = ~rd);
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OSHIFTS(O_SHLL, c = rd & hm; rd<<=1);
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OSHIFTS(O_SHLR, c = rd & 1; rd>>=1);
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OSHIFTS(O_SHLR, c = rd & 1; rd = (unsigned int) rd >> 1);
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OSHIFTS(O_SHAL, c = rd & hm; rd<<=1);
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OSHIFTS(O_SHAR, t = rd & hm; c = rd&1;rd>>=1;rd|=t;);
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OSHIFTS(O_ROTL, c = rd & hm; rd <<=1; rd|= C);
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OSHIFTS(O_ROTR, c = rd &1 ; rd >>=1; if (c) rd|= hm;);
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OSHIFTS(O_ROTR, c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm;);
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OSHIFTS(O_ROTXL,t = rd & hm; rd<<=1; rd|=C; c=t;);
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OSHIFTS(O_ROTXR,t = rd & 1; rd>>=1; if (C) rd|=hm; c=t;);
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OSHIFTS(O_ROTXR,t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd|=hm; c=t;);
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case O(O_JMP, SB):
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{
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@ -1080,7 +1078,7 @@ case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how;
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call:
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tmp = cpu.regs[7];
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if (Hmode)
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if (HMODE)
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{
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tmp -= 4;
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SET_MEMORY_L (tmp, code->next_pc);
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@ -1105,7 +1103,7 @@ case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how;
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tmp = cpu.regs[7];
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if (Hmode)
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if (HMODE)
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{
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pc = GET_MEMORY_L (tmp);
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tmp += 4;
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@ -1269,9 +1267,27 @@ case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how;
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SET_L_REG(code->dst.reg, (rd & 0xffff) | (tmp << 16));
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goto next;
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}
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case O (O_EXTS, SW):
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rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
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ea = rd & 0x80 ? -256 : 0;
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res = rd + ea;
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goto log16;
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case O (O_EXTS, SL):
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rd = GET_W_REG (code->src.reg) & 0xffff;
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ea = rd & 0x8000 ? -65536 : 0;
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res = rd + ea;
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goto log32;
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case O (O_EXTU, SW):
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rd = GET_B_REG (code->src.reg + 8) & 0xff;
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ea = 0;
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res = rd + ea;
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goto log16;
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case O (O_EXTU, SL):
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rd = GET_W_REG (code->src.reg) & 0xffff;
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ea = 0;
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res = rd + ea;
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goto log32;
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default:
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cpu.exception = 123;
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goto end;
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@ -1333,7 +1349,6 @@ case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how;
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SET_W_REG(code->src.reg, rd);
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goto next;
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shift32:
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/* Set flags after an 32 bit shift op, carry set in insn */
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n = (rd & 0x80000000);
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@ -1342,7 +1357,6 @@ case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how;
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SET_L_REG(code->src.reg, rd);
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goto next;
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log32:
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store (&code->dst, res);
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just_flags_log32:
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@ -1395,7 +1409,19 @@ case O(name, SL):{ int t;int hm = 0x80000000; rd = GET_L_REG(code->src.reg);how;
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nz = res & 0xffffffff;
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v = ((ea & 0x80000000) == (rd & 0x80000000))
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&& ((ea & 0x80000000) != (res & 0x80000000));
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c = (res < rd) || (res < ea);
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switch (code->opcode / 4)
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{
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case O_ADD:
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c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
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break;
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case O_SUB:
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case O_CMP:
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c = (unsigned) rd < (unsigned) -ea;
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break;
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case O_NEG:
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c = res != 0;
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break;
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}
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goto next;
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next:;
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@ -1559,7 +1585,7 @@ sim_fetch_register (rn, buf)
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break;
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}
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if (Hmode || longreg)
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if (HMODE || longreg)
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{
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buf[0] = v >> 24;
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buf[1] = v >> 16;
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@ -1635,3 +1661,8 @@ sim_info (verbose)
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#endif
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}
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void
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set_h8300h ()
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{
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HMODE = 1;
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}
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sim_csize(atoi(av[i+1]));
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i++;
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}
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else if (strcmp(av[i],"-h") == 0)
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set_h8300h ();
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else
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name = av[i];
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}
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