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2005-05-16 H.J. Lu <hongjiu.lu@intel.com>
PR 834 * elfxx-ia64.c (elfNN_ia64_relax_br): New. (elfNN_ia64_relax_section): Use it.
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H.J. Lu
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@ -1,3 +1,9 @@
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2005-05-16 H.J. Lu <hongjiu.lu@intel.com>
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PR 834
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* elfxx-ia64.c (elfNN_ia64_relax_br): New.
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(elfNN_ia64_relax_section): Use it.
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2005-05-14 Mark Kettenis <kettenis@gnu.org>
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* elflink.c (bfd_elf_size_dynamic_sections): Use lbasename instead
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145
bfd/elfxx-ia64.c
145
bfd/elfxx-ia64.c
@ -681,6 +681,141 @@ bfd_elfNN_ia64_after_parse (int itanium)
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oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl);
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}
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#define BTYPE_SHIFT 6
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#define Y_SHIFT 26
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#define X6_SHIFT 27
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#define X4_SHIFT 27
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#define X3_SHIFT 33
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#define X2_SHIFT 31
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#define X_SHIFT 33
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#define OPCODE_SHIFT 37
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#define OPCODE_BITS (0xfLL << OPCODE_SHIFT)
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#define X6_BITS (0x3fLL << X6_SHIFT)
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#define X4_BITS (0xfLL << X4_SHIFT)
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#define X3_BITS (0x7LL << X3_SHIFT)
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#define X2_BITS (0x3LL << X2_SHIFT)
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#define X_BITS (0x1LL << X_SHIFT)
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#define Y_BITS (0x1LL << Y_SHIFT)
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#define BTYPE_BITS (0x7LL << BTYPE_SHIFT)
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#define PREDICATE_BITS (0x3fLL)
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#define IS_NOP_B(i) \
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(((i) & (OPCODE_BITS | X6_BITS)) == (2LL << OPCODE_SHIFT))
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#define IS_NOP_F(i) \
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(((i) & (OPCODE_BITS | X_BITS | X6_BITS | Y_BITS)) \
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== (0x1LL << X6_SHIFT))
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#define IS_NOP_I(i) \
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(((i) & (OPCODE_BITS | X3_BITS | X6_BITS | Y_BITS)) \
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== (0x1LL << X6_SHIFT))
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#define IS_NOP_M(i) \
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(((i) & (OPCODE_BITS | X3_BITS | X2_BITS | X4_BITS | Y_BITS)) \
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== (0x1LL << X4_SHIFT))
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#define IS_BR_COND(i) \
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(((i) & (OPCODE_BITS | BTYPE_BITS)) == (0x4LL << OPCODE_SHIFT))
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#define IS_BR_CALL(i) \
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(((i) & OPCODE_BITS) == (0x5LL << OPCODE_SHIFT))
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static bfd_boolean
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elfNN_ia64_relax_br (bfd_byte *contents, bfd_vma off)
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{
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unsigned int template, mlx;
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bfd_vma t0, t1, s0, s1, s2, br_code;
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long br_slot;
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bfd_byte *hit_addr;
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hit_addr = (bfd_byte *) (contents + off);
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br_slot = (long) hit_addr & 0x3;
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hit_addr -= br_slot;
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t0 = bfd_getl64 (hit_addr + 0);
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t1 = bfd_getl64 (hit_addr + 8);
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/* Check if we can turn br into brl. A label is always at the start
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of the bundle. Even if there are predicates on NOPs, we still
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perform this optimization. */
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template = t0 & 0x1e;
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s0 = (t0 >> 5) & 0x1ffffffffffLL;
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s1 = ((t0 >> 46) | (t1 << 18)) & 0x1ffffffffffLL;
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s2 = (t1 >> 23) & 0x1ffffffffffLL;
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switch (br_slot)
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{
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case 0:
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/* Check if slot 1 and slot 2 are NOPs. Possible template is
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BBB. We only need to check nop.b. */
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if (!(IS_NOP_B (s1) && IS_NOP_B (s2)))
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return FALSE;
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br_code = s0;
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break;
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case 1:
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/* Check if slot 2 is NOP. Possible templates are MBB and BBB.
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For BBB, slot 0 also has to be nop.b. */
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if (!((template == 0x12 /* MBB */
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&& IS_NOP_B (s2))
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|| (template == 0x16 /* BBB */
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&& IS_NOP_B (s0)
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&& IS_NOP_B (s2))))
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return FALSE;
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br_code = s1;
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break;
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case 2:
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/* Check if slot 1 is NOP. Possible templates are MIB, MBB, BBB,
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MMB and MFB. For BBB, slot 0 also has to be nop.b. */
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if (!((template == 0x10 /* MIB */
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&& IS_NOP_I (s1))
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|| (template == 0x12 /* MBB */
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&& IS_NOP_B (s1))
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|| (template == 0x16 /* BBB */
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&& IS_NOP_B (s0)
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&& IS_NOP_B (s1))
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|| (template == 0x18 /* MMB */
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&& IS_NOP_M (s1))
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|| (template == 0x1c /* MFB */
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&& IS_NOP_F (s1))))
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return FALSE;
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br_code = s2;
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break;
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default:
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/* It should never happen. */
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abort ();
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}
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/* We can turn br.cond/br.call into brl.cond/brl.call. */
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if (!(IS_BR_COND (br_code) || IS_BR_CALL (br_code)))
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return FALSE;
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/* Turn br into brl by setting bit 40. */
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br_code |= 0x1LL << 40;
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/* Turn the old bundle into a MLX bundle with the same stop-bit
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variety. */
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if (t0 & 0x1)
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mlx = 0x5;
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else
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mlx = 0x4;
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if (template == 0x16)
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{
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/* For BBB, we need to put nop.m in slot 0 and keep the original
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predicate. */
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t0 &= PREDICATE_BITS << 5;
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t0 |= 0x1LL << (X4_SHIFT + 5);
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}
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else
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{
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/* Keep the original instruction in slot 0. */
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t0 &= 0x1ffffffffffLL << 5;
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}
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t0 |= mlx;
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/* Put brl in slot 1. */
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t1 = br_code << 23;
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bfd_putl64 (t0, hit_addr);
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bfd_putl64 (t1, hit_addr + 8);
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return TRUE;
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}
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static void
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elfNN_ia64_relax_brl (bfd_byte *contents, bfd_vma off)
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{
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@ -985,6 +1120,16 @@ elfNN_ia64_relax_section (abfd, sec, link_info, again)
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}
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else if (r_type == R_IA64_PCREL60B)
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continue;
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else if (elfNN_ia64_relax_br (contents, roff))
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{
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irel->r_info
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= ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
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R_IA64_PCREL60B);
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/* Make the relocation offset point to slot 1. */
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irel->r_offset = (irel->r_offset & ~((bfd_vma) 0x3)) + 1;
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continue;
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}
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/* We can't put a trampoline in a .init/.fini section. Issue
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an error. */
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