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x86/Intel: fix operand checking for MOVSD
The dual purpose mnemonic (string move vs scalar double move) breaks the assumption that the isstring flag would be set on both the first and last entry in the current set of templates, which results in bogus or missing diagnostics for the string move variant of the mnemonic. Short of mostly rewriting i386_index_check() and its interaction with the rest of the code, simply shrink the template set to just string instructions when encountering the second memory operand, and run i386_index_check() a second time for the first memory operand after that reduction.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
eefbbb8cbe
commit
8325cc6398
@ -1,3 +1,18 @@
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2016-07-01 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (struct _i386_insn): New field memop1_string.
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(md_assemble): Free first memory operand string.
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(i386_index_check): Use repprefixok to distingush xlat from
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other (real) string ops.
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(maybe_adjust_templates): New.
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(i386_att_operand). Call it. Store first memory operand string.
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* config/tc-i386-intel.c (i386_intel_operand): Likewise.
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* testsuite/gas/i386/intel-movs.s: New.
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* testsuite/gas/i386/intel-movs32.d: New.
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* testsuite/gas/i386/intel-movs64.d: New.
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* testsuite/gas/i386/i386.exp: Run new tests. Invoke as for
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64-bits tests with "--defsym x86_64=1 --strip-local-absolute".
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2016-06-30 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (get_append_method): Fix a comment typo.
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@ -821,6 +821,8 @@ i386_intel_operand (char *operand_string, int got_a_float)
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|| intel_state.is_mem)
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{
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/* Memory operand. */
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if (i.mem_operands == 1 && !maybe_adjust_templates ())
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return 0;
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if ((int) i.mem_operands
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>= 2 - !current_templates->start->opcode_modifier.isstring)
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{
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@ -983,6 +985,8 @@ i386_intel_operand (char *operand_string, int got_a_float)
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return 0;
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i.types[this_operand].bitfield.mem = 1;
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if (i.mem_operands == 0)
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i.memop1_string = xstrdup (operand_string);
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++i.mem_operands;
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}
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else
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@ -326,6 +326,9 @@ struct _i386_insn
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explicit segment overrides are given. */
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const seg_entry *seg[2];
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/* Copied first memory operand string, for re-checking. */
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char *memop1_string;
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/* PREFIX holds all the given prefix opcodes (usually null).
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PREFIXES is the number of prefix opcodes. */
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unsigned int prefixes;
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@ -3555,6 +3558,8 @@ md_assemble (char *line)
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line = parse_operands (line, mnemonic);
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this_operand = -1;
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xfree (i.memop1_string);
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i.memop1_string = NULL;
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if (line == NULL)
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return;
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@ -8510,7 +8515,7 @@ i386_index_check (const char *operand_string)
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kind = "string address";
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if (current_templates->start->opcode_modifier.w)
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if (current_templates->start->opcode_modifier.repprefixok)
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{
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i386_operand_type type = current_templates->end[-1].operand_types[0];
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@ -8661,6 +8666,49 @@ RC_SAE_immediate (const char *imm_start)
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return 1;
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}
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/* Only string instructions can have a second memory operand, so
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reduce current_templates to just those if it contains any. */
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static int
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maybe_adjust_templates (void)
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{
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const insn_template *t;
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gas_assert (i.mem_operands == 1);
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for (t = current_templates->start; t < current_templates->end; ++t)
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if (t->opcode_modifier.isstring)
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break;
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if (t < current_templates->end)
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{
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static templates aux_templates;
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bfd_boolean recheck;
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aux_templates.start = t;
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for (; t < current_templates->end; ++t)
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if (!t->opcode_modifier.isstring)
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break;
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aux_templates.end = t;
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/* Determine whether to re-check the first memory operand. */
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recheck = (aux_templates.start != current_templates->start
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|| t != current_templates->end);
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current_templates = &aux_templates;
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if (recheck)
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{
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i.mem_operands = 0;
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if (i.memop1_string != NULL
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&& i386_index_check (i.memop1_string) == 0)
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return 0;
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i.mem_operands = 1;
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}
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}
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return 1;
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}
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/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
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on error. */
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@ -8800,6 +8848,8 @@ i386_att_operand (char *operand_string)
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char *vop_start;
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do_memory_reference:
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if (i.mem_operands == 1 && !maybe_adjust_templates ())
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return 0;
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if ((i.mem_operands == 1
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&& !current_templates->start->opcode_modifier.isstring)
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|| i.mem_operands == 2)
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@ -8977,6 +9027,8 @@ i386_att_operand (char *operand_string)
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if (i386_index_check (operand_string) == 0)
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return 0;
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i.types[this_operand].bitfield.mem = 1;
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if (i.mem_operands == 0)
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i.memop1_string = xstrdup (operand_string);
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i.mem_operands++;
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}
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else
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@ -401,6 +401,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "att-regs"
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run_dump_test "intel-got32"
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run_dump_test "intel-regs"
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run_dump_test "intel-movs32"
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run_list_test "inval-equ-1" "-al"
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run_list_test "inval-equ-2" "-al"
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run_dump_test "ifunc"
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@ -482,7 +483,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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global ASFLAGS
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set old_ASFLAGS "$ASFLAGS"
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set ASFLAGS "$ASFLAGS --64"
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set ASFLAGS "$ASFLAGS --64 --defsym x86_64=1 --strip-local-absolute"
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run_dump_test "x86_64"
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run_dump_test "x86_64-intel"
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@ -564,6 +565,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-sib-intel"
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run_dump_test "x86-64-disp"
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run_dump_test "x86-64-disp-intel"
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run_dump_test "intel-movs64"
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run_dump_test "x86-64-disp32"
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run_dump_test "rexw"
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run_list_test "x86-64-specific-reg"
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18
gas/testsuite/gas/i386/intel-movs.s
Normal file
18
gas/testsuite/gas/i386/intel-movs.s
Normal file
@ -0,0 +1,18 @@
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.text
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.intel_syntax noprefix
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movs:
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movsb
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movsb es:[edi], [esi]
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movsb es:[edi], fs:[esi]
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movsw
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movsw es:[edi], [esi]
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movsw es:[edi], fs:[esi]
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movsd
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movsd es:[edi], [esi]
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movsd es:[edi], fs:[esi]
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.ifdef x86_64
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movsq
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movsq es:[rdi], [rsi]
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movsq es:[rdi], fs:[rsi]
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.endif
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19
gas/testsuite/gas/i386/intel-movs32.d
Normal file
19
gas/testsuite/gas/i386/intel-movs32.d
Normal file
@ -0,0 +1,19 @@
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#objdump: -dMintel
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#source: intel-movs.s
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#name: x86 Intel movs (32-bit object)
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.*: +file format .*
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Disassembly of section .text:
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0+ <movs>:
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[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\])
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[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\])
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[ ]*[a-f0-9]+: 64 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?fs:\[esi\]
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[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\])
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[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\])
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[ ]*[a-f0-9]+: 64 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?fs:\[esi\]
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[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\])
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[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\])
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[ ]*[a-f0-9]+: 64 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?fs:?\[esi\]
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#pass
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22
gas/testsuite/gas/i386/intel-movs64.d
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22
gas/testsuite/gas/i386/intel-movs64.d
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@ -0,0 +1,22 @@
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#objdump: -dMintel
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#source: intel-movs.s
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#name: x86 Intel movs (64-bit object)
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.*: +file format .*
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Disassembly of section .text:
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0+ <movs>:
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[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\])
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[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\]
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[ ]*[a-f0-9]+: 64 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?fs:\[esi\]
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[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\])
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[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\]
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[ ]*[a-f0-9]+: 64 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?fs:\[esi\]
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[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\])
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[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\]
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[ ]*[a-f0-9]+: 64 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?fs:\[esi\]
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[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\])
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[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\])
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[ ]*[a-f0-9]+: 64 48 a5 * movs +QWORD PTR es:\[rdi\],(QWORD PTR )?fs:?\[rsi\]
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#pass
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@ -1,3 +1,8 @@
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2016-07-01 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (xlat): Remove RepPrefixOk.
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* i386-tbl.h: Re-generate.
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2016-06-30 Yao Qi <yao.qi@linaro.org>
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* arm-dis.c (print_insn): Fix typo in comment.
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@ -474,8 +474,8 @@ stos, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk,
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ssto, 0, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
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ssto, 1, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
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ssto, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
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xlat, 0, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
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xlat, 1, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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xlat, 0, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 }
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xlat, 1, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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// Bit manipulation.
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bsf, 2, 0xfbc, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
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@ -4985,7 +4985,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
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1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -4998,7 +4998,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
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1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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