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aarch64: Remove support for CSRE
This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
This commit is contained in:
Kyrylo Tkachov
parent
c0f6e439cc
commit
82c70b08df
@ -1,3 +1,20 @@
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2021-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* NEWS: Remove CSRE.
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* config/tc-aarch64.c (parse_csr_operand): Delete.
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(parse_operands): Delete handling of
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AARCH64_OPND_CSRE_CSR.
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(aarch64_features): Remove csre.
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* doc/c-aarch64.texi: Remove CSRE.
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* testsuite/gas/aarch64/csre.d: Delete.
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* testsuite/gas/aarch64/csre-invalid.s: Likewise.
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* testsuite/gas/aarch64/csre-invalid.d: Likewise.
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* testsuite/gas/aarch64/csre_csr.s: Likewise.
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* testsuite/gas/aarch64/csre_csr.d: Likewise.
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* testsuite/gas/aarch64/csre_csr-invalid.s: Likewise.
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* testsuite/gas/aarch64/csre_csr-invalid.l: Likewise.
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* testsuite/gas/aarch64/csre_csr-invalid.d: Likewise.
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2021-01-11 Nick Clifton <nickc@redhat.com>
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* po/uk.po: Updated Ukranian translation.
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8
gas/NEWS
8
gas/NEWS
@ -18,18 +18,14 @@ Changes in 2.36:
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Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM.
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* Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace
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Extension), TRBE (Trace Buffer Extension), CSRE (Call Stack Recorder
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Extension) and BRBE (Branch Record Buffer Extension) system registers for
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AArch64.
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Extension), TRBE (Trace Buffer Extension)and BRBE (Branch Record Buffer
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Extension) system registers for AArch64.
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* Add support for Armv8-R and Armv8.7-A AArch64.
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* Add support for DSB memory nXS barrier, WFET and WFIT instruction for Armv8.7
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AArch64.
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* Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE
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feature in AArch64.
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* Add support for +flagm feature for -march in Armv8.4 AArch64.
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* Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic
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@ -4036,29 +4036,6 @@ parse_barrier_psb (char **str,
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return 0;
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}
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/* Parse an operand for CSR (CSRE instruction). */
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static int
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parse_csr_operand (char **str)
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{
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char *p, *q;
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p = q = *str;
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while (ISALPHA (*q))
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q++;
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/* Instruction has only one operand PDEC which encodes Rt field of the
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operation to 0b11111. */
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if (strcasecmp(p, "pdec"))
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{
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set_syntax_error (_("CSR instruction accepts only PDEC"));
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return PARSE_FAIL;
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}
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*str = q;
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return 0;
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}
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/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
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return 0 if successful. Otherwise return PARSE_FAIL. */
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@ -6793,12 +6770,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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goto failure;
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break;
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case AARCH64_OPND_CSRE_CSR:
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val = parse_csr_operand (&str);
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if (val == PARSE_FAIL)
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goto failure;
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break;
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default:
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as_fatal (_("unhandled operand code %d"), operands[i]);
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}
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@ -9230,8 +9201,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
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{"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
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{"csre", AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0),
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AARCH64_ARCH_NONE},
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{"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0),
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AARCH64_ARCH_NONE},
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{"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0),
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@ -229,8 +229,6 @@ automatically cause those extensions to be disabled.
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@tab Enable SVE2 SHA3 Extension.
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@item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
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@tab Enable Flag Manipulation instructions.
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@item @code{csre} @tab ARMv8-A @tab No
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@tab Enable Call Stack Recorder Extension.
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@item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
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@tab Enable 64 Byte Loads/Stores.
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@item @code{pauth} @tab ARMv8-A @tab No
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@ -1,3 +0,0 @@
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#name: Invalid CSRE System registers usage
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#source: csre-invalid.s
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#warning_output: csre-invalid.l
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@ -1,6 +0,0 @@
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/* Write to read-only CSRE system registers. */
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msr csridr_el0 ,x0
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msr csrptridx_el0 ,x0
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msr csrptridx_el1 ,x0
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msr csrptridx_el2 ,x0
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@ -1,29 +0,0 @@
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#name: CSRE System registers
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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[^:]+: d5338000 mrs x0, csrcr_el0
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[^:]+: d5338020 mrs x0, csrptr_el0
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[^:]+: d5338040 mrs x0, csridr_el0
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[^:]+: d5338060 mrs x0, csrptridx_el0
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[^:]+: d5308000 mrs x0, csrcr_el1
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[^:]+: d5358000 mrs x0, csrcr_el12
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[^:]+: d5308020 mrs x0, csrptr_el1
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[^:]+: d5358020 mrs x0, csrptr_el12
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[^:]+: d5308060 mrs x0, csrptridx_el1
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[^:]+: d5348000 mrs x0, csrcr_el2
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[^:]+: d5348020 mrs x0, csrptr_el2
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[^:]+: d5348060 mrs x0, csrptridx_el2
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[^:]+: d5138000 msr csrcr_el0, x0
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[^:]+: d5138020 msr csrptr_el0, x0
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[^:]+: d5108000 msr csrcr_el1, x0
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[^:]+: d5158000 msr csrcr_el12, x0
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[^:]+: d5108020 msr csrptr_el1, x0
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[^:]+: d5158020 msr csrptr_el12, x0
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[^:]+: d5148000 msr csrcr_el2, x0
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[^:]+: d5148020 msr csrptr_el2, x0
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@ -1,3 +0,0 @@
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#name: CSR PDEC instruction
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#source: csre_csr-invalid.s
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#error_output: csre_csr-invalid.l
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@ -1,2 +0,0 @@
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.*: Assembler messages:
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.*: Error: selected processor does not support `csr pdec'
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@ -1,4 +0,0 @@
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/* CSR PDEC requires +csre for -march= command line option. */
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.arch armv8-a
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csr pdec
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@ -1,10 +0,0 @@
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#name: CSRE extension CSR PDEC instruction
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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.*: d50b721f csr pdec
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.*: d50b721f csr pdec
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@ -1,4 +0,0 @@
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.arch armv8-a+csre
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csr pdec
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CSR PDEC
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@ -1,3 +1,8 @@
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2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete.
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(aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR.
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2021-01-09 Nick Clifton <nickc@redhat.com>
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* 2.36 release branch crated.
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@ -51,7 +51,6 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
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#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
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#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
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#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */
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#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */
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#define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */
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#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
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@ -440,7 +439,6 @@ enum aarch64_opnd
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AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
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AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
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AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
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AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */
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};
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/* Qualifier constrains an operand. It either specifies a variant of an
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@ -1,3 +1,15 @@
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2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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* aarch64-opc.c (aarch64_print_operand):
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Delete handling of AARCH64_OPND_CSRE_CSR.
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* aarch64-tbl.h (aarch64_feature_csre): Delete.
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(CSRE): Likewise.
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(_CSRE_INSN): Likewise.
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(aarch64_opcode_table): Delete csr.
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2021-01-11 Nick Clifton <nickc@redhat.com>
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* po/de.po: Updated German translation.
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@ -426,177 +426,177 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1188: /* movz */
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value = 1188; /* --> movz. */
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break;
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case 1247: /* autibsp */
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case 1246: /* autibz */
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case 1245: /* autiasp */
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case 1244: /* autiaz */
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case 1243: /* pacibsp */
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case 1242: /* pacibz */
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case 1241: /* paciasp */
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case 1240: /* paciaz */
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case 1216: /* tsb */
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case 1215: /* psb */
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case 1214: /* esb */
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case 1213: /* autib1716 */
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case 1212: /* autia1716 */
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case 1211: /* pacib1716 */
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case 1210: /* pacia1716 */
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case 1209: /* xpaclri */
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case 1207: /* sevl */
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case 1206: /* sev */
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case 1205: /* wfi */
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case 1204: /* wfe */
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case 1203: /* yield */
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case 1202: /* bti */
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case 1201: /* csdb */
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case 1200: /* nop */
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case 1199: /* hint */
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value = 1199; /* --> hint. */
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case 1246: /* autibsp */
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case 1245: /* autibz */
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case 1244: /* autiasp */
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case 1243: /* autiaz */
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case 1242: /* pacibsp */
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case 1241: /* pacibz */
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case 1240: /* paciasp */
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case 1239: /* paciaz */
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case 1215: /* tsb */
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case 1214: /* psb */
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case 1213: /* esb */
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case 1212: /* autib1716 */
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case 1211: /* autia1716 */
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case 1210: /* pacib1716 */
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case 1209: /* pacia1716 */
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case 1208: /* xpaclri */
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case 1206: /* sevl */
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case 1205: /* sev */
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case 1204: /* wfi */
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case 1203: /* wfe */
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case 1202: /* yield */
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case 1201: /* bti */
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case 1200: /* csdb */
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case 1199: /* nop */
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case 1198: /* hint */
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value = 1198; /* --> hint. */
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break;
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case 1221: /* pssbb */
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case 1220: /* ssbb */
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case 1219: /* dfb */
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case 1217: /* dsb */
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value = 1217; /* --> dsb. */
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break;
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case 1222: /* pssbb */
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case 1221: /* ssbb */
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case 1220: /* dfb */
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case 1218: /* dsb */
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value = 1218; /* --> dsb. */
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break;
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case 1219: /* dsb */
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value = 1219; /* --> dsb. */
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case 1234: /* cpp */
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case 1233: /* dvp */
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case 1232: /* cfp */
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case 1229: /* tlbi */
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case 1228: /* ic */
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case 1227: /* dc */
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case 1226: /* at */
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case 1225: /* sys */
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value = 1225; /* --> sys. */
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break;
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case 1235: /* cpp */
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case 1234: /* dvp */
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case 1233: /* cfp */
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case 1230: /* tlbi */
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case 1229: /* ic */
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case 1228: /* dc */
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case 1227: /* at */
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case 1226: /* sys */
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value = 1226; /* --> sys. */
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case 1230: /* wfet */
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value = 1230; /* --> wfet. */
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break;
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case 1231: /* wfet */
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value = 1231; /* --> wfet. */
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case 1231: /* wfit */
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value = 1231; /* --> wfit. */
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break;
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case 1232: /* wfit */
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value = 1232; /* --> wfit. */
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case 2044: /* bic */
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case 1294: /* and */
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value = 1294; /* --> and. */
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break;
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case 2045: /* bic */
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case 1295: /* and */
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value = 1295; /* --> and. */
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case 1277: /* mov */
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case 1296: /* and */
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value = 1296; /* --> and. */
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break;
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case 1278: /* mov */
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case 1297: /* and */
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value = 1297; /* --> and. */
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case 1281: /* movs */
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case 1297: /* ands */
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value = 1297; /* --> ands. */
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break;
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case 1282: /* movs */
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case 1298: /* ands */
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value = 1298; /* --> ands. */
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case 2045: /* cmple */
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case 1332: /* cmpge */
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value = 1332; /* --> cmpge. */
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break;
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case 2046: /* cmple */
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case 1333: /* cmpge */
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value = 1333; /* --> cmpge. */
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case 2048: /* cmplt */
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case 1335: /* cmpgt */
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value = 1335; /* --> cmpgt. */
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break;
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case 2049: /* cmplt */
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case 1336: /* cmpgt */
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value = 1336; /* --> cmpgt. */
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case 2046: /* cmplo */
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case 1337: /* cmphi */
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value = 1337; /* --> cmphi. */
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break;
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case 2047: /* cmplo */
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case 1338: /* cmphi */
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value = 1338; /* --> cmphi. */
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case 2047: /* cmpls */
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case 1340: /* cmphs */
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value = 1340; /* --> cmphs. */
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break;
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case 2048: /* cmpls */
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case 1341: /* cmphs */
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value = 1341; /* --> cmphs. */
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case 1274: /* mov */
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case 1362: /* cpy */
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value = 1362; /* --> cpy. */
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break;
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case 1275: /* mov */
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case 1276: /* mov */
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case 1363: /* cpy */
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value = 1363; /* --> cpy. */
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break;
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case 1277: /* mov */
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case 2055: /* fmov */
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case 1279: /* mov */
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case 1364: /* cpy */
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value = 1364; /* --> cpy. */
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break;
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case 2056: /* fmov */
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case 1280: /* mov */
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case 1365: /* cpy */
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value = 1365; /* --> cpy. */
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case 1269: /* mov */
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case 1376: /* dup */
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value = 1376; /* --> dup. */
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break;
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case 1270: /* mov */
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case 1271: /* mov */
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case 1268: /* mov */
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case 1377: /* dup */
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value = 1377; /* --> dup. */
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break;
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case 1272: /* mov */
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case 1269: /* mov */
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case 2054: /* fmov */
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case 1273: /* mov */
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case 1378: /* dup */
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value = 1378; /* --> dup. */
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break;
|
||||
case 2055: /* fmov */
|
||||
case 1274: /* mov */
|
||||
case 1379: /* dup */
|
||||
value = 1379; /* --> dup. */
|
||||
case 1272: /* mov */
|
||||
case 1379: /* dupm */
|
||||
value = 1379; /* --> dupm. */
|
||||
break;
|
||||
case 1273: /* mov */
|
||||
case 1380: /* dupm */
|
||||
value = 1380; /* --> dupm. */
|
||||
case 2049: /* eon */
|
||||
case 1381: /* eor */
|
||||
value = 1381; /* --> eor. */
|
||||
break;
|
||||
case 2050: /* eon */
|
||||
case 1382: /* eor */
|
||||
value = 1382; /* --> eor. */
|
||||
case 1282: /* not */
|
||||
case 1383: /* eor */
|
||||
value = 1383; /* --> eor. */
|
||||
break;
|
||||
case 1283: /* not */
|
||||
case 1384: /* eor */
|
||||
value = 1384; /* --> eor. */
|
||||
case 1283: /* nots */
|
||||
case 1384: /* eors */
|
||||
value = 1384; /* --> eors. */
|
||||
break;
|
||||
case 1284: /* nots */
|
||||
case 1385: /* eors */
|
||||
value = 1385; /* --> eors. */
|
||||
case 2050: /* facle */
|
||||
case 1389: /* facge */
|
||||
value = 1389; /* --> facge. */
|
||||
break;
|
||||
case 2051: /* facle */
|
||||
case 1390: /* facge */
|
||||
value = 1390; /* --> facge. */
|
||||
case 2051: /* faclt */
|
||||
case 1390: /* facgt */
|
||||
value = 1390; /* --> facgt. */
|
||||
break;
|
||||
case 2052: /* faclt */
|
||||
case 1391: /* facgt */
|
||||
value = 1391; /* --> facgt. */
|
||||
case 2052: /* fcmle */
|
||||
case 1403: /* fcmge */
|
||||
value = 1403; /* --> fcmge. */
|
||||
break;
|
||||
case 2053: /* fcmle */
|
||||
case 1404: /* fcmge */
|
||||
value = 1404; /* --> fcmge. */
|
||||
break;
|
||||
case 2054: /* fcmlt */
|
||||
case 1406: /* fcmgt */
|
||||
value = 1406; /* --> fcmgt. */
|
||||
break;
|
||||
case 1267: /* fmov */
|
||||
case 1412: /* fcpy */
|
||||
value = 1412; /* --> fcpy. */
|
||||
case 2053: /* fcmlt */
|
||||
case 1405: /* fcmgt */
|
||||
value = 1405; /* --> fcmgt. */
|
||||
break;
|
||||
case 1266: /* fmov */
|
||||
case 1435: /* fdup */
|
||||
value = 1435; /* --> fdup. */
|
||||
case 1411: /* fcpy */
|
||||
value = 1411; /* --> fcpy. */
|
||||
break;
|
||||
case 1268: /* mov */
|
||||
case 1265: /* fmov */
|
||||
case 1434: /* fdup */
|
||||
value = 1434; /* --> fdup. */
|
||||
break;
|
||||
case 1267: /* mov */
|
||||
case 1765: /* orr */
|
||||
value = 1765; /* --> orr. */
|
||||
break;
|
||||
case 2056: /* orn */
|
||||
case 1766: /* orr */
|
||||
value = 1766; /* --> orr. */
|
||||
break;
|
||||
case 2057: /* orn */
|
||||
case 1767: /* orr */
|
||||
value = 1767; /* --> orr. */
|
||||
case 1270: /* mov */
|
||||
case 1768: /* orr */
|
||||
value = 1768; /* --> orr. */
|
||||
break;
|
||||
case 1271: /* mov */
|
||||
case 1769: /* orr */
|
||||
value = 1769; /* --> orr. */
|
||||
case 1280: /* movs */
|
||||
case 1769: /* orrs */
|
||||
value = 1769; /* --> orrs. */
|
||||
break;
|
||||
case 1281: /* movs */
|
||||
case 1770: /* orrs */
|
||||
value = 1770; /* --> orrs. */
|
||||
case 1275: /* mov */
|
||||
case 1831: /* sel */
|
||||
value = 1831; /* --> sel. */
|
||||
break;
|
||||
case 1276: /* mov */
|
||||
case 1278: /* mov */
|
||||
case 1832: /* sel */
|
||||
value = 1832; /* --> sel. */
|
||||
break;
|
||||
case 1279: /* mov */
|
||||
case 1833: /* sel */
|
||||
value = 1833; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -312,17 +312,17 @@ static const unsigned op_enum_table [] =
|
||||
391,
|
||||
413,
|
||||
415,
|
||||
1271,
|
||||
1276,
|
||||
1269,
|
||||
1270,
|
||||
1275,
|
||||
1268,
|
||||
1272,
|
||||
1279,
|
||||
1281,
|
||||
1282,
|
||||
1267,
|
||||
1271,
|
||||
1278,
|
||||
1284,
|
||||
1280,
|
||||
1281,
|
||||
1277,
|
||||
1283,
|
||||
1282,
|
||||
131,
|
||||
};
|
||||
|
||||
|
||||
@ -3788,10 +3788,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
snprintf (buf, size, "%s", opnd->hint_option->name);
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_CSRE_CSR:
|
||||
snprintf (buf, size, "pdec");
|
||||
break;
|
||||
|
||||
default:
|
||||
assert (0);
|
||||
}
|
||||
|
||||
@ -2418,8 +2418,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
|
||||
| AARCH64_FEATURE_SVE, 0);
|
||||
static const aarch64_feature_set aarch64_feature_v8_r =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_V8_R, 0);
|
||||
static const aarch64_feature_set aarch64_feature_csre =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0);
|
||||
static const aarch64_feature_set aarch64_feature_ls64 =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_V8_6 | AARCH64_FEATURE_LS64, 0);
|
||||
static const aarch64_feature_set aarch64_feature_flagm =
|
||||
@ -2470,7 +2468,6 @@ static const aarch64_feature_set aarch64_feature_flagm =
|
||||
#define I8MM &aarch64_feature_i8mm
|
||||
#define ARMV8_R &aarch64_feature_v8_r
|
||||
#define ARMV8_7 &aarch64_feature_v8_7
|
||||
#define CSRE &aarch64_feature_csre
|
||||
#define LS64 &aarch64_feature_ls64
|
||||
#define FLAGM &aarch64_feature_flagm
|
||||
|
||||
@ -2582,8 +2579,6 @@ static const aarch64_feature_set aarch64_feature_flagm =
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define V8_7_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_7, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define _CSRE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, CSRE, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
@ -3863,8 +3858,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
|
||||
_TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
|
||||
_TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
|
||||
/* CSRE Instructions. */
|
||||
_CSRE_INSN ("csr", 0xd50b721f, 0xffffffff, 0, OP1 (CSRE_CSR), {}, 0),
|
||||
/* System. */
|
||||
CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE),
|
||||
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user