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sim: bfin: se_all32bitopcodes: skip debug insns under the sim

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Since the sim has a few fake debug insns that the hardware does not, we
need to check for those before attempting to run them.  Otherwise we'll
randomly trigger the sim debug asserts/aborts/halts insns.  On the
hardware, these are proper invalid insns, and the table catches that.
This commit is contained in:
Mike Frysinger 2013-06-24 01:52:33 +00:00
parent 531d5282c0
commit 7f5884f775
2 changed files with 18 additions and 1 deletions
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4
sim/testsuite/sim/bfin/ChangeLog
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@ -1,3 +1,7 @@
2013-06-23 Mike Frysinger <vapier@gentoo.org>
* se_all32bitopcodes.S (se_all_next_insn): Skip debug insn opcodes.
2013-06-23 Mike Frysinger <vapier@gentoo.org>
* se_allopcodes.h (_match): Simplify register test to one less insn.

15
sim/testsuite/sim/bfin/se_all32bitopcodes.S
View File

@ -64,6 +64,19 @@
R0 = R0 + R1;
1:
.ifndef BFIN_JTAG
/* Skip debug insns when running in the sim. */
R1.L = 0xff00;
R1.H = 0x0000;
R2 = R0 & R1;
R1.L = 0xf000;
CC = R1 == R2;
IF !CC jump 1f (bp);
R0.L = 0xf100;
R0.H = 0x0000;
1:
.endif
[P5] = R0;
.endm
@ -34164,7 +34177,7 @@
.dw 0x0000, 0xe5c0, 0xffff, 0xe5ff, 0x21, 0
.dw 0x0000, 0xe6c0, 0xffff, 0xe6ff, 0x21, 0
.dw 0x0000, 0xe740, 0xffff, 0xe7ff, 0x21, 0
.dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0
.dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0
.dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0
.endm