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* gas/config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.
(neon_cvt_mode): New enumeration. (do_vfp_nsyn_cvt_fpv8): New function. (do_neon_cvt_1): Add support for new conversions. (do_neon_cvtr): Use neon_cvt_mode enumerator. (do_neon_cvt): Likewise. (do_neon_cvta): New function. (do_neon_cvtn): Likewise. (do_neon_cvtp): Likewise. (do_neon_cvtm): Likewise. (insns): Add new VCVT instructions. * gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+fp.s: Likewise. * gas/testsuite/gas/arm/armv8-a+simd.d: Likewise. * gas/testsuite/gas/arm/armv8-a+simd.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add support for new VCVT variants. (neon_opcodes): Likewise.
This commit is contained in:
Matthew Gretton-Dann
parent
6b9a8b6790
commit
7e8e678496
@ -1,3 +1,17 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.
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(neon_cvt_mode): New enumeration.
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(do_vfp_nsyn_cvt_fpv8): New function.
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(do_neon_cvt_1): Add support for new conversions.
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(do_neon_cvtr): Use neon_cvt_mode enumerator.
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(do_neon_cvt): Likewise.
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(do_neon_cvta): New function.
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(do_neon_cvtn): Likewise.
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(do_neon_cvtp): Likewise.
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(do_neon_cvtm): Likewise.
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(insns): Add new VCVT instructions.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm>
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* config/tc-arm.c (CVT_FLAVOUR_VAR): New define.
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@ -12347,7 +12347,8 @@ struct neon_tab_entry
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X(vselge, 0xe200a00, N_INV, N_INV), \
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X(vselgt, 0xe300a00, N_INV, N_INV), \
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X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
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X(vminnm, 0xe800a40, 0x3200f10, N_INV)
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X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
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X(vcvta, 0xebc0a40, 0x3bb0000, N_INV)
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enum neon_opc
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{
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@ -14574,6 +14575,16 @@ get_neon_cvt_flavour (enum neon_shape rs)
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#undef CVT_VAR
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}
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enum neon_cvt_mode
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{
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neon_cvt_mode_a,
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neon_cvt_mode_n,
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neon_cvt_mode_p,
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neon_cvt_mode_m,
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neon_cvt_mode_z,
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neon_cvt_mode_x
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};
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/* Neon-syntax VFP conversions. */
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static void
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@ -14638,14 +14649,65 @@ do_vfp_nsyn_cvtz (void)
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}
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static void
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do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
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do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
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enum neon_cvt_mode mode)
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{
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int sz, op;
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int rm;
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set_it_insn_type (OUTSIDE_IT_INSN);
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switch (flavour)
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{
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case neon_cvt_flavour_s32_f64:
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sz = 1;
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op = 0;
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break;
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case neon_cvt_flavour_s32_f32:
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sz = 0;
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op = 1;
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break;
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case neon_cvt_flavour_u32_f64:
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sz = 1;
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op = 0;
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break;
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case neon_cvt_flavour_u32_f32:
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sz = 0;
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op = 0;
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break;
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default:
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first_error (_("invalid instruction shape"));
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return;
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}
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switch (mode)
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{
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case neon_cvt_mode_a: rm = 0; break;
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case neon_cvt_mode_n: rm = 1; break;
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case neon_cvt_mode_p: rm = 2; break;
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case neon_cvt_mode_m: rm = 3; break;
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default: first_error (_("invalid rounding mode")); return;
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}
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NEON_ENCODE (FPV8, inst);
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encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
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encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
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inst.instruction |= sz << 8;
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inst.instruction |= op << 7;
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inst.instruction |= rm << 16;
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inst.instruction |= 0xf0000000;
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inst.is_neon = TRUE;
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}
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static void
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do_neon_cvt_1 (enum neon_cvt_mode mode)
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{
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enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
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NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
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enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
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/* PR11109: Handle round-to-zero for VCVT conversions. */
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if (round_to_zero
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if (mode == neon_cvt_mode_z
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&& ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
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&& (flavour == neon_cvt_flavour_s32_f32
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|| flavour == neon_cvt_flavour_u32_f32
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@ -14660,7 +14722,11 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
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/* VFP rather than Neon conversions. */
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if (flavour >= neon_cvt_flavour_first_fp)
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{
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do_vfp_nsyn_cvt (rs, flavour);
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if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
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do_vfp_nsyn_cvt (rs, flavour);
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else
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do_vfp_nsyn_cvt_fpv8 (flavour, mode);
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return;
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}
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@ -14697,28 +14763,51 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
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case NS_DD:
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case NS_QQ:
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if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
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{
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NEON_ENCODE (FLOAT, inst);
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set_it_insn_type (OUTSIDE_IT_INSN);
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
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return;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.instruction |= HI1 (inst.operands[1].reg) << 5;
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inst.instruction |= neon_quad (rs) << 6;
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inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
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inst.instruction |= mode << 8;
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if (thumb_mode)
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inst.instruction |= 0xfc000000;
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else
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inst.instruction |= 0xf0000000;
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}
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else
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{
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int_encode:
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{
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unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
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{
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unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
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NEON_ENCODE (INTEGER, inst);
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NEON_ENCODE (INTEGER, inst);
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
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return;
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
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return;
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if (flavour != neon_cvt_flavour_invalid)
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inst.instruction |= enctab[flavour];
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if (flavour != neon_cvt_flavour_invalid)
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inst.instruction |= enctab[flavour];
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.instruction |= HI1 (inst.operands[1].reg) << 5;
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inst.instruction |= neon_quad (rs) << 6;
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inst.instruction |= 2 << 18;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.instruction |= HI1 (inst.operands[1].reg) << 5;
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inst.instruction |= neon_quad (rs) << 6;
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inst.instruction |= 2 << 18;
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neon_dp_fixup (&inst);
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}
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break;
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neon_dp_fixup (&inst);
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}
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}
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break;
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/* Half-precision conversions for Advanced SIMD -- neon. */
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case NS_QD:
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@ -14752,20 +14841,47 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
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default:
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/* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
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do_vfp_nsyn_cvt (rs, flavour);
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if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
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do_vfp_nsyn_cvt (rs, flavour);
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else
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do_vfp_nsyn_cvt_fpv8 (flavour, mode);
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}
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}
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static void
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do_neon_cvtr (void)
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{
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do_neon_cvt_1 (FALSE);
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do_neon_cvt_1 (neon_cvt_mode_x);
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}
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static void
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do_neon_cvt (void)
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{
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do_neon_cvt_1 (TRUE);
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do_neon_cvt_1 (neon_cvt_mode_z);
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}
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static void
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do_neon_cvta (void)
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{
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do_neon_cvt_1 (neon_cvt_mode_a);
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}
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static void
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do_neon_cvtn (void)
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{
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do_neon_cvt_1 (neon_cvt_mode_n);
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}
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static void
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do_neon_cvtp (void)
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{
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do_neon_cvt_1 (neon_cvt_mode_p);
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}
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static void
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do_neon_cvtm (void)
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{
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do_neon_cvt_1 (neon_cvt_mode_m);
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}
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static void
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@ -18100,6 +18216,10 @@ static const struct asm_opcode insns[] =
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nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
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nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
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nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
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nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
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nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
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nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
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nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
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@ -1,3 +1,10 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/armv8-a+fp.d: Update testcase.
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* gas/arm/armv8-a+fp.s: Likewise.
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* gas/arm/armv8-a+simd.d: Likewise.
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* gas/arm/armv8-a+simd.s: Likewise.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/testsuite/gas/armv8-a+fp.d: Update testcase.
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@ -28,6 +28,14 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
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0[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0
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0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1
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0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30
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0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31
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0[0-9a-f]+ <[^>]+> febc0b40 vcvta.u32.f64 s0, d0
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0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16
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0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
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0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
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0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
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0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
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0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
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@ -52,3 +60,11 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
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0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
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0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
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0[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0
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0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1
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0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30
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0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31
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0[0-9a-f]+ <[^>]+> febc 0b40 vcvta.u32.f64 s0, d0
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0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16
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0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
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0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
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@ -28,6 +28,14 @@
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vminnm.f64 d16, d16, d16
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vminnm.f64 d15, d15, d15
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vminnm.f64 d31, d31, d31
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vcvta.s32.f32 s0, s0
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vcvtn.s32.f32 s1, s1
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vcvtp.u32.f32 s30, s30
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vcvtm.u32.f32 s31, s31
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vcvta.s32.f64 s0, d0
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vcvtn.s32.f64 s1, d16
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vcvtp.u32.f64 s30, d15
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vcvtm.u32.f64 s31, d31
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.thumb
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vseleq.f32 s0, s0, s0
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@ -54,3 +62,11 @@
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vminnm.f64 d16, d16, d16
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vminnm.f64 d15, d15, d15
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vminnm.f64 d31, d31, d31
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vcvta.s32.f32 s0, s0
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vcvtn.s32.f32 s1, s1
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vcvtp.u32.f32 s30, s30
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vcvtm.u32.f32 s31, s31
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vcvta.s32.f64 s0, d0
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vcvtn.s32.f64 s1, d16
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vcvtp.u32.f64 s30, d15
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vcvtm.u32.f64 s31, d31
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@ -20,6 +20,14 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8
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0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7
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0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15
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0[0-9a-f]+ <[^>]+> f3bb0000 vcvta.s32.f32 d0, d0
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0[0-9a-f]+ <[^>]+> f3fb0120 vcvtn.s32.f32 d16, d16
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0[0-9a-f]+ <[^>]+> f3bbf28f vcvtp.u32.f32 d15, d15
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0[0-9a-f]+ <[^>]+> f3fbf3af vcvtm.u32.f32 d31, d31
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0[0-9a-f]+ <[^>]+> f3bb0040 vcvta.s32.f32 q0, q0
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0[0-9a-f]+ <[^>]+> f3fb0160 vcvtn.s32.f32 q8, q8
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0[0-9a-f]+ <[^>]+> f3bbe2ce vcvtp.u32.f32 q7, q7
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0[0-9a-f]+ <[^>]+> f3fbe3ee vcvtm.u32.f32 q15, q15
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0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0
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0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16
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0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15
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@ -36,3 +44,11 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8
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0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7
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0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15
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0[0-9a-f]+ <[^>]+> ffbb 0000 vcvta.s32.f32 d0, d0
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0[0-9a-f]+ <[^>]+> fffb 0120 vcvtn.s32.f32 d16, d16
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0[0-9a-f]+ <[^>]+> ffbb f28f vcvtp.u32.f32 d15, d15
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||||
0[0-9a-f]+ <[^>]+> fffb f3af vcvtm.u32.f32 d31, d31
|
||||
0[0-9a-f]+ <[^>]+> ffbb 0040 vcvta.s32.f32 q0, q0
|
||||
0[0-9a-f]+ <[^>]+> fffb 0160 vcvtn.s32.f32 q8, q8
|
||||
0[0-9a-f]+ <[^>]+> ffbb e2ce vcvtp.u32.f32 q7, q7
|
||||
0[0-9a-f]+ <[^>]+> fffb e3ee vcvtm.u32.f32 q15, q15
|
||||
|
||||
@ -19,6 +19,14 @@
|
||||
vminnm.f32 q8, q8, q8
|
||||
vminnm.f32 q7, q7, q7
|
||||
vminnm.f32 q15, q15, q15
|
||||
vcvta.s32.f32 d0, d0
|
||||
vcvtn.s32.f32 d16, d16
|
||||
vcvtp.u32.f32 d15, d15
|
||||
vcvtm.u32.f32 d31, d31
|
||||
vcvta.s32.f32 q0, q0
|
||||
vcvtn.s32.f32 q8, q8
|
||||
vcvtp.u32.f32 q7, q7
|
||||
vcvtm.u32.f32 q15, q15
|
||||
|
||||
.thumb
|
||||
vmaxnm.f32 d0, d0, d0
|
||||
@ -37,3 +45,11 @@
|
||||
vminnm.f32 q8, q8, q8
|
||||
vminnm.f32 q7, q7, q7
|
||||
vminnm.f32 q15, q15, q15
|
||||
vcvta.s32.f32 d0, d0
|
||||
vcvtn.s32.f32 d16, d16
|
||||
vcvtp.u32.f32 d15, d15
|
||||
vcvtm.u32.f32 d31, d31
|
||||
vcvta.s32.f32 q0, q0
|
||||
vcvtn.s32.f32 q8, q8
|
||||
vcvtp.u32.f32 q7, q7
|
||||
vcvtm.u32.f32 q15, q15
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): Add support for new VCVT
|
||||
variants.
|
||||
(neon_opcodes): Likewise.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
|
||||
|
||||
@ -494,6 +494,8 @@ static const struct opcode32 coprocessor_opcodes[] =
|
||||
{FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
|
||||
{FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
|
||||
{FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
|
||||
{FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
|
||||
{FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
|
||||
|
||||
/* Generic coprocessor instructions. */
|
||||
{ 0, SENTINEL_GENERIC_START, 0, "" },
|
||||
@ -576,6 +578,7 @@ static const struct opcode32 neon_opcodes[] =
|
||||
{FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
|
||||
|
||||
/* Two registers, miscellaneous. */
|
||||
{FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
|
||||
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
|
||||
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
|
||||
{FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
|
||||
@ -2917,7 +2920,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
|
||||
func (stream, "{d%d-d%d}", regno, regno + num);
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
|
||||
case '0': case '1': case '2': case '3': case '4':
|
||||
case '5': case '6': case '7': case '8': case '9':
|
||||
|
||||
Loading…
Reference in New Issue
Block a user