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* coff-h8300.c: Add and adjust comments about relaxation.

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* elf32-h8300.c: Likewise.
This commit is contained in:
Kazu Hirata 2004-01-19 17:02:45 +00:00
parent 437b434f9a
commit 7e89635aac
3 changed files with 50 additions and 14 deletions
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5
bfd/ChangeLog
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@ -1,3 +1,8 @@
2004-01-19 Kazu Hirata <kazu@cs.umass.edu>
* coff-h8300.c: Add and adjust comments about relaxation.
* elf32-h8300.c: Likewise.
2004-01-16 Kazu Hirata <kazu@cs.umass.edu>
* coff-h8300.c: Fix comment typos.

27
bfd/coff-h8300.c
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@ -776,8 +776,15 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
src_address += 4;
break;
/* A 16-bit absolute relocation that was formerly a 24-/32-bit
absolute relocation. */
/* This is a 24-/32-bit absolute address in one of the following
instructions:
"band", "bclr", "biand", "bild", "bior", "bist", "bixor",
"bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and
"mov.[bwl]"
We may relax this into an 16-bit absolute address if it's in
the right range. */
case R_MOVL2:
value = bfd_coff_reloc16_get_value (reloc, link_info, input_section);
value = bfd_h8300_pad_address (abfd, value);
@ -788,8 +795,9 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
/* Insert the 16-bit value into the proper location. */
bfd_put_16 (abfd, value, data + dst_address);
/* Fix the opcode. For all the move insns, we simply
need to turn off bit 0x20 in the previous byte. */
/* Fix the opcode. For all the instructions that belong to
this relaxation, we simply need to turn off bit 0x20 in
the previous byte. */
data[dst_address - 1] &= ~0x20;
dst_address += 2;
src_address += 4;
@ -834,7 +842,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
bfd_put_8 (abfd, 0x55, data + dst_address - 1);
break;
case 0x5a:
/* jmp ->bra */
/* jmp -> bra */
bfd_put_8 (abfd, 0x40, data + dst_address - 1);
break;
@ -877,12 +885,15 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
{
case 0x58:
/* bCC:16 -> bCC:8 */
/* Get the condition code from the original insn. */
/* Get the second byte of the original insn, which contains
the condition code. */
tmp = data[dst_address - 1];
/* Compute the fisrt byte of the relaxed instruction. The
original sequence 0x58 0xX0 is relaxed to 0x4X, where X
represents the condition code. */
tmp &= 0xf0;
tmp >>= 4;
/* Now or in the high nibble of the opcode. */
tmp |= 0x40;
/* Write it. */

32
bfd/elf32-h8300.c
View File

@ -666,6 +666,9 @@ elf32_h8_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
mov.b:16 -> mov.b:8 2 bytes
mov.b:24/32 -> mov.b:8 4 bytes
bset:24/32 -> bset:16 2 bytes
(also applicable to other bit manipulation instructions)
mov.[bwl]:24/32 -> mov.[bwl]:16 2 bytes */
static bfd_boolean
@ -919,8 +922,10 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
}
if (code == 0x5e)
/* This is jsr. */
bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 1);
else if (code == 0x5a)
/* This is jmp. */
bfd_put_8 (abfd, 0x40, contents + irel->r_offset - 1);
else
abort ();
@ -975,14 +980,21 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
if (code == 0x58)
{
/* bCC:16 -> bCC:8 */
/* Get the condition code from the original insn. */
/* Get the second byte of the original insn, which
contains the condition code. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
/* Compute the fisrt byte of the relaxed
instruction. The original sequence 0x58 0xX0
is relaxed to 0x4X, where X represents the
condition code. */
code &= 0xf0;
code >>= 4;
code |= 0x40;
bfd_put_8 (abfd, code, contents + irel->r_offset - 2);
}
else if (code == 0x5c)
/* This is bsr. */
bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2);
else
abort ();
@ -1179,11 +1191,17 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
}
}
/* Fall through. */
/* Fall through. */
/* This is a 24-/32-bit absolute address in a "mov" insn,
which may become a 16-bit absolute address if it is in the
right range. */
/* This is a 24-/32-bit absolute address in one of the
following instructions:
"band", "bclr", "biand", "bild", "bior", "bist",
"bixor", "bld", "bnot", "bor", "bset", "bst", "btst",
"bxor", and "mov.[bwl]"
We may relax this into an 16-bit absolute address if it's
in the right range. */
case R_H8_DIR32A16:
{
bfd_vma value;
@ -1202,7 +1220,9 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
/* Get the opcode. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
/* We just need to turn off bit 0x20. */
/* Fix the opcode. For all the instructions that
belong to this relaxation, we simply need to turn
off bit 0x20 in the previous byte. */
code &= ~0x20;
bfd_put_8 (abfd, code, contents + irel->r_offset - 1);