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* simops.c: Add shift support.

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This commit is contained in:
Jeff Law 1996-08-29 22:29:41 +00:00
parent fb8eb42bd6
commit 775533747d
2 changed files with 59 additions and 25 deletions
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2
sim/v850/ChangeLog
View File

@ -1,5 +1,7 @@
Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Add shift support.
* simops.c: Add multiply & divide support. Abort for system
instructions.

82
sim/v850/simops.c
View File

@ -2,11 +2,6 @@
#include "v850_sim.h"
#include "simops.h"
void
OP_280 ()
{
}
void
OP_220 ()
{
@ -227,16 +222,6 @@ OP_40 ()
State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff);
}
void
OP_8007E0 ()
{
}
void
OP_C007E0 ()
{
}
void
OP_10720 ()
{
@ -257,11 +242,6 @@ OP_60 ()
{
}
void
OP_2A0 ()
{
}
void
OP_87C0 ()
{
@ -356,9 +336,66 @@ OP_20 ()
State.regs[OP[1]] = ~State.regs[OP[0]];
}
/* sar zero_extend(imm5),reg1
XXX condition codes. */
void
OP_2A0 ()
{
int temp = State.regs[OP[1]];
temp >>= (OP[0] & 0x1f);
State.regs[OP[1]] = temp;
}
/* sar reg1, reg2
XXX condition codes. */
void
OP_A007E0 ()
{
int temp = State.regs[OP[1]];
temp >>= (State.regs[OP[0]] & 0x1f);
State.regs[OP[1]] = temp;
}
/* shl zero_extend(imm5),reg1
XXX condition codes. */
void
OP_2C0 ()
{
State.regs[OP[1]] <<= (OP[0] & 0x1f);
}
/* shl reg1, reg2
XXX condition codes. */
void
OP_C007E0 ()
{
State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
}
/* shr zero_extend(imm5),reg1
XXX condition codes. */
void
OP_280 ()
{
State.regs[OP[1]] >>= (OP[0] & 0x1f);
}
/* shr reg1, reg2
XXX condition codes. */
void
OP_8007E0 ()
{
State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
}
void
@ -366,11 +403,6 @@ OP_500 ()
{
}
void
OP_2C0 ()
{
}
void
OP_47C0 ()
{