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sim: build: clean more generated outputs

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This commit is contained in:
Mike Frysinger 2024-01-08 20:27:23 -05:00
parent 4c68f4e386
commit 7531822f10
10 changed files with 147 additions and 125 deletions
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262
sim/Makefile.in
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@ -150,67 +150,74 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/run
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/gencode
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@am__append_18 = cris/libsim.a
@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/run
@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/rvdummy
@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = \
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/libsim.a
@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/run
@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/rvdummy
@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_23 = d10v/libsim.a
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_24 = d10v/run
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/gencode
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_28 = erc32/libsim.a
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_29 = erc32/run erc32/sis
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_30 = sim-%D-install-exec-local
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = sim-erc32-uninstall-local
@SIM_ENABLE_ARCH_examples_TRUE@am__append_32 = example-synacor/libsim.a
@SIM_ENABLE_ARCH_examples_TRUE@am__append_33 = example-synacor/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_34 = frv/libsim.a
@SIM_ENABLE_ARCH_frv_TRUE@am__append_35 = frv/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_36 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_38 = ft32/libsim.a
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_39 = ft32/run
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_40 = h8300/libsim.a
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_41 = h8300/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_42 = iq2000/libsim.a
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_43 = iq2000/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_44 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_46 = lm32/libsim.a
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_47 = lm32/run
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_48 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_49 = $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_50 = m32c/libsim.a
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_51 = m32c/run
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_52 = m32c/opc2c
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_53 = \
@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/engv10.h cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/libsim.a
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/run
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 = $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = erc32/libsim.a
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = erc32/run erc32/sis
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 = sim-%D-install-exec-local
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 = sim-erc32-uninstall-local
@SIM_ENABLE_ARCH_examples_TRUE@am__append_35 = example-synacor/libsim.a
@SIM_ENABLE_ARCH_examples_TRUE@am__append_36 = example-synacor/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/libsim.a
@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_42 = ft32/libsim.a
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 = ft32/run
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_44 = h8300/libsim.a
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 = h8300/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/libsim.a
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_49 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = lm32/libsim.a
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = lm32/run
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 = $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/libsim.a
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = m32c/run
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 = m32c/opc2c
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_59 = \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_54 = m32r/libsim.a
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_55 = m32r/run
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_56 = \
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = m32r/libsim.a
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = m32r/run
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_57 = $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_58 = m68hc11/libsim.a
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_59 = m68hc11/run
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_60 = m68hc11/gencode
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_61 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_62 = mcore/libsim.a
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_63 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_64 = microblaze/libsim.a
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_65 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_66 = \
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_63 = m32r/eng.h m32r/engx.h m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 = $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/libsim.a
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = m68hc11/run
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_67 = m68hc11/gencode
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_68 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_69 = mcore/libsim.a
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_70 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_71 = microblaze/libsim.a
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_72 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_73 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.o \
@ -219,7 +226,7 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_67 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_74 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o \
@ -233,35 +240,35 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_68 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_75 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
@SIM_ENABLE_ARCH_mips_TRUE@am__append_69 = mips/libsim.a
@SIM_ENABLE_ARCH_mips_TRUE@am__append_70 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_71 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/libsim.a
@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_72 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_79 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_73 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_80 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_74 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_81 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_77 = mn10300/libsim.a
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_78 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_79 = \
@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = mn10300/libsim.a
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@ -270,46 +277,47 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_80 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_81 = moxie/libsim.a
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_82 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_83 = msp430/libsim.a
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_84 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_85 = or1k/libsim.a
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_86 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_87 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_88 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_89 = ppc/libsim.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_90 = ppc/run
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_91 = ppc/defines.h ppc/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_88 = moxie/libsim.a
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_89 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_90 = msp430/libsim.a
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/libsim.a
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/libsim.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/run
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/defines.h ppc/icache.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h ppc/semantics.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h ppc/support.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h ppc/hw.h
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_92 = ppc/defines.h \
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = ppc/defines.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-defines \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_IGEN_TOOLS) ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_93 = ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_94 = $(ppc_IGEN_TOOLS)
@SIM_ENABLE_ARCH_pru_TRUE@am__append_95 = pru/libsim.a
@SIM_ENABLE_ARCH_pru_TRUE@am__append_96 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_97 = riscv/libsim.a
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_98 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_99 = rl78/libsim.a
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_100 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_101 = rx/libsim.a
@SIM_ENABLE_ARCH_rx_TRUE@am__append_102 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 = sh/libsim.a
@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = \
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_101 = ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_102 = $(ppc_IGEN_TOOLS)
@SIM_ENABLE_ARCH_pru_TRUE@am__append_103 = pru/libsim.a
@SIM_ENABLE_ARCH_pru_TRUE@am__append_104 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_105 = riscv/libsim.a
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_106 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_107 = rl78/libsim.a
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_108 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_109 = rx/libsim.a
@SIM_ENABLE_ARCH_rx_TRUE@am__append_110 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = sh/libsim.a
@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 = v850/libsim.a
@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 = \
@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = v850/libsim.a
@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_118 = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@ -318,7 +326,7 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 = $(v850_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_119 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
@ -727,8 +735,8 @@ am__DEPENDENCIES_1 =
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_66) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_67) \
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \
@ -1845,39 +1853,41 @@ GNULIB_PARENT_DIR = ..
srccom = $(srcdir)/common
srcroot = $(srcdir)/..
pkginclude_HEADERS = $(am__append_1)
EXTRA_LIBRARIES = igen/libigen.a $(am__append_93)
EXTRA_LIBRARIES = igen/libigen.a $(am__append_101)
noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \
$(am__append_7) $(am__append_9) $(am__append_11) \
$(am__append_13) $(am__append_18) $(am__append_23) \
$(am__append_28) $(am__append_32) $(am__append_34) \
$(am__append_38) $(am__append_40) $(am__append_42) \
$(am__append_46) $(am__append_50) $(am__append_54) \
$(am__append_58) $(am__append_62) $(am__append_64) \
$(am__append_69) $(am__append_77) $(am__append_81) \
$(am__append_83) $(am__append_85) $(am__append_89) \
$(am__append_95) $(am__append_97) $(am__append_99) \
$(am__append_101) $(am__append_103) $(am__append_108)
BUILT_SOURCES = $(am__append_15) $(am__append_21) $(am__append_25) \
$(am__append_36) $(am__append_44) $(am__append_48) \
$(am__append_56) $(am__append_71) $(am__append_79) \
$(am__append_87) $(am__append_91) $(am__append_105) \
$(am__append_110)
$(am__append_13) $(am__append_19) $(am__append_25) \
$(am__append_31) $(am__append_35) $(am__append_37) \
$(am__append_42) $(am__append_44) $(am__append_46) \
$(am__append_51) $(am__append_56) $(am__append_60) \
$(am__append_65) $(am__append_69) $(am__append_71) \
$(am__append_76) $(am__append_84) $(am__append_88) \
$(am__append_90) $(am__append_92) $(am__append_97) \
$(am__append_103) $(am__append_105) $(am__append_107) \
$(am__append_109) $(am__append_111) $(am__append_116)
BUILT_SOURCES = $(am__append_15) $(am__append_22) $(am__append_27) \
$(am__append_39) $(am__append_48) $(am__append_53) \
$(am__append_62) $(am__append_78) $(am__append_86) \
$(am__append_94) $(am__append_99) $(am__append_113) \
$(am__append_118)
CLEANFILES = common/version.c common/version.c-stamp \
testsuite/common/bits-gen testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
testsuite/common/bits64m63.c
DISTCLEANFILES = $(am__append_76)
testsuite/common/bits64m63.c $(am__append_17) $(am__append_23) \
$(am__append_29) $(am__append_40) $(am__append_49) \
$(am__append_54) $(am__append_63) $(am__append_95)
DISTCLEANFILES = $(am__append_83)
MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \
$(SIM_ENABLED_ARCHES:%=%/hw-config.h) \
$(SIM_ENABLED_ARCHES:%=%/stamp-hw) \
$(SIM_ENABLED_ARCHES:%=%/modules.c) \
$(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \
igen/libigen.a site-sim-config.exp testrun.log testrun.sum \
$(am__append_17) $(am__append_22) $(am__append_27) \
$(am__append_37) $(am__append_45) $(am__append_49) \
$(am__append_53) $(am__append_57) $(am__append_61) \
$(am__append_75) $(am__append_80) $(am__append_88) \
$(am__append_92) $(am__append_107) $(am__append_111)
$(am__append_18) $(am__append_24) $(am__append_30) \
$(am__append_41) $(am__append_50) $(am__append_55) \
$(am__append_59) $(am__append_64) $(am__append_68) \
$(am__append_82) $(am__append_87) $(am__append_96) \
$(am__append_100) $(am__append_115) $(am__append_119)
CONFIG_STATUS_DEPENDENCIES = $(srcroot)/bfd/development.sh
AM_CFLAGS = \
$(WERROR_CFLAGS) \
@ -1894,8 +1904,8 @@ AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_INSTALL_DATA_LOCAL_DEPS =
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_30)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_31)
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_33)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_34)
SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
SIM_COMPILE = \
$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \
@ -2694,8 +2704,8 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_66) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_67) $(am__append_68)
@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c
@ -2767,8 +2777,8 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74)
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@ -3164,6 +3174,8 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_sh_TRUE@sh_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.c
@SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c

1
sim/cr16/local.mk
View File

@ -74,4 +74,5 @@ BUILT_SOURCES += %D%/simops.h
$(AM_V_GEN)$< >$@
EXTRA_PROGRAMS += %D%/gencode
CLEANFILES += %D%/simops.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)

1
sim/cris/local.mk
View File

@ -112,6 +112,7 @@ BUILT_SOURCES += \
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop-v32f.cin %D%/mloopv32f.c
$(AM_V_at)touch $@
CLEANFILES += %D%/engv10.h %D%/engv32.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
## Target that triggers all cgen targets that works when --disable-cgen-maint.

1
sim/d10v/local.mk
View File

@ -75,4 +75,5 @@ BUILT_SOURCES += %D%/simops.h
$(AM_V_GEN)$< >$@
EXTRA_PROGRAMS += %D%/gencode
CLEANFILES += %D%/simops.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)

1
sim/frv/local.mk
View File

@ -99,6 +99,7 @@ BUILT_SOURCES += %D%/eng.h
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop.cin %D%/mloop.c
$(AM_V_at)touch $@
CLEANFILES += %D%/eng.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
## Target that triggers all cgen targets that works when --disable-cgen-maint.

1
sim/iq2000/local.mk
View File

@ -75,6 +75,7 @@ BUILT_SOURCES += %D%/eng.h
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop.cin %D%/mloop.c
$(AM_V_at)touch $@
CLEANFILES += %D%/eng.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
## Target that triggers all cgen targets that works when --disable-cgen-maint.

1
sim/lm32/local.mk
View File

@ -80,6 +80,7 @@ BUILT_SOURCES += %D%/eng.h
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop.cin %D%/mloop.c
$(AM_V_at)touch $@
CLEANFILES += %D%/eng.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
## Target that triggers all cgen targets that works when --disable-cgen-maint.

1
sim/m32r/local.mk
View File

@ -122,6 +122,7 @@ BUILT_SOURCES += \
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop2.cin %D%/mloop2.c
$(AM_V_at)touch $@
CLEANFILES += %D%/eng.h %D%/engx.h %D%/eng2.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
## Target that triggers all cgen targets that works when --disable-cgen-maint.

1
sim/or1k/local.mk
View File

@ -82,6 +82,7 @@ BUILT_SOURCES += %D%/eng.h
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop.cin %D%/mloop.c
$(AM_V_at)touch $@
CLEANFILES += %D%/eng.h
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
## Target that triggers all cgen targets that works when --disable-cgen-maint.

2
sim/sh/local.mk
View File

@ -51,6 +51,8 @@ BUILT_SOURCES += \
%D%/ppi.c
%C%_BUILD_OUTPUTS = \
%D%/gencode$(EXEEXT) \
%D%/code.c \
%D%/ppi.c \
%D%/table.c
## Generating modules.c requires all sources to scan.