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Add self to aarch64 maintainers. Fix mla instruction.
sim/ * MAINTAINTERS (aarch64): Add myself. sim/aarch64/ * simulator.c (do_vec_MLA): Rewrite switch body. sim/testsuite/sim/aarch64/ * mla.s: New.
This commit is contained in:
Jim Wilson
parent
bf25e9a0f1
commit
742e3a7781
@ -1,3 +1,7 @@
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2017-02-14 Jim Wilson <jim.wilson@linaro.org>
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* MAINTAINTERS (aarch64): Add myself.
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2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
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* MAINTAINERS (Maintainers for particular sims): Add myself as
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@ -14,6 +14,7 @@ Mike Frysinger vapier@gentoo.org
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Maintainers for particular sims:
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aarch64 Nick Clifton <nickc@redhat.com>
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aarch64 Jim Wilson <jim.wilson@linaro.org>
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arm Nick Clifton <nickc@redhat.com>
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bfin Mike Frysinger <vapier@gentoo.org>
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cr16 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
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@ -1,5 +1,7 @@
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2017-02-14 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_MLA): Rewrite switch body.
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* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
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2. Move test_false if inside loop. Fix logic for computing result
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stored to vd.
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@ -3799,63 +3799,30 @@ do_vec_MLA (sim_cpu *cpu)
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switch (INSTR (23, 22))
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{
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case 0:
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{
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uint16_t a[16], b[16];
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for (i = 0; i < (full ? 16 : 8); i++)
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{
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a[i] = aarch64_get_vec_u8 (cpu, vn, i);
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b[i] = aarch64_get_vec_u8 (cpu, vm, i);
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}
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for (i = 0; i < (full ? 16 : 8); i++)
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{
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uint16_t v = aarch64_get_vec_u8 (cpu, vd, i);
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aarch64_set_vec_u16 (cpu, vd, i, v + (a[i] * b[i]));
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}
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}
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for (i = 0; i < (full ? 16 : 8); i++)
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aarch64_set_vec_u8 (cpu, vd, i,
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aarch64_get_vec_u8 (cpu, vd, i)
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+ (aarch64_get_vec_u8 (cpu, vn, i)
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* aarch64_get_vec_u8 (cpu, vm, i)));
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return;
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case 1:
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{
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uint32_t a[8], b[8];
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for (i = 0; i < (full ? 8 : 4); i++)
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{
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a[i] = aarch64_get_vec_u16 (cpu, vn, i);
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b[i] = aarch64_get_vec_u16 (cpu, vm, i);
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}
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for (i = 0; i < (full ? 8 : 4); i++)
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{
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uint32_t v = aarch64_get_vec_u16 (cpu, vd, i);
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aarch64_set_vec_u32 (cpu, vd, i, v + (a[i] * b[i]));
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}
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}
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for (i = 0; i < (full ? 8 : 4); i++)
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aarch64_set_vec_u16 (cpu, vd, i,
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aarch64_get_vec_u16 (cpu, vd, i)
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+ (aarch64_get_vec_u16 (cpu, vn, i)
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* aarch64_get_vec_u16 (cpu, vm, i)));
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return;
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case 2:
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{
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uint64_t a[4], b[4];
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for (i = 0; i < (full ? 4 : 2); i++)
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{
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a[i] = aarch64_get_vec_u32 (cpu, vn, i);
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b[i] = aarch64_get_vec_u32 (cpu, vm, i);
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}
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for (i = 0; i < (full ? 4 : 2); i++)
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{
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uint64_t v = aarch64_get_vec_u32 (cpu, vd, i);
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aarch64_set_vec_u64 (cpu, vd, i, v + (a[i] * b[i]));
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}
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}
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for (i = 0; i < (full ? 4 : 2); i++)
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aarch64_set_vec_u32 (cpu, vd, i,
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aarch64_get_vec_u32 (cpu, vd, i)
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+ (aarch64_get_vec_u32 (cpu, vn, i)
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* aarch64_get_vec_u32 (cpu, vm, i)));
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return;
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case 3:
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default:
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HALT_UNALLOC;
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}
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}
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@ -1,5 +1,7 @@
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2017-02-14 Jim Wilson <jim.wilson@linaro.org>
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* mla.s: New.
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* bit.s: New.
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* ldn_single.s: New.
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103
sim/testsuite/sim/aarch64/mla.s
Normal file
103
sim/testsuite/sim/aarch64/mla.s
Normal file
@ -0,0 +1,103 @@
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# mach: aarch64
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# Check the vector multiply add instruction: mla.
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.include "testutils.inc"
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input:
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.word 0x04030201
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.word 0x08070605
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.word 0x0c0b0a09
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.word 0x100f0e0d
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m8b:
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.word 0x110a0502
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.word 0x4132251a
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m16b:
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.word 0x110a0502
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.word 0x4132251a
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.word 0x917a6552
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.word 0x01e2c5aa
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m4h:
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.word 0x180a0402
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.word 0x70323c1a
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m8h:
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.word 0x180a0402
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.word 0x70323c1a
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.word 0x087ab452
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.word 0xe0e26caa
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m2s:
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.word 0x140a0402
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.word 0xa46a3c1a
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m4s:
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.word 0x140a0402
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.word 0xa46a3c1a
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.word 0xb52ab452
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.word 0x464b6caa
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start
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adrp x0, input
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ldr q0, [x0, #:lo12:input]
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movi v1.8b, #1
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mla v1.8b, v0.8b, v0.8b
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mov x1, v1.d[0]
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adrp x3, m8b
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ldr x4, [x3, #:lo12:m8b]
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cmp x1, x4
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bne .Lfailure
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movi v1.16b, #1
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mla v1.16b, v0.16b, v0.16b
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mov x1, v1.d[0]
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mov x2, v1.d[1]
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adrp x3, m16b
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ldr x4, [x3, #:lo12:m16b]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:m16b+8]
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cmp x2, x5
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bne .Lfailure
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movi v1.4h, #1
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mla v1.4h, v0.4h, v0.4h
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mov x1, v1.d[0]
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adrp x3, m4h
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ldr x4, [x3, #:lo12:m4h]
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cmp x1, x4
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bne .Lfailure
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movi v1.8h, #1
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mla v1.8h, v0.8h, v0.8h
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mov x1, v1.d[0]
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mov x2, v1.d[1]
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adrp x3, m8h
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ldr x4, [x3, #:lo12:m8h]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:m8h+8]
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cmp x2, x5
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bne .Lfailure
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movi v1.2s, #1
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mla v1.2s, v0.2s, v0.2s
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mov x1, v1.d[0]
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adrp x3, m2s
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ldr x4, [x3, #:lo12:m2s]
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cmp x1, x4
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bne .Lfailure
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movi v1.4s, #1
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mla v1.4s, v0.4s, v0.4s
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mov x1, v1.d[0]
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mov x2, v1.d[1]
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adrp x3, m4s
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ldr x4, [x3, #:lo12:m4s]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:m4s+8]
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cmp x2, x5
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bne .Lfailure
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pass
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.Lfailure:
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fail
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