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aarch64: add Branch Record Buffer extension instructions

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The FEAT_BRBE extension provides two aliases of sys:
- brb iall (Invalidates all Branch records in the Branch Record Buffer)
- brb inj (Injects the Branch Record held in BRBINFINJ_EL1,
  BRBSRCINJ_EL1, and BRBTGTINJ_EL1 into the Branch Record Buffer)

This patch adds:
- the feature option "brbe" that must be added for the aliases to be available
- a new operand flag AARCH64_OPND_Rt_IN_SYS_ALIASES that warns in a comment
  when Rt is set to the non default value 0b11111 (it is constrained
  unpredictable whether the instruction is undefined or behaves as if the Rt
  field is set to 0b11111).
- a new operand flag AARCH64_OPND_BRBOP that encodes and decodes Op2 values
  from bit 5
- support for the two brb aliases above

See:
- https://developer.arm.com/documentation/ddi0602/2024-03/Base-Instructions/BRB--Branch-Record-Buffer--an-alias-of-SYS-?lang=en
- https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-INJ--Branch-Record-Injection-into-the-Branch-Record-Buffer?lang=en
- https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-IALL--Invalidate-the-Branch-Record-Buffer?lang=en
This commit is contained in:
Claudio Bantaloukas 2024-06-07 13:59:02 +00:00 committed by Richard Earnshaw
parent 292b9a3029
commit 72476aca8f
18 changed files with 2576 additions and 2459 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gas/config/tc-aarch64.c
View File

@ -6235,6 +6235,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_Rs:
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_Rt_IN_SYS_ALIASES:
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_Rm_SP:
@ -6619,6 +6620,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_LS64:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_Rt_IN_SYS_ALIASES:
case AARCH64_OPND_PAIRREG:
case AARCH64_OPND_PAIRREG_OR_XZR:
case AARCH64_OPND_SVE_Rm:
@ -8076,6 +8078,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
info->imm.value = val;
break;
case AARCH64_OPND_BRBOP:
po_strict_enum_or_fail (aarch64_brbop_array);
info->imm.value = val;
break;
case AARCH64_OPND_MOPS_ADDR_Rd:
case AARCH64_OPND_MOPS_ADDR_Rs:
po_char_or_fail ('[');
@ -10589,6 +10596,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"faminmax", AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)},
{"fp8", AARCH64_FEATURE (FP8), AARCH64_FEATURE (SIMD)},
{"lut", AARCH64_FEATURE (LUT), AARCH64_FEATURE (SIMD)},
{"brbe", AARCH64_FEATURE (BRBE), AARCH64_NO_FEATURES},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};

2
gas/doc/c-aarch64.texi
View File

@ -165,6 +165,8 @@ automatically cause those extensions to be disabled.
@tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
@item @code{bf16} @tab @code{fp}
@tab Enable BFloat16 extension.
@item @code{brbe} @tab
@tab Enable the Branch Record Buffer extension.
@item @code{chk} @tab
@tab Enable the Check Feature Status Extension.
@item @code{compnum} @tab @code{simd}

2
gas/testsuite/gas/aarch64/brbe-brb-bad.d Normal file
View File

@ -0,0 +1,2 @@
#as: -march=armv9.1-a+brbe
#error_output: brbe-brb-bad.l

4
gas/testsuite/gas/aarch64/brbe-brb-bad.l Normal file
View File

@ -0,0 +1,4 @@
.*: Assembler messages:
.*: Error: operand 1 must be Branch Record Buffer operation operand -- `brb foobar'
.*: Error: operand 1 must be Branch Record Buffer operation operand -- `brb #123'
.*: Error: operand 1 must be Branch Record Buffer operation operand -- `brb'

6
gas/testsuite/gas/aarch64/brbe-brb-bad.s Normal file
View File

@ -0,0 +1,6 @@
/* brb only accepts iall and inj as arguments */
.text
brb foobar
brb #123
brb

14
gas/testsuite/gas/aarch64/brbe-brb-inst.d Normal file
View File

@ -0,0 +1,14 @@
#as: -march=armv9.1-a+brbe
#objdump: -dr
# This test is only valid on ELF based ports.
#notarget: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d509729f brb iall
.*: d509729e brb iall // unpredictable encoding \(Rt!=31\): #30
.*: d50972bf brb inj
.*: d50972be brb inj // unpredictable encoding \(Rt!=31\): #30

5
gas/testsuite/gas/aarch64/brbe-brb-inst.s Normal file
View File

@ -0,0 +1,5 @@
.text
.inst 0xd509729f // brb iall
.inst 0xd509729e // brb iall with non default Rt
.inst 0xd50972bf // brb inj
.inst 0xd50972be // brb inj with non default Rt

3
gas/testsuite/gas/aarch64/brbe-brb-invalid.d Normal file
View File

@ -0,0 +1,3 @@
#as: -march=armv9.1-a
#source: brbe-brb.s
#error_output: brbe-brb-invalid.l

3
gas/testsuite/gas/aarch64/brbe-brb-invalid.l Normal file
View File

@ -0,0 +1,3 @@
.*: Assembler messages:
.*: Error: selected processor does not support `brb iall'
.*: Error: selected processor does not support `brb inj'

12
gas/testsuite/gas/aarch64/brbe-brb.d Normal file
View File

@ -0,0 +1,12 @@
#as: -march=armv9.1-a+brbe
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d509729f brb iall
.*: d509729f brb iall
.*: d50972bf brb inj
.*: d50972bf brb inj

5
gas/testsuite/gas/aarch64/brbe-brb.s Normal file
View File

@ -0,0 +1,5 @@
.text
brb iall
.inst 0xd509729f // brb iall
brb inj
.inst 0xd50972bf // brb inj

7
include/opcode/aarch64.h
View File

@ -238,6 +238,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FP8,
/* LUT instructions. */
AARCH64_FEATURE_LUT,
/* Branch Record Buffer Extension */
AARCH64_FEATURE_BRBE,
AARCH64_NUM_FEATURES
};
@ -625,6 +627,8 @@ enum aarch64_opnd
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
AARCH64_OPND_BRBOP, /* BRB operation IALL or INJ in bit 5. */
AARCH64_OPND_Rt_IN_SYS_ALIASES, /* Defaulted and omitted Rt used in SYS aliases such as brb. */
AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */
AARCH64_OPND_LSE128_Rt2, /* LSE128 <Xt2>. */
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
@ -822,7 +826,7 @@ enum aarch64_opnd
AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */
AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */
AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [<Xn|SP>, #<imm>]!. */
AARCH64_OPND_RCPC3_ADDR_OFFSET
AARCH64_OPND_RCPC3_ADDR_OFFSET,
};
/* Qualifier constrains an operand. It either specifies a variant of an
@ -1918,6 +1922,7 @@ extern const char *const aarch64_sve_pattern_array[32];
extern const char *const aarch64_sve_prfop_array[16];
extern const char *const aarch64_rprfmop_array[64];
extern const char *const aarch64_sme_vlxn_array[2];
extern const char *const aarch64_brbop_array[2];
#ifdef __cplusplus
}

375
opcodes/aarch64-asm-2.c
View File

@ -426,15 +426,15 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1218: /* movz */
value = 1218; /* --> movz. */
break;
case 3215: /* clrbhb */
case 1298: /* autibsp */
case 1297: /* autibz */
case 1296: /* autiasp */
case 1295: /* autiaz */
case 1294: /* pacibsp */
case 1293: /* pacibz */
case 1292: /* paciasp */
case 1291: /* paciaz */
case 3216: /* clrbhb */
case 1299: /* autibsp */
case 1298: /* autibz */
case 1297: /* autiasp */
case 1296: /* autiaz */
case 1295: /* pacibsp */
case 1294: /* pacibz */
case 1293: /* paciasp */
case 1292: /* paciaz */
case 1271: /* gcsb */
case 1251: /* clearbhb */
case 1250: /* tsb */
@ -465,7 +465,8 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1254: /* dsb */
value = 1254; /* --> dsb. */
break;
case 3216: /* trcit */
case 3217: /* trcit */
case 1285: /* brb */
case 1284: /* cosp */
case 1283: /* cpp */
case 1282: /* dvp */
@ -487,126 +488,126 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1280: /* wfit */
value = 1280; /* --> wfit. */
break;
case 2100: /* bic */
case 1347: /* and */
value = 1347; /* --> and. */
case 2101: /* bic */
case 1348: /* and */
value = 1348; /* --> and. */
break;
case 1330: /* mov */
case 1349: /* and */
value = 1349; /* --> and. */
case 1331: /* mov */
case 1350: /* and */
value = 1350; /* --> and. */
break;
case 1334: /* movs */
case 1350: /* ands */
value = 1350; /* --> ands. */
case 1335: /* movs */
case 1351: /* ands */
value = 1351; /* --> ands. */
break;
case 2101: /* cmple */
case 1385: /* cmpge */
value = 1385; /* --> cmpge. */
case 2102: /* cmple */
case 1386: /* cmpge */
value = 1386; /* --> cmpge. */
break;
case 2104: /* cmplt */
case 1388: /* cmpgt */
value = 1388; /* --> cmpgt. */
case 2105: /* cmplt */
case 1389: /* cmpgt */
value = 1389; /* --> cmpgt. */
break;
case 2102: /* cmplo */
case 1390: /* cmphi */
value = 1390; /* --> cmphi. */
case 2103: /* cmplo */
case 1391: /* cmphi */
value = 1391; /* --> cmphi. */
break;
case 2103: /* cmpls */
case 1393: /* cmphs */
value = 1393; /* --> cmphs. */
case 2104: /* cmpls */
case 1394: /* cmphs */
value = 1394; /* --> cmphs. */
break;
case 1327: /* mov */
case 1415: /* cpy */
value = 1415; /* --> cpy. */
break;
case 1329: /* mov */
case 1328: /* mov */
case 1416: /* cpy */
value = 1416; /* --> cpy. */
break;
case 2111: /* fmov */
case 1332: /* mov */
case 1330: /* mov */
case 1417: /* cpy */
value = 1417; /* --> cpy. */
break;
case 1321: /* mov */
case 1429: /* dup */
value = 1429; /* --> dup. */
case 2112: /* fmov */
case 1333: /* mov */
case 1418: /* cpy */
value = 1418; /* --> cpy. */
break;
case 1324: /* mov */
case 1320: /* mov */
case 1322: /* mov */
case 1430: /* dup */
value = 1430; /* --> dup. */
break;
case 2110: /* fmov */
case 1326: /* mov */
case 1325: /* mov */
case 1321: /* mov */
case 1431: /* dup */
value = 1431; /* --> dup. */
break;
case 1325: /* mov */
case 1432: /* dupm */
value = 1432; /* --> dupm. */
case 2111: /* fmov */
case 1327: /* mov */
case 1432: /* dup */
value = 1432; /* --> dup. */
break;
case 2105: /* eon */
case 1434: /* eor */
value = 1434; /* --> eor. */
case 1326: /* mov */
case 1433: /* dupm */
value = 1433; /* --> dupm. */
break;
case 1335: /* not */
case 1436: /* eor */
value = 1436; /* --> eor. */
case 2106: /* eon */
case 1435: /* eor */
value = 1435; /* --> eor. */
break;
case 1336: /* nots */
case 1437: /* eors */
value = 1437; /* --> eors. */
case 1336: /* not */
case 1437: /* eor */
value = 1437; /* --> eor. */
break;
case 2106: /* facle */
case 1442: /* facge */
value = 1442; /* --> facge. */
case 1337: /* nots */
case 1438: /* eors */
value = 1438; /* --> eors. */
break;
case 2107: /* faclt */
case 1443: /* facgt */
value = 1443; /* --> facgt. */
case 2107: /* facle */
case 1443: /* facge */
value = 1443; /* --> facge. */
break;
case 2108: /* fcmle */
case 1456: /* fcmge */
value = 1456; /* --> fcmge. */
case 2108: /* faclt */
case 1444: /* facgt */
value = 1444; /* --> facgt. */
break;
case 2109: /* fcmlt */
case 1458: /* fcmgt */
value = 1458; /* --> fcmgt. */
case 2109: /* fcmle */
case 1457: /* fcmge */
value = 1457; /* --> fcmge. */
break;
case 2110: /* fcmlt */
case 1459: /* fcmgt */
value = 1459; /* --> fcmgt. */
break;
case 1319: /* fmov */
case 1465: /* fcpy */
value = 1465; /* --> fcpy. */
break;
case 1318: /* fmov */
case 1464: /* fcpy */
value = 1464; /* --> fcpy. */
case 1488: /* fdup */
value = 1488; /* --> fdup. */
break;
case 1317: /* fmov */
case 1487: /* fdup */
value = 1487; /* --> fdup. */
break;
case 1319: /* mov */
case 1819: /* orr */
value = 1819; /* --> orr. */
break;
case 2112: /* orn */
case 1320: /* mov */
case 1820: /* orr */
value = 1820; /* --> orr. */
break;
case 2113: /* orn */
case 1821: /* orr */
value = 1821; /* --> orr. */
break;
case 1324: /* mov */
case 1323: /* mov */
case 1322: /* mov */
case 1822: /* orr */
value = 1822; /* --> orr. */
case 1823: /* orr */
value = 1823; /* --> orr. */
break;
case 1333: /* movs */
case 1823: /* orrs */
value = 1823; /* --> orrs. */
case 1334: /* movs */
case 1824: /* orrs */
value = 1824; /* --> orrs. */
break;
case 1328: /* mov */
case 1886: /* sel */
value = 1886; /* --> sel. */
break;
case 1331: /* mov */
case 1329: /* mov */
case 1887: /* sel */
value = 1887; /* --> sel. */
break;
case 1332: /* mov */
case 1888: /* sel */
value = 1888; /* --> sel. */
break;
default: return NULL;
}
@ -650,10 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
case 121:
case 122:
case 180:
case 181:
case 123:
case 124:
case 182:
case 183:
case 184:
@ -666,30 +666,32 @@ aarch64_insert_operand (const aarch64_operand *self,
case 191:
case 192:
case 193:
case 208:
case 209:
case 194:
case 195:
case 210:
case 211:
case 220:
case 221:
case 212:
case 213:
case 222:
case 223:
case 224:
case 235:
case 239:
case 243:
case 250:
case 251:
case 258:
case 259:
case 225:
case 226:
case 237:
case 241:
case 245:
case 252:
case 253:
case 260:
case 261:
case 262:
case 263:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 118:
case 119:
case 293:
case 295:
case 297:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -703,18 +705,16 @@ aarch64_insert_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
case 297:
case 299:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 39:
case 40:
case 41:
case 225:
case 226:
case 229:
case 262:
case 263:
case 278:
case 279:
case 227:
case 228:
case 231:
case 264:
case 265:
case 280:
case 281:
case 282:
@ -726,6 +726,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 288:
case 289:
case 290:
case 291:
case 292:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 42:
return aarch64_ins_reglist (self, info, code, inst, errors);
@ -763,23 +765,24 @@ aarch64_insert_operand (const aarch64_operand *self,
case 90:
case 91:
case 117:
case 177:
case 121:
case 179:
case 200:
case 201:
case 181:
case 202:
case 203:
case 204:
case 205:
case 206:
case 207:
case 264:
case 291:
case 292:
case 208:
case 209:
case 266:
case 293:
case 294:
case 296:
case 301:
case 302:
case 298:
case 303:
case 304:
return aarch64_ins_imm (self, info, code, inst, errors);
case 51:
case 52:
@ -789,10 +792,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 55:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 59:
case 167:
case 169:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 77:
case 175:
case 177:
return aarch64_ins_limm (self, info, code, inst, errors);
case 78:
return aarch64_ins_aimm (self, info, code, inst, errors);
@ -802,11 +805,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 82:
case 83:
case 172:
case 174:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 84:
case 171:
case 173:
case 175:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 85:
case 86:
@ -851,25 +854,23 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_prfop (self, info, code, inst, errors);
case 120:
return aarch64_ins_hint (self, info, code, inst, errors);
case 123:
case 124:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 125:
case 126:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 127:
case 128:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 129:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 130:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 131:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 132:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 133:
case 134:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 135:
case 136:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 137:
case 138:
case 139:
@ -883,125 +884,127 @@ aarch64_insert_operand (const aarch64_operand *self,
case 147:
case 148:
case 149:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 150:
case 151:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 152:
case 153:
case 154:
case 155:
case 156:
case 157:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 158:
case 159:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 160:
case 161:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 162:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 163:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 164:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 165:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 166:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 167:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 168:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 169:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 170:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 171:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 172:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 174:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 176:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 178:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 180:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 194:
case 195:
case 196:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 197:
case 198:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 199:
case 277:
case 200:
case 201:
case 279:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 212:
case 213:
case 214:
case 215:
return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 216:
case 217:
return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 218:
case 219:
case 220:
case 221:
return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
case 227:
case 228:
case 229:
case 230:
case 231:
case 232:
case 233:
case 234:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 235:
case 236:
return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
case 237:
return aarch64_ins_sve_index (self, info, code, inst, errors);
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 238:
return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
case 239:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 240:
case 257:
case 303:
case 304:
case 305:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 241:
case 242:
case 259:
case 305:
case 306:
case 307:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 243:
case 244:
case 245:
case 246:
case 247:
case 256:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 248:
case 249:
case 258:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 250:
case 251:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 252:
case 254:
case 265:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 253:
case 255:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 266:
case 256:
case 267:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 255:
case 257:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 268:
case 269:
case 270:
case 271:
case 272:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 273:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 274:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 275:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 276:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 277:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 278:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case 298:
case 299:
case 300:
case 301:
case 302:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
case 306:
case 307:
case 308:
case 309:
return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 310:
case 311:
return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 312:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}

4531
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

18
opcodes/aarch64-opc-2.c
View File

@ -145,6 +145,8 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_GCSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the GCSB option name DSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BTI_TARGET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
{AARCH64_OPND_CLASS_SYSTEM, "BRBOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_brbop}, "Branch Record Buffer operation operand"},
{AARCH64_OPND_CLASS_INT_REG, "Rt_IN_SYS_ALIASES", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "Rt register with defaults for SYS aliases"},
{AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_LSE128_Rt}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_LSE128_Rt2}, "an integer register"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
@ -412,18 +414,18 @@ static const unsigned op_enum_table [] =
391,
413,
415,
1322,
1323,
1328,
1320,
1319,
1324,
1331,
1333,
1329,
1321,
1320,
1325,
1332,
1334,
1330,
1336,
1335,
1331,
1337,
1336,
131,
};

24
opcodes/aarch64-opc.c
View File

@ -117,6 +117,12 @@ const char *const aarch64_sme_vlxn_array[2] = {
"vlx4"
};
/* Values accepted by the brb alias. */
const char *const aarch64_brbop_array[] = {
"iall",
"inj",
};
/* Helper functions to determine which operand to be used to encode/decode
the size:Q fields for AdvSIMD instructions. */
@ -418,6 +424,7 @@ const aarch64_field fields[] =
{ 6, 1 }, /* ZAn: name of the bit encoded ZA tile. */
{ 12, 4 }, /* opc2: in rcpc3 ld/st inst deciding the pre/post-index. */
{ 30, 2 }, /* rcpc3_size: in rcpc3 ld/st, field controls Rt/Rt2 width. */
{ 5, 1 }, /* FLD_brbop: used in BRB to mean IALL or INJ. */
};
enum aarch64_operand_class
@ -3958,6 +3965,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Rt2:
case AARCH64_OPND_Rs:
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_IN_SYS_ALIASES:
case AARCH64_OPND_Rt_LS64:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
@ -3973,6 +3981,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
if (!opnd->present)
break;
}
else if ((opnd->type == AARCH64_OPND_Rt_IN_SYS_ALIASES)
&& (opnd->reg.regno
!= get_optional_operand_default_value (opcode)))
{
/* Avoid printing an invalid additional value for Rt in SYS aliases such as
BRB, provide a helpful comment instead */
snprintf (comment, comment_size, "unpredictable encoding (Rt!=31): #%" PRIi64, opnd->imm.value);
break;
}
/* Omit the operand, e.g. RET. */
else if (optional_operand_p (opcode, idx)
&& (opnd->reg.regno
@ -4355,6 +4372,13 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
style_sub_mnem (styler, aarch64_sme_vlxn_array[enum_value]));
break;
case AARCH64_OPND_BRBOP:
enum_value = opnd->imm.value;
assert (enum_value < ARRAY_SIZE (aarch64_brbop_array));
snprintf (buf, size, "%s",
style_sub_mnem (styler, aarch64_brbop_array[enum_value]));
break;
case AARCH64_OPND_CRn:
case AARCH64_OPND_CRm:
snprintf (buf, size, "%s",

1
opcodes/aarch64-opc.h
View File

@ -225,6 +225,7 @@ enum aarch64_field_kind
FLD_ZAn,
FLD_opc2,
FLD_rcpc3_size,
FLD_brbop,
};
/* Field description. */

15
opcodes/aarch64-tbl.h
View File

@ -100,6 +100,11 @@
QLF1(NIL), \
}
#define QL_IMM_NIL_NIL \
{ \
QLF2(NIL, NIL), \
}
/* e.g. B.<cond> <label>. */
#define QL_PCREL_NIL \
{ \
@ -2745,6 +2750,8 @@ static const aarch64_feature_set aarch64_feature_lut =
AARCH64_FEATURE (LUT);
static const aarch64_feature_set aarch64_feature_lut_sve2 =
AARCH64_FEATURES (2, LUT, SVE2);
static const aarch64_feature_set aarch64_feature_brbe =
AARCH64_FEATURE (BRBE);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@ -2821,6 +2828,7 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 =
#define FP8_SME2 &aarch64_feature_fp8_sme2
#define LUT &aarch64_feature_lut
#define LUT_SVE2 &aarch64_feature_lut_sve2
#define BRBE &aarch64_feature_brbe
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@ -3019,6 +3027,8 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 =
#define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \
{ NAME, OPCODE, MASK, lut, 0, LUT_SVE2, OPS, QUALS, \
FLAGS, CONSTRAINTS, 0, NULL }
#define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@ -4443,6 +4453,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
PREDRES2_INSN ("cosp", 0xd50b73c0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
BRBE_INSN ("brb", 0xd5097280, 0xffffffc0, OP2 (BRBOP, Rt_IN_SYS_ALIASES), QL_IMM_NIL_NIL, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
/* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr
below it. Usually we can resolve this by setting an alias condition on the flags, however that
depends on the disassembly masks to be able to quickly find the alias. The problem is the
@ -6836,6 +6847,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"the GCSB option name DSYNC") \
Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \
"BTI targets j/c/jc") \
Y(SYSTEM, imm, "BRBOP", 0, F(FLD_brbop), \
"Branch Record Buffer operation operand") \
Y(INT_REG, regno, "Rt_IN_SYS_ALIASES", 0, F(FLD_Rt), \
"Rt register with defaults for SYS aliases") \
Y(INT_REG, regno, "LSE128_Rt", 0, F(FLD_LSE128_Rt), "an integer register") \
Y(INT_REG, regno, "LSE128_Rt2", 0, F(FLD_LSE128_Rt2), "an integer register") \
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \