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opcodes/
* mips-opc.c (mips_builtin_opcodes): Move coprocessor 2 move/branch operations to the bottom so that VR5400 multimedia instructions take precedence in disassembly. gas/testsuite/ * gas/mips/vr5400.d: Update for a correct disassembly of "racm.ob".
This commit is contained in:
Maciej W. Rozycki
parent
01a3f561ab
commit
6f14957b2c
@ -1,3 +1,8 @@
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2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
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* gas/mips/vr5400.d: Update for a correct disassembly of
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"racm.ob".
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2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
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* gas/mips/mips32.s: Adjust for the unified "break" syntax. Add
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@ -119,7 +119,7 @@ Disassembly of section \.text:
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0+01bc <stuff\+0x1bc> rzu\.ob \$f2,0xd
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0+01c0 <stuff\+0x1c0> rach\.ob \$f2
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0+01c4 <stuff\+0x1c4> racl\.ob \$f2
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0+01c8 <stuff\+0x1c8> bc2f 0+04c8 <stuff\+0x4c8>
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0+01c8 <stuff\+0x1c8> racm\.ob \$f2
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0+01cc <stuff\+0x1cc> wach\.ob \$f2
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0+01d0 <stuff\+0x1d0> wacl\.ob \$f2,\$f4
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0+01d4 <stuff\+0x1d4> rorv a0,a1,a2
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@ -1,3 +1,9 @@
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2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
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* mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
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move/branch operations to the bottom so that VR5400 multimedia
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instructions take precedence in disassembly.
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2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
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* mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
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@ -209,10 +209,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
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{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
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{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
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{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
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/* bc2* are at the bottom of the table. */
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{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
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@ -443,14 +440,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
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{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
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{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
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{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
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/* cfc2 is at the bottom of the table. */
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{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
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{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
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{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
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{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
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{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
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{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
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{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
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/* ctc2 is at the bottom of the table. */
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{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
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{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
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{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
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@ -539,10 +536,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
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{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
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{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
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{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 },
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{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 },
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{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 },
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{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 },
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/* dmfc2 is at the bottom of the table. */
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/* dmtc2 is at the bottom of the table. */
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{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 },
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{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 },
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{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 },
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@ -740,9 +735,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
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{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
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{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
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{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
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{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
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{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 },
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/* mfc2 is at the bottom of the table. */
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/* mfhc2 is at the bottom of the table. */
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{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
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{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
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{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, N5 },
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@ -804,9 +798,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
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{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
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{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
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{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
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{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
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{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 },
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/* mtc2 is at the bottom of the table. */
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/* mthc2 is at the bottom of the table. */
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{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
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{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
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{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, N5 },
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@ -1186,6 +1179,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
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{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
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/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
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instructions so they are here for the latters to take precedence. */
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{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
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{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
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{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 },
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{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 },
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{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 },
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{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 },
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{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
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{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
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{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 },
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{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
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{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
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{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 },
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/* No hazard protection on coprocessor instructions--they shouldn't
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change the state of the processor and if they do it's up to the
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user to put in nops as necessary. These are at the end so that the
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