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ppc: Add Power ISA 3.0/POWER9 instructions record support
gdb/ChangeLog: 2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com> * rs6000-tdep.c (PPC_DQ): New macro. (ppc_process_record_op4): Add Power ISA 3.0 instructions. (ppc_process_record_op19): Likewise. (ppc_process_record_op31): Likewise. (ppc_process_record_op59): Likewise. (ppc_process_record_op60): Likewise. (ppc_process_record_op63): Likewise. (ppc_process_record): Likewise. (ppc_process_record_op61): New function.
This commit is contained in:
Edjunior Barbosa Machado
parent
ad43e107eb
commit
6ec2b213de
@ -1,3 +1,15 @@
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2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
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* rs6000-tdep.c (PPC_DQ): New macro.
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(ppc_process_record_op4): Add Power ISA 3.0 instructions.
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(ppc_process_record_op19): Likewise.
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(ppc_process_record_op31): Likewise.
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(ppc_process_record_op59): Likewise.
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(ppc_process_record_op60): Likewise.
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(ppc_process_record_op63): Likewise.
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(ppc_process_record): Likewise.
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(ppc_process_record_op61): New function.
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2016-09-21 Yao Qi <yao.qi@linaro.org>
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* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
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@ -3817,6 +3817,7 @@ bfd_uses_spe_extensions (bfd *abfd)
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#define PPC_T(insn) PPC_FIELD (insn, 6, 5)
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#define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
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#define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
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#define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
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#define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
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#define PPC_OE(insn) PPC_BIT (insn, 21)
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#define PPC_RC(insn) PPC_BIT (insn, 31)
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@ -3864,6 +3865,7 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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int ext = PPC_FIELD (insn, 21, 11);
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int vra = PPC_FIELD (insn, 11, 5);
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switch (ext & 0x3f)
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{
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@ -3875,6 +3877,7 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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/* FALL-THROUGH */
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case 42: /* Vector Select */
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case 43: /* Vector Permute */
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case 59: /* Vector Permute Right-indexed */
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case 44: /* Vector Shift Left Double by Octet Immediate */
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case 45: /* Vector Permute and Exclusive-OR */
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case 60: /* Vector Add Extended Unsigned Quadword Modulo */
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@ -3882,6 +3885,7 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
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case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
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case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
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case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
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case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
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case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
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case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
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@ -3891,14 +3895,37 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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return 0;
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case 48: /* Multiply-Add High Doubleword */
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case 49: /* Multiply-Add High Doubleword Unsigned */
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case 51: /* Multiply-Add Low Doubleword */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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}
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switch ((ext & 0x1ff))
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{
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case 385:
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if (vra != 0 /* Decimal Convert To Signed Quadword */
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&& vra != 2 /* Decimal Convert From Signed Quadword */
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&& vra != 4 /* Decimal Convert To Zoned */
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&& vra != 5 /* Decimal Convert To National */
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&& vra != 6 /* Decimal Convert From Zoned */
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&& vra != 7 /* Decimal Convert From National */
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&& vra != 31) /* Decimal Set Sign */
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break;
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/* 5.16 Decimal Integer Arithmetic Instructions */
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case 1: /* Decimal Add Modulo */
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case 65: /* Decimal Subtract Modulo */
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case 193: /* Decimal Shift */
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case 129: /* Decimal Unsigned Shift */
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case 449: /* Decimal Shift and Round */
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case 257: /* Decimal Truncate */
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case 321: /* Decimal Unsigned Truncate */
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/* Bit-21 should be set. */
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if (!PPC_BIT (insn, 21))
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break;
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@ -3928,6 +3955,12 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 198: /* Vector Compare Equal To Single-Precision */
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case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
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case 710: /* Vector Compare Greater Than Single-Precision */
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case 7: /* Vector Compare Not Equal Byte */
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case 71: /* Vector Compare Not Equal Halfword */
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case 135: /* Vector Compare Not Equal Word */
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case 263: /* Vector Compare Not Equal or Zero Byte */
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case 327: /* Vector Compare Not Equal or Zero Halfword */
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case 391: /* Vector Compare Not Equal or Zero Word */
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if (PPC_Rc (insn))
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record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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record_full_arch_list_add_reg (regcache,
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@ -3935,6 +3968,38 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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return 0;
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}
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if (ext == 1538)
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{
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switch (vra)
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{
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case 0: /* Vector Count Leading Zero Least-Significant Bits
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Byte */
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case 1: /* Vector Count Trailing Zero Least-Significant Bits
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Byte */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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case 6: /* Vector Negate Word */
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case 7: /* Vector Negate Doubleword */
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case 8: /* Vector Parity Byte Word */
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case 9: /* Vector Parity Byte Doubleword */
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case 10: /* Vector Parity Byte Quadword */
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case 16: /* Vector Extend Sign Byte To Word */
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case 17: /* Vector Extend Sign Halfword To Word */
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case 24: /* Vector Extend Sign Byte To Doubleword */
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case 25: /* Vector Extend Sign Halfword To Doubleword */
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case 26: /* Vector Extend Sign Word To Doubleword */
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case 28: /* Vector Count Trailing Zeros Byte */
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case 29: /* Vector Count Trailing Zeros Halfword */
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case 30: /* Vector Count Trailing Zeros Word */
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case 31: /* Vector Count Trailing Zeros Doubleword */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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return 0;
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}
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}
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switch (ext)
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{
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case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
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@ -4106,10 +4171,44 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 1923: /* Vector Population Count Word */
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case 1987: /* Vector Population Count Doubleword */
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case 1356: /* Vector Bit Permute Quadword */
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case 1484: /* Vector Bit Permute Doubleword */
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case 513: /* Vector Multiply-by-10 Unsigned Quadword */
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case 1: /* Vector Multiply-by-10 & write Carry Unsigned
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Quadword */
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case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
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case 65: /* Vector Multiply-by-10 Extended & write Carry
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Unsigned Quadword */
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case 1027: /* Vector Absolute Difference Unsigned Byte */
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case 1091: /* Vector Absolute Difference Unsigned Halfword */
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case 1155: /* Vector Absolute Difference Unsigned Word */
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case 1796: /* Vector Shift Right Variable */
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case 1860: /* Vector Shift Left Variable */
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case 133: /* Vector Rotate Left Word then Mask Insert */
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case 197: /* Vector Rotate Left Doubleword then Mask Insert */
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case 389: /* Vector Rotate Left Word then AND with Mask */
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case 453: /* Vector Rotate Left Doubleword then AND with Mask */
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case 525: /* Vector Extract Unsigned Byte */
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case 589: /* Vector Extract Unsigned Halfword */
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case 653: /* Vector Extract Unsigned Word */
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case 717: /* Vector Extract Doubleword */
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case 781: /* Vector Insert Byte */
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case 845: /* Vector Insert Halfword */
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case 909: /* Vector Insert Word */
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case 973: /* Vector Insert Doubleword */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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return 0;
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case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
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case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
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case 1677: /* Vector Extract Unsigned Word Left-Indexed */
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case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
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case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
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case 1933: /* Vector Extract Unsigned Word Right-Indexed */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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case 1604: /* Move To Vector Status and Control Register */
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record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
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return 0;
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@ -4117,6 +4216,11 @@ ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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return 0;
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case 833: /* Decimal Copy Sign */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_vr0_regnum + PPC_VRT (insn));
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record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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return 0;
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}
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fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
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@ -4134,6 +4238,14 @@ ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache,
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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int ext = PPC_EXTOP (insn);
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switch (ext & 0x01f)
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{
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case 2: /* Add PC Immediate Shifted */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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}
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switch (ext)
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{
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case 0: /* Move Condition Register Field */
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@ -4239,6 +4351,15 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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return 0;
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}
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if ((ext & 0xff) == 170)
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{
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/* Add Extended using alternate carry bits */
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record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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}
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switch (ext)
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{
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case 78: /* Determine Leftmost Zero Byte */
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@ -4257,6 +4378,9 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 302: /* Move From Branch History Rolling Buffer */
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case 339: /* Move From Special Purpose Register */
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case 371: /* Move From Time Base [Phased-Out] */
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case 309: /* Load Doubleword Monitored Indexed */
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case 128: /* Set Boolean */
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case 755: /* Deliver A Random Number */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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@ -4273,6 +4397,7 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 282: /* Convert Declets To Binary Coded Decimal */
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case 314: /* Convert Binary Coded Decimal To Declets */
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case 508: /* Compare bytes */
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case 307: /* Move From VSR Lower Doubleword */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RA (insn));
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return 0;
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@ -4291,6 +4416,12 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 32: /* Compare logical */
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case 144: /* Move To Condition Register Fields */
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/* Move To One Condition Register Field */
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case 192: /* Compare Ranged Byte */
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case 224: /* Compare Equal Byte */
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case 576: /* Move XER to CR Extended */
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case 902: /* Paste (should always fail due to single-stepping and
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the memory location might not be accessible, so
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record only CR) */
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record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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return 0;
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@ -4317,6 +4448,12 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 790: /* Load Halfword Byte-Reverse Indexed */
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case 534: /* Load Word Byte-Reverse Indexed */
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case 532: /* Load Doubleword Byte-Reverse Indexed */
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case 582: /* Load Word Atomic */
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case 614: /* Load Doubleword Atomic */
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case 265: /* Modulo Unsigned Doubleword */
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case 777: /* Modulo Signed Doubleword */
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case 267: /* Modulo Unsigned Word */
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case 779: /* Modulo Signed Word */
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record_full_arch_list_add_reg (regcache,
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tdep->ppc_gp0_regnum + PPC_RT (insn));
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return 0;
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@ -4395,6 +4532,16 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 844: /* Load VSX Vector Doubleword*2 Indexed */
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case 332: /* Load VSX Vector Doubleword & Splat Indexed */
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case 780: /* Load VSX Vector Word*4 Indexed */
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case 268: /* Load VSX Vector Indexed */
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case 364: /* Load VSX Vector Word & Splat Indexed */
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case 812: /* Load VSX Vector Halfword*8 Indexed */
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case 876: /* Load VSX Vector Byte*16 Indexed */
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case 269: /* Load VSX Vector with Length */
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case 301: /* Load VSX Vector Left-justified with Length */
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case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
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case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
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case 403: /* Move To VSR Word & Splat */
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case 435: /* Move To VSR Double Doubleword */
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ppc_record_vsr (regcache, tdep, PPC_XT (insn));
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return 0;
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@ -4416,6 +4563,10 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 922: /* Extend Sign Halfword */
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case 954: /* Extend Sign Byte */
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case 986: /* Extend Sign Word */
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case 538: /* Count Trailing Zeros Word */
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case 570: /* Count Trailing Zeros Doubleword */
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case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
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case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
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if (PPC_RC (insn))
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record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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record_full_arch_list_add_reg (regcache,
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@ -4458,6 +4609,11 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 727: /* Store Floating-Point Double Indexed */
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case 919: /* Store Floating-Point Double Pair Indexed */
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case 983: /* Store Floating-Point as Integer Word Indexed */
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case 396: /* Store VSX Vector Indexed */
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case 940: /* Store VSX Vector Halfword*8 Indexed */
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case 1004: /* Store VSX Vector Byte*16 Indexed */
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case 909: /* Store VSX Scalar as Integer Byte Indexed */
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case 941: /* Store VSX Scalar as Integer Halfword Indexed */
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if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182)
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record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
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@ -4487,6 +4643,7 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 135: /* Store Vector Element Byte Indexed */
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case 215: /* Store Byte Indexed */
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case 694: /* Store Byte Conditional Indexed */
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case 909: /* Store VSX Scalar as Integer Byte Indexed */
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size = 1;
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break;
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case 439: /* Store Halfword with Update Indexed */
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@ -4494,6 +4651,7 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 407: /* Store Halfword Indexed */
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case 726: /* Store Halfword Conditional Indexed */
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case 918: /* Store Halfword Byte-Reverse Indexed */
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case 941: /* Store VSX Scalar as Integer Halfword Indexed */
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size = 2;
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break;
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case 181: /* Store Doubleword with Update Indexed */
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@ -4511,6 +4669,9 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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case 231: /* Store Vector Indexed */
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case 487: /* Store Vector Indexed LRU */
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case 919: /* Store Floating-Point Double Pair Indexed */
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case 396: /* Store VSX Vector Indexed */
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case 940: /* Store VSX Vector Halfword*8 Indexed */
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case 1004: /* Store VSX Vector Byte*16 Indexed */
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size = 16;
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break;
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default:
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@ -4537,6 +4698,38 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
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record_full_arch_list_add_mem (addr, size);
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return 0;
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case 397: /* Store VSX Vector with Length */
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case 429: /* Store VSX Vector Left-justified with Length */
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if (PPC_RA (insn) != 0)
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regcache_raw_read_unsigned (regcache,
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tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
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regcache_raw_read_unsigned (regcache,
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tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
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/* Store up to 16 bytes. */
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nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff);
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if (nb > 0)
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record_full_arch_list_add_mem (ea, nb);
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return 0;
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case 710: /* Store Word Atomic */
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case 742: /* Store Doubleword Atomic */
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if (PPC_RA (insn) != 0)
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regcache_raw_read_unsigned (regcache,
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tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
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switch (ext)
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{
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case 710: /* Store Word Atomic */
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size = 8;
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break;
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case 742: /* Store Doubleword Atomic */
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size = 16;
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break;
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default:
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gdb_assert (0);
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}
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||||
record_full_arch_list_add_mem (ea, size);
|
||||
return 0;
|
||||
|
||||
case 725: /* Store String Word Immediate */
|
||||
ra = 0;
|
||||
if (PPC_RA (insn) != 0)
|
||||
@ -4606,6 +4799,7 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 430: /* Clear BHRB */
|
||||
case 598: /* Synchronize */
|
||||
case 62: /* Wait for Interrupt */
|
||||
case 30: /* Wait */
|
||||
case 22: /* Instruction Cache Block Touch */
|
||||
case 854: /* Enforce In-order Execution of I/O */
|
||||
case 246: /* Data Cache Block Touch for Store */
|
||||
@ -4614,6 +4808,8 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 278: /* Data Cache Block Touch */
|
||||
case 758: /* Data Cache Block Allocate */
|
||||
case 982: /* Instruction Cache Block Invalidate */
|
||||
case 774: /* Copy */
|
||||
case 838: /* CP_Abort */
|
||||
return 0;
|
||||
|
||||
case 654: /* Transaction Begin */
|
||||
@ -4713,6 +4909,7 @@ ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 226: /* DFP Test Data Group */
|
||||
case 642: /* DFP Compare Unordered */
|
||||
case 674: /* DFP Test Significance */
|
||||
case 675: /* DFP Test Significance Immediate */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
return 0;
|
||||
@ -4812,7 +5009,16 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 217: /* ditto */
|
||||
case 104: /* VSX Vector Subtract Double-Precision */
|
||||
case 72: /* VSX Vector Subtract Single-Precision */
|
||||
case 128: /* VSX Scalar Maximum Type-C Double-Precision */
|
||||
case 136: /* VSX Scalar Minimum Type-C Double-Precision */
|
||||
case 144: /* VSX Scalar Maximum Type-J Double-Precision */
|
||||
case 152: /* VSX Scalar Minimum Type-J Double-Precision */
|
||||
case 3: /* VSX Scalar Compare Equal Double-Precision */
|
||||
case 11: /* VSX Scalar Compare Greater Than Double-Precision */
|
||||
case 19: /* VSX Scalar Compare Greater Than or Equal
|
||||
Double-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
/* FALL-THROUGH */
|
||||
case 240: /* VSX Vector Copy Sign Double-Precision */
|
||||
case 208: /* VSX Vector Copy Sign Single-Precision */
|
||||
case 130: /* VSX Logical AND */
|
||||
@ -4833,6 +5039,14 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
|
||||
case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
|
||||
case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
|
||||
case 216: /* VSX Vector Insert Exponent Single-Precision */
|
||||
case 248: /* VSX Vector Insert Exponent Double-Precision */
|
||||
case 26: /* VSX Vector Permute */
|
||||
case 58: /* VSX Vector Permute Right-indexed */
|
||||
case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
|
||||
case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
|
||||
case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
|
||||
case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
|
||||
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
||||
return 0;
|
||||
|
||||
@ -4844,6 +5058,7 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
|
||||
case 35: /* VSX Scalar Compare Unordered Double-Precision */
|
||||
case 43: /* VSX Scalar Compare Ordered Double-Precision */
|
||||
case 59: /* VSX Scalar Compare Exponents Double-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
return 0;
|
||||
@ -4990,6 +5205,7 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 203: /* VSX Vector Square Root Double-Precision */
|
||||
case 139: /* VSX Vector Square Root Single-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
/* FALL-THROUGH */
|
||||
case 345: /* VSX Scalar Absolute Value Double-Precision */
|
||||
case 267: /* VSX Scalar Convert Scalar Single-Precision to
|
||||
Vector Single-Precision format Non-signalling */
|
||||
@ -5004,9 +5220,15 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 505: /* VSX Vector Negate Double-Precision */
|
||||
case 441: /* VSX Vector Negate Single-Precision */
|
||||
case 164: /* VSX Splat Word */
|
||||
case 165: /* VSX Vector Extract Unsigned Word */
|
||||
case 181: /* VSX Vector Insert Word */
|
||||
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
||||
return 0;
|
||||
|
||||
case 298: /* VSX Scalar Test Data Class Single-Precision */
|
||||
case 362: /* VSX Scalar Test Data Class Double-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
/* FALL-THROUGH */
|
||||
case 106: /* VSX Scalar Test for software Square Root
|
||||
Double-Precision */
|
||||
case 234: /* VSX Vector Test for software Square Root
|
||||
@ -5015,6 +5237,60 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
Single-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
||||
return 0;
|
||||
|
||||
case 347:
|
||||
switch (PPC_FIELD (insn, 11, 5))
|
||||
{
|
||||
case 0: /* VSX Scalar Extract Exponent Double-Precision */
|
||||
case 1: /* VSX Scalar Extract Significand Double-Precision */
|
||||
record_full_arch_list_add_reg (regcache,
|
||||
tdep->ppc_gp0_regnum + PPC_RT (insn));
|
||||
return 0;
|
||||
case 16: /* VSX Scalar Convert Half-Precision format to
|
||||
Double-Precision format */
|
||||
case 17: /* VSX Scalar round & Convert Double-Precision format
|
||||
to Half-Precision format */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 475:
|
||||
switch (PPC_FIELD (insn, 11, 5))
|
||||
{
|
||||
case 24: /* VSX Vector Convert Half-Precision format to
|
||||
Single-Precision format */
|
||||
case 25: /* VSX Vector round and Convert Single-Precision format
|
||||
to Half-Precision format */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
/* FALL-THROUGH */
|
||||
case 0: /* VSX Vector Extract Exponent Double-Precision */
|
||||
case 1: /* VSX Vector Extract Significand Double-Precision */
|
||||
case 7: /* VSX Vector Byte-Reverse Halfword */
|
||||
case 8: /* VSX Vector Extract Exponent Single-Precision */
|
||||
case 9: /* VSX Vector Extract Significand Single-Precision */
|
||||
case 15: /* VSX Vector Byte-Reverse Word */
|
||||
case 23: /* VSX Vector Byte-Reverse Doubleword */
|
||||
case 31: /* VSX Vector Byte-Reverse Quadword */
|
||||
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ext)
|
||||
{
|
||||
case 360: /* VSX Vector Splat Immediate Byte */
|
||||
if (PPC_FIELD (insn, 11, 2) == 0)
|
||||
{
|
||||
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case 918: /* VSX Scalar Insert Exponent Double-Precision */
|
||||
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (((ext >> 3) & 0x3) == 3) /* VSX Select */
|
||||
@ -5028,6 +5304,65 @@ ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Parse and record instructions of primary opcode-61 at ADDR.
|
||||
Return 0 if successful. */
|
||||
|
||||
static int
|
||||
ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
CORE_ADDR addr, uint32_t insn)
|
||||
{
|
||||
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
||||
ULONGEST ea = 0;
|
||||
int size;
|
||||
|
||||
switch (insn & 0x3)
|
||||
{
|
||||
case 0: /* Store Floating-Point Double Pair */
|
||||
case 2: /* Store VSX Scalar Doubleword */
|
||||
case 3: /* Store VSX Scalar Single */
|
||||
if (PPC_RA (insn) != 0)
|
||||
regcache_raw_read_unsigned (regcache,
|
||||
tdep->ppc_gp0_regnum + PPC_RA (insn),
|
||||
&ea);
|
||||
ea += PPC_DS (insn) << 2;
|
||||
switch (insn & 0x3)
|
||||
{
|
||||
case 0: /* Store Floating-Point Double Pair */
|
||||
size = 16;
|
||||
break;
|
||||
case 2: /* Store VSX Scalar Doubleword */
|
||||
size = 8;
|
||||
break;
|
||||
case 3: /* Store VSX Scalar Single */
|
||||
size = 4;
|
||||
break;
|
||||
default:
|
||||
gdb_assert (0);
|
||||
}
|
||||
record_full_arch_list_add_mem (ea, size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (insn & 0x7)
|
||||
{
|
||||
case 1: /* Load VSX Vector */
|
||||
ppc_record_vsr (regcache, tdep, PPC_XT (insn));
|
||||
return 0;
|
||||
case 5: /* Store VSX Vector */
|
||||
if (PPC_RA (insn) != 0)
|
||||
regcache_raw_read_unsigned (regcache,
|
||||
tdep->ppc_gp0_regnum + PPC_RA (insn),
|
||||
&ea);
|
||||
ea += PPC_DQ (insn) << 4;
|
||||
record_full_arch_list_add_mem (ea, 16);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
|
||||
"at %s.\n", insn, paddress (gdbarch, addr));
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Parse and record instructions of primary opcode-63 at ADDR.
|
||||
Return 0 if successful. */
|
||||
|
||||
@ -5066,6 +5401,16 @@ ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
||||
}
|
||||
|
||||
switch (ext & 0xff)
|
||||
{
|
||||
case 5: /* VSX Scalar Round to Quad-Precision Integer */
|
||||
case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
|
||||
Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (ext)
|
||||
{
|
||||
case 2: /* DFP Add Quad */
|
||||
@ -5095,6 +5440,7 @@ ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 226: /* DFP Test Data Group Quad */
|
||||
case 642: /* DFP Compare Unordered Quad */
|
||||
case 674: /* DFP Test Significance Quad */
|
||||
case 675: /* DFP Test Significance Immediate Quad */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
return 0;
|
||||
@ -5151,7 +5497,26 @@ ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
return 0;
|
||||
|
||||
case 583: /* Move From FPSCR */
|
||||
case 583:
|
||||
switch (PPC_FIELD (insn, 11, 5))
|
||||
{
|
||||
case 1: /* Move From FPSCR & Clear Enables */
|
||||
case 20: /* Move From FPSCR Control & set DRN */
|
||||
case 21: /* Move From FPSCR Control & set DRN Immediate */
|
||||
case 22: /* Move From FPSCR Control & set RN */
|
||||
case 23: /* Move From FPSCR Control & set RN Immediate */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
case 0: /* Move From FPSCR */
|
||||
case 24: /* Move From FPSCR Lightweight */
|
||||
if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn))
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
||||
record_full_arch_list_add_reg (regcache,
|
||||
tdep->ppc_fp0_regnum
|
||||
+ PPC_FRT (insn));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 8: /* Floating Copy Sign */
|
||||
case 40: /* Floating Negate */
|
||||
case 72: /* Floating Move Register */
|
||||
@ -5181,6 +5546,10 @@ ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
case 0: /* Floating Compare Unordered */
|
||||
case 32: /* Floating Compare Ordered */
|
||||
case 64: /* Move to Condition Register from FPSCR */
|
||||
case 132: /* VSX Scalar Compare Ordered Quad-Precision */
|
||||
case 164: /* VSX Scalar Compare Exponents Quad-Precision */
|
||||
case 644: /* VSX Scalar Compare Unordered Quad-Precision */
|
||||
case 708: /* VSX Scalar Test Data Class Quad-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
/* FALL-THROUGH */
|
||||
case 128: /* Floating Test for software Divide */
|
||||
@ -5188,10 +5557,65 @@ ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
|
||||
return 0;
|
||||
|
||||
case 4: /* VSX Scalar Add Quad-Precision */
|
||||
case 36: /* VSX Scalar Multiply Quad-Precision */
|
||||
case 388: /* VSX Scalar Multiply-Add Quad-Precision */
|
||||
case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
|
||||
case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
|
||||
case 484: /* VSX Scalar Negative Multiply-Subtract
|
||||
Quad-Precision */
|
||||
case 516: /* VSX Scalar Subtract Quad-Precision */
|
||||
case 548: /* VSX Scalar Divide Quad-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
/* FALL-THROUGH */
|
||||
case 100: /* VSX Scalar Copy Sign Quad-Precision */
|
||||
case 868: /* VSX Scalar Insert Exponent Quad-Precision */
|
||||
ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
||||
return 0;
|
||||
|
||||
case 804:
|
||||
switch (PPC_FIELD (insn, 11, 5))
|
||||
{
|
||||
case 27: /* VSX Scalar Square Root Quad-Precision */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
/* FALL-THROUGH */
|
||||
case 0: /* VSX Scalar Absolute Quad-Precision */
|
||||
case 2: /* VSX Scalar Extract Exponent Quad-Precision */
|
||||
case 8: /* VSX Scalar Negative Absolute Quad-Precision */
|
||||
case 16: /* VSX Scalar Negate Quad-Precision */
|
||||
case 18: /* VSX Scalar Extract Significand Quad-Precision */
|
||||
ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 836:
|
||||
switch (PPC_FIELD (insn, 11, 5))
|
||||
{
|
||||
case 1: /* VSX Scalar truncate & Convert Quad-Precision format
|
||||
to Unsigned Word format */
|
||||
case 2: /* VSX Scalar Convert Unsigned Doubleword format to
|
||||
Quad-Precision format */
|
||||
case 9: /* VSX Scalar truncate & Convert Quad-Precision format
|
||||
to Signed Word format */
|
||||
case 10: /* VSX Scalar Convert Signed Doubleword format to
|
||||
Quad-Precision format */
|
||||
case 17: /* VSX Scalar truncate & Convert Quad-Precision format
|
||||
to Unsigned Doubleword format */
|
||||
case 20: /* VSX Scalar round & Convert Quad-Precision format to
|
||||
Double-Precision format */
|
||||
case 22: /* VSX Scalar Convert Double-Precision format to
|
||||
Quad-Precision format */
|
||||
case 25: /* VSX Scalar truncate & Convert Quad-Precision format
|
||||
to Signed Doubleword format */
|
||||
record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
|
||||
ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
|
||||
"at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
|
||||
"at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext);
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -5402,12 +5826,21 @@ ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
}
|
||||
break;
|
||||
|
||||
case 57: /* Load Floating-Point Double Pair */
|
||||
if (PPC_FIELD (insn, 30, 2) != 0)
|
||||
goto UNKNOWN_OP;
|
||||
tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
|
||||
record_full_arch_list_add_reg (regcache, tmp);
|
||||
record_full_arch_list_add_reg (regcache, tmp + 1);
|
||||
case 57:
|
||||
switch (insn & 0x3)
|
||||
{
|
||||
case 0: /* Load Floating-Point Double Pair */
|
||||
tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
|
||||
record_full_arch_list_add_reg (regcache, tmp);
|
||||
record_full_arch_list_add_reg (regcache, tmp + 1);
|
||||
break;
|
||||
case 2: /* Load VSX Scalar Doubleword */
|
||||
case 3: /* Load VSX Scalar Single */
|
||||
ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
|
||||
break;
|
||||
default:
|
||||
goto UNKNOWN_OP;
|
||||
}
|
||||
break;
|
||||
|
||||
case 58: /* Load Doubleword */
|
||||
@ -5433,7 +5866,11 @@ ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
return -1;
|
||||
break;
|
||||
|
||||
case 61: /* Store Floating-Point Double Pair */
|
||||
case 61:
|
||||
if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0)
|
||||
return -1;
|
||||
break;
|
||||
|
||||
case 62: /* Store Doubleword */
|
||||
/* Store Doubleword with Update */
|
||||
/* Store Quadword with Update */
|
||||
@ -5442,7 +5879,7 @@ ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
int size;
|
||||
int sub2 = PPC_FIELD (insn, 30, 2);
|
||||
|
||||
if ((op6 == 61 && sub2 != 0) || (op6 == 62 && sub2 > 2))
|
||||
if (sub2 > 2)
|
||||
goto UNKNOWN_OP;
|
||||
|
||||
if (PPC_RA (insn) != 0)
|
||||
@ -5450,7 +5887,7 @@ ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
|
||||
tdep->ppc_gp0_regnum + PPC_RA (insn),
|
||||
&addr);
|
||||
|
||||
size = ((op6 == 61) || sub2 == 2) ? 16 : 8;
|
||||
size = (sub2 == 2) ? 16 : 8;
|
||||
|
||||
addr += PPC_DS (insn) << 2;
|
||||
record_full_arch_list_add_mem (addr, size);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user