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* Makefile.in (ns32k-opcode.h): Remove reference.
(ns32k-pinsn.o): Update dependencies. * ns32k-opcode.h: Remove file. * ns32k-pinsn.c (print_insn): Call version in libopcodes, remove all other code in this file.
This commit is contained in:
Stan Shebs
parent
dd55ca703a
commit
6d8dfa64d2
@ -1,3 +1,11 @@
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Mon Aug 29 14:39:42 1994 Stan Shebs (shebs@andros.cygnus.com)
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* Makefile.in (ns32k-opcode.h): Remove reference.
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(ns32k-pinsn.o): Update dependencies.
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* ns32k-opcode.h: Remove file.
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* ns32k-pinsn.c (print_insn): Call version in libopcodes, remove
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all other code in this file.
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Mon Aug 29 12:04:07 1994 Stu Grossman (grossman@cygnus.com)
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* nlm/configure.in: Stop using cpu.c. Put it in TDEPFILES instead.
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@ -1,328 +0,0 @@
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/* ns32k-opcode.h */
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#ifndef ns32k_opcodeT
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#define ns32k_opcodeT int
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#endif /* no ns32k_opcodeT */
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struct not_wot /* ns32k opcode table: wot to do with this */
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/* particular opcode */
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{
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int obits; /* number of opcode bits */
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int ibits; /* number of instruction bits */
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ns32k_opcodeT code; /* op-code (may be > 8 bits!) */
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char *args; /* how to compile said opcode */
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};
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struct not /* ns32k opcode text */
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{
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char * name; /* opcode name: lowercase string [key] */
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struct not_wot detail; /* rest of opcode table [datum] */
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};
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/* Instructions look like this:
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basic instruction--1, 2, or 3 bytes
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index byte for operand A, if operand A is indexed--1 byte
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index byte for operand B, if operand B is indexed--1 byte
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addressing extension for operand A
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addressing extension for operand B
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implied operands
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Operand A is the operand listed first in the following opcode table.
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Operand B is the operand listed second in the following opcode table.
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All instructions have at most 2 general operands, so this is enough.
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The implied operands are associated with operands other than A and B.
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Each operand has a digit and a letter.
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The digit gives the position in the assembly language. The letter,
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one of the following, tells us what kind of operand it is. */
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/* F : 32 bit float
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* L : 64 bit float
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* B : byte
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* W : word
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* D : double-word
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* Q : quad-word
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* d : displacement
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* q : quick
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* i : immediate (8 bits)
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* r : register number (3 bits)
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* p : displacement - pc relative addressing
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*/
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static struct not
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notstrs[] =
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{
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{ "absf", 14,24, 0x35be, "1F2F" },
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{ "absl", 14,24, 0x34be, "1L2L" },
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{ "absb", 14,24, 0x304e, "1B2B" },
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{ "absw", 14,24, 0x314e, "1W2W" },
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{ "absd", 14,24, 0x334e, "1D2D" },
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{ "acbb", 7,16, 0x4c, "2B1q3p" },
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{ "acbw", 7,16, 0x4d, "2W1q3p" },
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{ "acbd", 7,16, 0x4f, "2D1q3p" },
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{ "addf", 14,24, 0x01be, "1F2F" },
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{ "addl", 14,24, 0x00be, "1L2L" },
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{ "addb", 6,16, 0x00, "1B2B" },
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{ "addw", 6,16, 0x01, "1W2W" },
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{ "addd", 6,16, 0x03, "1D2D" },
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{ "addcb", 6,16, 0x10, "1B2B" },
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{ "addcw", 6,16, 0x11, "1W2W" },
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{ "addcd", 6,16, 0x13, "1D2D" },
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{ "addpb", 14,24, 0x3c4e, "1B2B" },
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{ "addpw", 14,24, 0x3d4e, "1W2W" },
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{ "addpd", 14,24, 0x3f4e, "1D2D" },
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{ "addqb", 7,16, 0x0c, "2B1q" },
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{ "addqw", 7,16, 0x0d, "2W1q" },
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{ "addqd", 7,16, 0x0f, "2D1q" },
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{ "addr", 6,16, 0x27, "1D2D" },
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{ "adjspb", 11,16, 0x057c, "1B" },
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{ "adjspw", 11,16, 0x057d, "1W" },
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{ "adjspd", 11,16, 0x057f, "1D" },
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{ "andb", 6,16, 0x28, "1B2B" },
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{ "andw", 6,16, 0x29, "1W2W" },
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{ "andd", 6,16, 0x2b, "1D2D" },
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{ "ashb", 14,24, 0x044e, "1B2B" },
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{ "ashw", 14,24, 0x054e, "1B2W" },
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{ "ashd", 14,24, 0x074e, "1B2D" },
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{ "beq", 8,8, 0x0a, "1p" },
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{ "bne", 8,8, 0x1a, "1p" },
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{ "bcs", 8,8, 0x2a, "1p" },
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{ "bcc", 8,8, 0x3a, "1p" },
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{ "bhi", 8,8, 0x4a, "1p" },
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{ "bls", 8,8, 0x5a, "1p" },
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{ "bgt", 8,8, 0x6a, "1p" },
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{ "ble", 8,8, 0x7a, "1p" },
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{ "bfs", 8,8, 0x8a, "1p" },
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{ "bfc", 8,8, 0x9a, "1p" },
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{ "blo", 8,8, 0xaa, "1p" },
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{ "bhs", 8,8, 0xba, "1p" },
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{ "blt", 8,8, 0xca, "1p" },
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{ "bge", 8,8, 0xda, "1p" },
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{ "bicb", 6,16, 0x08, "1B2B" },
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{ "bicw", 6,16, 0x09, "1W2W" },
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{ "bicd", 6,16, 0x0b, "1D2D" },
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{ "bicpsrb", 11,16, 0x17c, "1B" },
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{ "bicpsrw", 11,16, 0x17d, "1W" },
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{ "bispsrb", 11,16, 0x37c, "1B" },
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{ "bispsrw", 11,16, 0x37d, "1W" },
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{ "bpt", 8,8, 0xf2, "" },
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{ "br", 8,8, 0xea, "1p" },
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{ "bsr", 8,8, 0x02, "1p" },
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{ "caseb", 11,16, 0x77c, "1B" },
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{ "casew", 11,16, 0x77d, "1W" },
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{ "cased", 11,16, 0x77f, "1D" },
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{ "cbitb", 14,24, 0x084e, "1B2D" },
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{ "cbitw", 14,24, 0x094e, "1W2D" },
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{ "cbitd", 14,24, 0x0b4e, "1D2D" },
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{ "cbitib", 14,24, 0x0c4e, "1B2D" },
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{ "cbitiw", 14,24, 0x0d4e, "1W2D" },
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{ "cbitid", 14,24, 0x0f4e, "1D2D" },
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{ "checkb", 11,24, 0x0ee, "2A3B1r" },
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{ "checkw", 11,24, 0x1ee, "2A3B1r" },
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{ "checkd", 11,24, 0x3ee, "2A3D1r" },
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{ "cmpf", 14,24, 0x09be, "1F2F" },
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{ "cmpl", 14,24, 0x08be, "1L2L" },
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{ "cmpb", 6,16, 0x04, "1B2B" },
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{ "cmpw", 6,16, 0x05, "1W2W" },
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{ "cmpd", 6,16, 0x07, "1D2D" },
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{ "cmpmb", 14,24, 0x04ce, "1D2D3d" },
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{ "cmpmw", 14,24, 0x05ce, "1D2D3d" },
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{ "cmpmd", 14,24, 0x07ce, "1D2D3d" },
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{ "cmpqb", 7,16, 0x1c, "2B1q" },
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{ "cmpqw", 7,16, 0x1d, "2W1q" },
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{ "cmpqd", 7,16, 0x1f, "2D1q" },
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{ "cmpsb", 16,16, 0x040e, "1i" },
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{ "cmpsw", 16,16, 0x050e, "1i" },
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{ "cmpsd", 16,16, 0x070e, "1i" },
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{ "cmpst", 16,16, 0x840e, "1i" },
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{ "comb", 14,24, 0x344e, "1B2B" },
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{ "comw", 14,24, 0x354e, "1W2W" },
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{ "comd", 14,24, 0x374e, "1D2D" },
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{ "cvtp", 11,24, 0x036e, "2D3D1r" },
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{ "cxp", 8,8, 0x22, "1p" },
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{ "cxpd", 11,16, 0x07f, "1D" },
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{ "deib", 14,24, 0x2cce, "1B2W" },
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{ "deiw", 14,24, 0x2dce, "1W2D" },
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{ "deid", 14,24, 0x2fce, "1D2Q" },
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{ "dia", 8,8, 0xc2, "" },
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{ "divf", 14,24, 0x21be, "1F2F" },
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{ "divl", 14,24, 0x20be, "1L2L" },
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{ "divb", 14,24, 0x3cce, "1B2B" },
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{ "divw", 14,24, 0x3dce, "1W2W" },
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{ "divd", 14,24, 0x3fce, "1D2D" },
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{ "enter", 8,8, 0x82, "1i2d" },
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{ "exit", 8,8, 0x92, "1i" },
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{ "extb", 11,24, 0x02e, "2D3B1r4d" },
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{ "extw", 11,24, 0x12e, "2D3W1r4d" },
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{ "extd", 11,24, 0x32e, "2D3D1r4d" },
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{ "extsb", 14,24, 0x0cce, "1D2B3i" },
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{ "extsw", 14,24, 0x0dce, "1D2W3i" },
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{ "extsd", 14,24, 0x0fce, "1D2D3i" },
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{ "ffsb", 14,24, 0x046e, "1B2B" },
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{ "ffsw", 14,24, 0x056e, "1W2B" },
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{ "ffsd", 14,24, 0x076e, "1D2B" },
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{ "flag", 8,8, 0xd2, "" },
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{ "floorfb", 14,24, 0x3c3e, "1F2B" },
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{ "floorfw", 14,24, 0x3d3e, "1F2W" },
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{ "floorfd", 14,24, 0x3f3e, "1F2D" },
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{ "floorlb", 14,24, 0x383e, "1L2B" },
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{ "floorlw", 14,24, 0x393e, "1L2W" },
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{ "floorld", 14,24, 0x3b3e, "1L2D" },
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{ "ibitb", 14,24, 0x384e, "1B2D" },
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{ "ibitw", 14,24, 0x394e, "1W2D" },
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{ "ibitd", 14,24, 0x3b4e, "1D2D" },
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{ "indexb", 11,24, 0x42e, "2B3B1r" },
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{ "indexw", 11,24, 0x52e, "2W3W1r" },
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{ "indexd", 11,24, 0x72e, "2D3D1r" },
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{ "insb", 11,24, 0x0ae, "2B3B1r4d" },
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{ "insw", 11,24, 0x1ae, "2W3W1r4d" },
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{ "insd", 11,24, 0x3ae, "2D3D1r4d" },
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{ "inssb", 14,24, 0x08ce, "1B2D3i" },
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{ "inssw", 14,24, 0x09ce, "1W2D3i" },
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{ "inssd", 14,24, 0x0bce, "1D2D3i" },
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{ "jsr", 11,16, 0x67f, "1A" },
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{ "jump", 11,16, 0x27f, "1A" },
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{ "lfsr", 19,24, 0x00f3e,"1D" },
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{ "lmr", 15,24, 0x0b1e, "2D1q" },
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{ "lprb", 7,16, 0x6c, "2B1q" },
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{ "lprw", 7,16, 0x6d, "2W1q" },
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{ "lprd", 7,16, 0x6f, "2D1q" },
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{ "lshb", 14,24, 0x144e, "1B2B" },
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{ "lshw", 14,24, 0x154e, "1B2W" },
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{ "lshd", 14,24, 0x174e, "1B2D" },
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{ "meib", 14,24, 0x24ce, "1B2W" },
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{ "meiw", 14,24, 0x25ce, "1W2D" },
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{ "meid", 14,24, 0x27ce, "1D2Q" },
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{ "modb", 14,24, 0x38ce, "1B2B" },
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{ "modw", 14,24, 0x39ce, "1W2W" },
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{ "modd", 14,24, 0x3bce, "1D2D" },
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{ "movf", 14,24, 0x05be, "1F2F" },
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{ "movl", 14,24, 0x04be, "1L2L" },
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{ "movb", 6,16, 0x14, "1B2B" },
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{ "movw", 6,16, 0x15, "1W2W" },
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{ "movd", 6,16, 0x17, "1D2D" },
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{ "movbf", 14,24, 0x043e, "1B2F" },
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{ "movwf", 14,24, 0x053e, "1W2F" },
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{ "movdf", 14,24, 0x073e, "1D2F" },
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{ "movbl", 14,24, 0x003e, "1B2L" },
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{ "movwl", 14,24, 0x013e, "1W2L" },
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{ "movdl", 14,24, 0x033e, "1D2L" },
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{ "movfl", 14,24, 0x1b3e, "1F2L" },
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{ "movlf", 14,24, 0x163e, "1L2F" },
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{ "movmb", 14,24, 0x00ce, "1D2D3d" },
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{ "movmw", 14,24, 0x01ce, "1D2D3d" },
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{ "movmd", 14,24, 0x03ce, "1D2D3d" },
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{ "movqb", 7,16, 0x5c, "2B1q" },
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{ "movqw", 7,16, 0x5d, "2B1q" },
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{ "movqd", 7,16, 0x5f, "2B1q" },
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{ "movsb", 16,16, 0x000e, "1i" },
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{ "movsw", 16,16, 0x010e, "1i" },
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{ "movsd", 16,16, 0x030e, "1i" },
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{ "movst", 16,16, 0x800e, "1i" },
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{ "movsub", 14,24, 0x0cae, "1A1A" },
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{ "movsuw", 14,24, 0x0dae, "1A1A" },
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{ "movsud", 14,24, 0x0fae, "1A1A" },
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{ "movusb", 14,24, 0x1cae, "1A1A" },
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{ "movusw", 14,24, 0x1dae, "1A1A" },
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{ "movusd", 14,24, 0x1fae, "1A1A" },
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{ "movxbd", 14,24, 0x1cce, "1B2D" },
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{ "movxwd", 14,24, 0x1dce, "1W2D" },
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{ "movxbw", 14,24, 0x10ce, "1B2W" },
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{ "movzbd", 14,24, 0x18ce, "1B2D" },
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{ "movzwd", 14,24, 0x19ce, "1W2D" },
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{ "movzbw", 14,24, 0x14ce, "1B2W" },
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{ "mulf", 14,24, 0x31be, "1F2F" },
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{ "mull", 14,24, 0x30be, "1L2L" },
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{ "mulb", 14,24, 0x20ce, "1B2B" },
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{ "mulw", 14,24, 0x21ce, "1W2W" },
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{ "muld", 14,24, 0x23ce, "1D2D" },
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{ "negf", 14,24, 0x15be, "1F2F" },
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{ "negl", 14,24, 0x14be, "1L2L" },
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{ "negb", 14,24, 0x204e, "1B2B" },
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{ "negw", 14,24, 0x214e, "1W2W" },
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{ "negd", 14,24, 0x234e, "1D2D" },
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{ "nop", 8,8, 0xa2, "" },
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{ "notb", 14,24, 0x244e, "1B2B" },
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{ "notw", 14,24, 0x254e, "1W2W" },
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{ "notd", 14,24, 0x274e, "1D2D" },
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{ "orb", 6,16, 0x18, "1B1B" },
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{ "orw", 6,16, 0x19, "1W1W" },
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{ "ord", 6,16, 0x1b, "1D2D" },
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{ "quob", 14,24, 0x30ce, "1B2B" },
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{ "quow", 14,24, 0x31ce, "1W2W" },
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{ "quod", 14,24, 0x33ce, "1D2D" },
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{ "rdval", 19,24, 0x0031e,"1A" },
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{ "remb", 14,24, 0x34ce, "1B2B" },
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{ "remw", 14,24, 0x35ce, "1W2W" },
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{ "remd", 14,24, 0x37ce, "1D2D" },
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{ "restore", 8,8, 0x72, "1i" },
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{ "ret", 8,8, 0x12, "1d" },
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{ "reti", 8,8, 0x52, "" },
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{ "rett", 8,8, 0x42, "" },
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{ "rotb", 14,24, 0x004e, "1B2B" },
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{ "rotw", 14,24, 0x014e, "1B2W" },
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{ "rotd", 14,24, 0x034e, "1B2D" },
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{ "roundfb", 14,24, 0x243e, "1F2B" },
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{ "roundfw", 14,24, 0x253e, "1F2W" },
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{ "roundfd", 14,24, 0x273e, "1F2D" },
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{ "roundlb", 14,24, 0x203e, "1L2B" },
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{ "roundlw", 14,24, 0x213e, "1L2W" },
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{ "roundld", 14,24, 0x233e, "1L2D" },
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{ "rxp", 8,8, 0x32, "1d" },
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{ "sCONDb", 7,16, 0x3c, "2B1q" },
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{ "sCONDw", 7,16, 0x3d, "2D1q" },
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{ "sCONDd", 7,16, 0x3f, "2D1q" },
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{ "save", 8,8, 0x62, "1i" },
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{ "sbitb", 14,24, 0x184e, "1B2A" },
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{ "sbitw", 14,24, 0x194e, "1W2A" },
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{ "sbitd", 14,24, 0x1b4e, "1D2A" },
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{ "sbitib", 14,24, 0x1c4e, "1B2A" },
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{ "sbitiw", 14,24, 0x1d4e, "1W2A" },
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{ "sbitid", 14,24, 0x1f4e, "1D2A" },
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{ "setcfg", 15,24, 0x0b0e, "5D1q" },
|
||||
{ "sfsr", 14,24, 0x373e, "5D1D" },
|
||||
{ "skpsb", 16,16, 0x0c0e, "1i" },
|
||||
{ "skpsw", 16,16, 0x0d0e, "1i" },
|
||||
{ "skpsd", 16,16, 0x0f0e, "1i" },
|
||||
{ "skpst", 16,16, 0x8c0e, "1i" },
|
||||
{ "smr", 15,24, 0x0f1e, "2D1q" },
|
||||
{ "sprb", 7,16, 0x2c, "2B1q" },
|
||||
{ "sprw", 7,16, 0x2d, "2W1q" },
|
||||
{ "sprd", 7,16, 0x2f, "2D1q" },
|
||||
{ "subf", 14,24, 0x11be, "1F2F" },
|
||||
{ "subl", 14,24, 0x10be, "1L2L" },
|
||||
{ "subb", 6,16, 0x20, "1B2B" },
|
||||
{ "subw", 6,16, 0x21, "1W2W" },
|
||||
{ "subd", 6,16, 0x23, "1D2D" },
|
||||
{ "subcb", 6,16, 0x30, "1B2B" },
|
||||
{ "subcw", 6,16, 0x31, "1W2W" },
|
||||
{ "subcd", 6,16, 0x33, "1D2D" },
|
||||
{ "subpb", 14,24, 0x2c4e, "1B2B" },
|
||||
{ "subpw", 14,24, 0x2d4e, "1W2W" },
|
||||
{ "subpd", 14,24, 0x2f4e, "1D2D" },
|
||||
#ifdef NS32K_SVC_IMMED_OPERANDS
|
||||
{ "svc", 8,8, 0xe2, "2i1i" }, /* not really, but unix uses it */
|
||||
#else
|
||||
{ "svc", 8,8, 0xe2, "" }, /* not really, but unix uses it */
|
||||
#endif
|
||||
{ "tbitb", 6,16, 0x34, "1B2A" },
|
||||
{ "tbitw", 6,16, 0x35, "1W2A" },
|
||||
{ "tbitd", 6,16, 0x37, "1D2A" },
|
||||
{ "truncfb", 14,24, 0x2c3e, "1F2B" },
|
||||
{ "truncfw", 14,24, 0x2d3e, "1F2W" },
|
||||
{ "truncfd", 14,24, 0x2f3e, "1F2D" },
|
||||
{ "trunclb", 14,24, 0x283e, "1L2B" },
|
||||
{ "trunclw", 14,24, 0x293e, "1L2W" },
|
||||
{ "truncld", 14,24, 0x2b3e, "1L2D" },
|
||||
{ "wait", 8,8, 0xb2, "" },
|
||||
{ "wrval", 19,24, 0x0071e,"1A" },
|
||||
{ "xorb", 6,16, 0x38, "1B2B" },
|
||||
{ "xorw", 6,16, 0x39, "1W2W" },
|
||||
{ "xord", 6,16, 0x3b, "1D2D" },
|
||||
}; /* notstrs */
|
||||
|
||||
/* end: ns32k.opcode.h */
|
||||
|
||||
#define MAX_ARGS 4
|
||||
#define ARG_LEN 50
|
||||
@ -1,5 +1,5 @@
|
||||
/* Print National Semiconductor 32000 instructions for GDB, the GNU debugger.
|
||||
Copyright 1986, 1988, 1991, 1992 Free Software Foundation, Inc.
|
||||
/* Print NS 32000 instructions for GDB, the GNU debugger.
|
||||
Copyright 1986, 1988, 1991, 1992, 1994 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB.
|
||||
|
||||
@ -18,500 +18,19 @@ along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
#include "defs.h"
|
||||
#include "symtab.h"
|
||||
#include "ns32k-opcode.h"
|
||||
#include "gdbcore.h"
|
||||
#include "dis-asm.h"
|
||||
|
||||
/* 32000 instructions are never longer than this. */
|
||||
#define MAXLEN 62
|
||||
|
||||
/* Number of elements in the opcode table. */
|
||||
#define NOPCODES (sizeof notstrs / sizeof notstrs[0])
|
||||
|
||||
#define NEXT_IS_ADDR '|'
|
||||
|
||||
/*
|
||||
* extract "count" bits starting "offset" bits
|
||||
* into buffer
|
||||
*/
|
||||
|
||||
int
|
||||
bit_extract (buffer, offset, count)
|
||||
char *buffer;
|
||||
int offset;
|
||||
int count;
|
||||
{
|
||||
int result;
|
||||
int mask;
|
||||
int bit;
|
||||
|
||||
buffer += offset >> 3;
|
||||
offset &= 7;
|
||||
bit = 1;
|
||||
result = 0;
|
||||
while (count--)
|
||||
{
|
||||
if ((*buffer & (1 << offset)))
|
||||
result |= bit;
|
||||
if (++offset == 8)
|
||||
{
|
||||
offset = 0;
|
||||
buffer++;
|
||||
}
|
||||
bit <<= 1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
float
|
||||
fbit_extract (buffer, offset, count)
|
||||
{
|
||||
union {
|
||||
int ival;
|
||||
float fval;
|
||||
} foo;
|
||||
|
||||
foo.ival = bit_extract (buffer, offset, 32);
|
||||
return foo.fval;
|
||||
}
|
||||
|
||||
double
|
||||
dbit_extract (buffer, offset, count)
|
||||
{
|
||||
union {
|
||||
struct {int low, high; } ival;
|
||||
double dval;
|
||||
} foo;
|
||||
|
||||
foo.ival.low = bit_extract (buffer, offset, 32);
|
||||
foo.ival.high = bit_extract (buffer, offset+32, 32);
|
||||
return foo.dval;
|
||||
}
|
||||
|
||||
sign_extend (value, bits)
|
||||
{
|
||||
value = value & ((1 << bits) - 1);
|
||||
return (value & (1 << (bits-1))
|
||||
? value | (~((1 << bits) - 1))
|
||||
: value);
|
||||
}
|
||||
|
||||
flip_bytes (ptr, count)
|
||||
char *ptr;
|
||||
int count;
|
||||
{
|
||||
char tmp;
|
||||
|
||||
while (count > 0)
|
||||
{
|
||||
tmp = *ptr;
|
||||
ptr[0] = ptr[count-1];
|
||||
ptr[count-1] = tmp;
|
||||
ptr++;
|
||||
count -= 2;
|
||||
}
|
||||
}
|
||||
|
||||
/* Given a character C, does it represent a general addressing mode? */
|
||||
#define Is_gen(c) \
|
||||
((c) == 'F' || (c) == 'L' || (c) == 'B' \
|
||||
|| (c) == 'W' || (c) == 'D' || (c) == 'A')
|
||||
|
||||
/* Adressing modes. */
|
||||
#define Adrmod_index_byte 0x1c
|
||||
#define Adrmod_index_word 0x1d
|
||||
#define Adrmod_index_doubleword 0x1e
|
||||
#define Adrmod_index_quadword 0x1f
|
||||
|
||||
/* Is MODE an indexed addressing mode? */
|
||||
#define Adrmod_is_index(mode) \
|
||||
(mode == Adrmod_index_byte \
|
||||
|| mode == Adrmod_index_word \
|
||||
|| mode == Adrmod_index_doubleword \
|
||||
|| mode == Adrmod_index_quadword)
|
||||
|
||||
|
||||
/* Print the 32000 instruction at address MEMADDR in debugged memory,
|
||||
/* Print the instruction at address MEMADDR in debugged memory,
|
||||
on STREAM. Returns length of the instruction, in bytes. */
|
||||
|
||||
int
|
||||
print_insn (memaddr, stream)
|
||||
CORE_ADDR memaddr;
|
||||
FILE *stream;
|
||||
GDB_FILE *stream;
|
||||
{
|
||||
unsigned char buffer[MAXLEN];
|
||||
register int i;
|
||||
register unsigned char *p;
|
||||
register char *d;
|
||||
unsigned short first_word;
|
||||
int gen, disp;
|
||||
int ioffset; /* bits into instruction */
|
||||
int aoffset; /* bits into arguments */
|
||||
char arg_bufs[MAX_ARGS+1][ARG_LEN];
|
||||
int argnum;
|
||||
int maxarg;
|
||||
disassemble_info info;
|
||||
|
||||
read_memory (memaddr, buffer, MAXLEN);
|
||||
GDB_INIT_DISASSEMBLE_INFO (info, stream);
|
||||
|
||||
first_word = *(unsigned short *) buffer;
|
||||
for (i = 0; i < NOPCODES; i++)
|
||||
if ((first_word & ((1 << notstrs[i].detail.obits) - 1))
|
||||
== notstrs[i].detail.code)
|
||||
break;
|
||||
|
||||
/* Handle undefined instructions. */
|
||||
if (i == NOPCODES)
|
||||
{
|
||||
fprintf (stream, "0%o", buffer[0]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fprintf (stream, "%s", notstrs[i].name);
|
||||
|
||||
ioffset = notstrs[i].detail.ibits;
|
||||
aoffset = notstrs[i].detail.ibits;
|
||||
d = notstrs[i].detail.args;
|
||||
|
||||
if (*d)
|
||||
{
|
||||
/* Offset in bits of the first thing beyond each index byte.
|
||||
Element 0 is for operand A and element 1 is for operand B.
|
||||
The rest are irrelevant, but we put them here so we don't
|
||||
index outside the array. */
|
||||
int index_offset[MAX_ARGS];
|
||||
|
||||
/* 0 for operand A, 1 for operand B, greater for other args. */
|
||||
int whicharg = 0;
|
||||
|
||||
fputc ('\t', stream);
|
||||
|
||||
maxarg = 0;
|
||||
|
||||
/* First we have to find and keep track of the index bytes,
|
||||
if we are using scaled indexed addressing mode, since the index
|
||||
bytes occur right after the basic instruction, not as part
|
||||
of the addressing extension. */
|
||||
if (Is_gen(d[1]))
|
||||
{
|
||||
int addr_mode = bit_extract (buffer, ioffset - 5, 5);
|
||||
|
||||
if (Adrmod_is_index (addr_mode))
|
||||
{
|
||||
aoffset += 8;
|
||||
index_offset[0] = aoffset;
|
||||
}
|
||||
}
|
||||
if (d[2] && Is_gen(d[3]))
|
||||
{
|
||||
int addr_mode = bit_extract (buffer, ioffset - 10, 5);
|
||||
|
||||
if (Adrmod_is_index (addr_mode))
|
||||
{
|
||||
aoffset += 8;
|
||||
index_offset[1] = aoffset;
|
||||
}
|
||||
}
|
||||
|
||||
while (*d)
|
||||
{
|
||||
argnum = *d - '1';
|
||||
d++;
|
||||
if (argnum > maxarg && argnum < MAX_ARGS)
|
||||
maxarg = argnum;
|
||||
ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer,
|
||||
memaddr, arg_bufs[argnum],
|
||||
index_offset[whicharg]);
|
||||
d++;
|
||||
whicharg++;
|
||||
}
|
||||
for (argnum = 0; argnum <= maxarg; argnum++)
|
||||
{
|
||||
CORE_ADDR addr;
|
||||
char *ch;
|
||||
for (ch = arg_bufs[argnum]; *ch;)
|
||||
{
|
||||
if (*ch == NEXT_IS_ADDR)
|
||||
{
|
||||
++ch;
|
||||
addr = atoi (ch);
|
||||
print_address (addr, stream);
|
||||
while (*ch && *ch != NEXT_IS_ADDR)
|
||||
++ch;
|
||||
if (*ch)
|
||||
++ch;
|
||||
}
|
||||
else
|
||||
putc (*ch++, stream);
|
||||
}
|
||||
if (argnum < maxarg)
|
||||
fprintf (stream, ", ");
|
||||
}
|
||||
}
|
||||
return aoffset / 8;
|
||||
}
|
||||
|
||||
/* Print an instruction operand of category given by d. IOFFSET is
|
||||
the bit position below which small (<1 byte) parts of the operand can
|
||||
be found (usually in the basic instruction, but for indexed
|
||||
addressing it can be in the index byte). AOFFSETP is a pointer to the
|
||||
bit position of the addressing extension. BUFFER contains the
|
||||
instruction. ADDR is where BUFFER was read from. Put the disassembled
|
||||
version of the operand in RESULT. INDEX_OFFSET is the bit position
|
||||
of the index byte (it contains garbage if this operand is not a
|
||||
general operand using scaled indexed addressing mode). */
|
||||
|
||||
print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
|
||||
char d;
|
||||
int ioffset, *aoffsetp;
|
||||
char *buffer;
|
||||
CORE_ADDR addr;
|
||||
char *result;
|
||||
int index_offset;
|
||||
{
|
||||
int addr_mode;
|
||||
float Fvalue;
|
||||
double Lvalue;
|
||||
int Ivalue;
|
||||
int disp1, disp2;
|
||||
int index;
|
||||
|
||||
switch (d)
|
||||
{
|
||||
case 'F':
|
||||
case 'L':
|
||||
case 'B':
|
||||
case 'W':
|
||||
case 'D':
|
||||
case 'A':
|
||||
addr_mode = bit_extract (buffer, ioffset-5, 5);
|
||||
ioffset -= 5;
|
||||
switch (addr_mode)
|
||||
{
|
||||
case 0x0: case 0x1: case 0x2: case 0x3:
|
||||
case 0x4: case 0x5: case 0x6: case 0x7:
|
||||
switch (d)
|
||||
{
|
||||
case 'F':
|
||||
case 'L':
|
||||
sprintf (result, "f%d", addr_mode);
|
||||
break;
|
||||
default:
|
||||
sprintf (result, "r%d", addr_mode);
|
||||
}
|
||||
break;
|
||||
case 0x8: case 0x9: case 0xa: case 0xb:
|
||||
case 0xc: case 0xd: case 0xe: case 0xf:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "%d(r%d)", disp1, addr_mode & 7);
|
||||
break;
|
||||
case 0x10:
|
||||
case 0x11:
|
||||
case 0x12:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
disp2 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "%d(%d(%s))", disp2, disp1,
|
||||
addr_mode==0x10?"fp":addr_mode==0x11?"sp":"sb");
|
||||
break;
|
||||
case 0x13:
|
||||
sprintf (result, "reserved");
|
||||
break;
|
||||
case 0x14:
|
||||
switch (d)
|
||||
{
|
||||
case 'B':
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 8);
|
||||
Ivalue = sign_extend (Ivalue, 8);
|
||||
*aoffsetp += 8;
|
||||
sprintf (result, "$%d", Ivalue);
|
||||
break;
|
||||
case 'W':
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 16);
|
||||
flip_bytes (&Ivalue, 2);
|
||||
*aoffsetp += 16;
|
||||
Ivalue = sign_extend (Ivalue, 16);
|
||||
sprintf (result, "$%d", Ivalue);
|
||||
break;
|
||||
case 'D':
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 32);
|
||||
flip_bytes (&Ivalue, 4);
|
||||
*aoffsetp += 32;
|
||||
sprintf (result, "$%d", Ivalue);
|
||||
break;
|
||||
case 'A':
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 32);
|
||||
flip_bytes (&Ivalue, 4);
|
||||
*aoffsetp += 32;
|
||||
sprintf (result, "$|%d|", Ivalue);
|
||||
break;
|
||||
case 'F':
|
||||
Fvalue = fbit_extract (buffer, *aoffsetp, 32);
|
||||
flip_bytes (&Fvalue, 4);
|
||||
*aoffsetp += 32;
|
||||
sprintf (result, "$%g", Fvalue);
|
||||
break;
|
||||
case 'L':
|
||||
Lvalue = dbit_extract (buffer, *aoffsetp, 64);
|
||||
flip_bytes (&Lvalue, 8);
|
||||
*aoffsetp += 64;
|
||||
sprintf (result, "$%g", Lvalue);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x15:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "@|%d|", disp1);
|
||||
break;
|
||||
case 0x16:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
disp2 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "EXT(%d) + %d", disp1, disp2);
|
||||
break;
|
||||
case 0x17:
|
||||
sprintf (result, "tos");
|
||||
break;
|
||||
case 0x18:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "%d(fp)", disp1);
|
||||
break;
|
||||
case 0x19:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "%d(sp)", disp1);
|
||||
break;
|
||||
case 0x1a:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "%d(sb)", disp1);
|
||||
break;
|
||||
case 0x1b:
|
||||
disp1 = get_displacement (buffer, aoffsetp);
|
||||
sprintf (result, "|%d|", addr + disp1);
|
||||
break;
|
||||
case 0x1c:
|
||||
case 0x1d:
|
||||
case 0x1e:
|
||||
case 0x1f:
|
||||
index = bit_extract (buffer, index_offset - 8, 3);
|
||||
print_insn_arg (d, index_offset, aoffsetp, buffer, addr,
|
||||
result, 0);
|
||||
{
|
||||
static char *ind[] = {"b", "w", "d", "q"};
|
||||
char *off;
|
||||
|
||||
off = result + strlen (result);
|
||||
sprintf (off, "[r%d:%s]", index,
|
||||
ind[addr_mode & 3]);
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 'q':
|
||||
Ivalue = bit_extract (buffer, ioffset-4, 4);
|
||||
Ivalue = sign_extend (Ivalue, 4);
|
||||
sprintf (result, "%d", Ivalue);
|
||||
ioffset -= 4;
|
||||
break;
|
||||
case 'r':
|
||||
Ivalue = bit_extract (buffer, ioffset-3, 3);
|
||||
sprintf (result, "r%d", Ivalue&7);
|
||||
ioffset -= 3;
|
||||
break;
|
||||
case 'd':
|
||||
sprintf (result, "%d", get_displacement (buffer, aoffsetp));
|
||||
break;
|
||||
case 'p':
|
||||
sprintf (result, "%c%d%c", NEXT_IS_ADDR,
|
||||
addr + get_displacement (buffer, aoffsetp),
|
||||
NEXT_IS_ADDR);
|
||||
break;
|
||||
case 'i':
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 8);
|
||||
*aoffsetp += 8;
|
||||
sprintf (result, "0x%x", Ivalue);
|
||||
break;
|
||||
}
|
||||
return ioffset;
|
||||
}
|
||||
|
||||
get_displacement (buffer, aoffsetp)
|
||||
char *buffer;
|
||||
int *aoffsetp;
|
||||
{
|
||||
int Ivalue;
|
||||
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 8);
|
||||
switch (Ivalue & 0xc0)
|
||||
{
|
||||
case 0x00:
|
||||
case 0x40:
|
||||
Ivalue = sign_extend (Ivalue, 7);
|
||||
*aoffsetp += 8;
|
||||
break;
|
||||
case 0x80:
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 16);
|
||||
flip_bytes (&Ivalue, 2);
|
||||
Ivalue = sign_extend (Ivalue, 14);
|
||||
*aoffsetp += 16;
|
||||
break;
|
||||
case 0xc0:
|
||||
Ivalue = bit_extract (buffer, *aoffsetp, 32);
|
||||
flip_bytes (&Ivalue, 4);
|
||||
Ivalue = sign_extend (Ivalue, 30);
|
||||
*aoffsetp += 32;
|
||||
break;
|
||||
}
|
||||
return Ivalue;
|
||||
}
|
||||
|
||||
/* Return the number of locals in the current frame given a pc
|
||||
pointing to the enter instruction. This is used in the macro
|
||||
FRAME_FIND_SAVED_REGS. */
|
||||
|
||||
ns32k_localcount (enter_pc)
|
||||
CORE_ADDR enter_pc;
|
||||
{
|
||||
unsigned char localtype;
|
||||
int localcount;
|
||||
|
||||
localtype = read_memory_integer (enter_pc+2, 1);
|
||||
if ((localtype & 0x80) == 0)
|
||||
localcount = localtype;
|
||||
else if ((localtype & 0xc0) == 0x80)
|
||||
localcount = (((localtype & 0x3f) << 8)
|
||||
| (read_memory_integer (enter_pc+3, 1) & 0xff));
|
||||
else
|
||||
localcount = (((localtype & 0x3f) << 24)
|
||||
| ((read_memory_integer (enter_pc+3, 1) & 0xff) << 16)
|
||||
| ((read_memory_integer (enter_pc+4, 1) & 0xff) << 8 )
|
||||
| (read_memory_integer (enter_pc+5, 1) & 0xff));
|
||||
return localcount;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the address of the enter opcode for the function
|
||||
* containing PC, if there is an enter for the function,
|
||||
* and if the pc is between the enter and exit.
|
||||
* Returns positive address if pc is between enter/exit,
|
||||
* 1 if pc before enter or after exit, 0 otherwise.
|
||||
*/
|
||||
|
||||
CORE_ADDR
|
||||
ns32k_get_enter_addr (pc)
|
||||
CORE_ADDR pc;
|
||||
{
|
||||
CORE_ADDR enter_addr;
|
||||
unsigned char op;
|
||||
|
||||
if (ABOUT_TO_RETURN (pc))
|
||||
return 1; /* after exit */
|
||||
|
||||
enter_addr = get_pc_function_start (pc);
|
||||
|
||||
if (pc == enter_addr)
|
||||
return 1; /* before enter */
|
||||
|
||||
op = read_memory_integer (enter_addr, 1);
|
||||
|
||||
if (op != 0x82)
|
||||
return 0; /* function has no enter/exit */
|
||||
|
||||
return enter_addr; /* pc is between enter and exit */
|
||||
return print_insn_ns32k (memaddr, &info);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user