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[AArch64] Cleanup comments in instruction decoding functions
gdb/ChangeLog: * aarch64-tdep.c (decode_cb): Move up comment describing the encoding. (decode_tb): Fix a typo in comment above the function. Move up comment describing the encoding.
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@ -1,3 +1,10 @@
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2015-09-11 Pierre Langlois <pierre.langlois@arm.com>
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* aarch64-tdep.c (decode_cb): Move up comment describing the
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encoding.
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(decode_tb): Fix a typo in comment above the function. Move up
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comment describing the encoding.
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2015-09-11 Pierre Langlois <pierre.langlois@arm.com>
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* aarch64-tdep.c (decode_bcond): Fix incorrect mask.
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@ -401,11 +401,10 @@ static int
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decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
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unsigned *rn, int32_t *offset)
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{
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if (decode_masked_match (insn, 0x7e000000, 0x34000000))
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{
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/* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
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/* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
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if (decode_masked_match (insn, 0x7e000000, 0x34000000))
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{
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*rn = (insn >> 0) & 0x1f;
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*is64 = (insn >> 31) & 0x1;
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*is_cbnz = (insn >> 24) & 0x1;
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@ -628,7 +627,7 @@ decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
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return 0;
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}
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/* Decode an opcode if it represents a TB or TBNZ instruction.
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/* Decode an opcode if it represents a TBZ or TBNZ instruction.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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@ -643,11 +642,10 @@ static int
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decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
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unsigned *rt, int32_t *imm)
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{
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if (decode_masked_match (insn, 0x7e000000, 0x36000000))
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{
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/* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
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/* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
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if (decode_masked_match (insn, 0x7e000000, 0x36000000))
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{
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*rt = (insn >> 0) & 0x1f;
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*is_tbnz = (insn >> 24) & 0x1;
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*bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
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