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* config/tc-mips.c (nops_for_vr4130): Don't check noreorder_p. (nops_for_insn): Likewise. gas/testsuite/ * gas/mips/vr4130.s, gas/mips/vr4130.d: Expect part A to have nops.
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@ -1,3 +1,8 @@
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2009-05-23 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (nops_for_vr4130): Don't check noreorder_p.
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(nops_for_insn): Likewise.
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2009-05-22 H.J. Lu <hongjiu.lu@intel.com>
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* symbols.c (COPIED_SYMFLAGS): Add BSF_GNU_INDIRECT_FUNCTION.
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@ -2679,7 +2679,7 @@ nops_for_vr4130 (const struct mips_cl_insn *history,
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/* Search for the first MFLO or MFHI. */
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for (i = 0; i < MAX_VR4130_NOPS; i++)
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if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
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if (MF_HILO_INSN (history[i].insn_mo->pinfo))
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{
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/* Extract the destination register. */
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if (mips_opts.mips16)
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@ -2714,12 +2714,11 @@ nops_for_insn (const struct mips_cl_insn *history,
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nops = 0;
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for (i = 0; i < MAX_DELAY_NOPS; i++)
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if (!history[i].noreorder_p)
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{
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tmp_nops = insns_between (history + i, insn) - i;
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if (tmp_nops > nops)
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nops = tmp_nops;
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}
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{
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tmp_nops = insns_between (history + i, insn) - i;
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if (tmp_nops > nops)
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nops = tmp_nops;
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}
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if (mips_fix_vr4130)
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{
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@ -1,3 +1,7 @@
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2009-05-23 Richard Sandiford <rdsandiford@googlemail.com>
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* gas/mips/vr4130.s, gas/mips/vr4130.d: Expect part A to have nops.
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2009-05-23 Richard Sandiford <rdsandiford@googlemail.com>
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* gas/mips/align.d: Use an nm test rather than an objdump one.
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@ -11,9 +11,17 @@ Disassembly.*
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# PART A
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#
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.* mfhi .*
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.* nop
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.* nop
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.* nop
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.* nop
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.* mult .*
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#
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.* mflo .*
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.* nop
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.* nop
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.* nop
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.* nop
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.* mult .*
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#
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# PART B
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@ -426,9 +434,17 @@ Disassembly.*
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# PART A
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#
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.* mfhi .*
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.* nop
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.* nop
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.* nop
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.* nop
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.* mult .*
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#
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.* mflo .*
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.* nop
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.* nop
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.* nop
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.* nop
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.* mult .*
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#
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# PART B
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@ -16,8 +16,7 @@
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# PART A
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#
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# Check that mfhis and mflos in .set noreorder blocks are not
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# considered.
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# Check that mfhis and mflos in .set noreorder blocks are considered.
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.set noreorder
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mfhi $2
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