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aarch64: Add +sme2

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This patch adds bare-bones support for +sme2.  Later patches
fill in the rest.
This commit is contained in:
Richard Sandiford 2023-03-30 11:09:10 +01:00
parent 4eede8c244
commit 60336e1965
4 changed files with 7 additions and 0 deletions
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2
gas/NEWS
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@ -1,5 +1,7 @@
-*- text -*-
* Add SME2 support to the AArch64 port.
Changes in 2.40:
* Add support for Intel RAO-INT instructions.

2
gas/config/tc-aarch64.c
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@ -10183,6 +10183,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
{"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
{"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
{"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),

2
gas/doc/c-aarch64.texi
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@ -235,6 +235,8 @@ automatically cause those extensions to be disabled.
@tab Enable SME F64F64 Extension.
@item @code{sme-i16i64} @tab Armv9-A @tab No
@tab Enable SME I16I64 Extension.
@item @code{sme2} @tab Armv9-A @tab No
@tab Enable SME2. This implies @code{sme}.
@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later

1
include/opcode/aarch64.h
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@ -100,6 +100,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SME_I16I64 (1ULL << 58) /* SME I16I64. */
#define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */
#define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */
#define AARCH64_FEATURE_SME2 (1ULL << 61) /* SME2. */
/* Crypto instructions are the combination of AES and SHA2. */
#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)