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opcodes: blackfin: fix style
Non-functional thrashing to the GNU style. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
93252b1cf4
commit
602427c4af
@ -1,3 +1,7 @@
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2011-02-14 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c: Add whitespace/parenthesis where needed.
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2011-02-14 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
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@ -129,19 +129,19 @@ fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
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if (constant_formats[cf].pcrel)
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ea += pc;
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/* truncate to 32-bits for proper symbol lookup/matching */
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ea = (bu32)ea;
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/* truncate to 32-bits for proper symbol lookup/matching */
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ea = (bu32)ea;
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if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
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{
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if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
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{
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outf->print_address_func (ea, outf);
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return "";
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}
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else
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{
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}
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else
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{
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sprintf (buf, "%lx", (unsigned long) x);
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return buf;
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}
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}
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}
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/* Negative constants have an implied sign bit. */
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@ -319,7 +319,7 @@ static const enum machine_registers decode_pregs[] =
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#define pregs(x) REGNAME (decode_pregs[(x) & 7])
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#define spfp(x) REGNAME (decode_spfp[(x) & 1])
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#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
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#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
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#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
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#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
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#define accum(x) REGNAME (decode_accum[(x) & 1])
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@ -358,7 +358,7 @@ static const enum machine_registers decode_gregs[] =
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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};
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#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
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#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
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/* [dregs pregs (iregs mregs) (bregs lregs)]. */
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static const enum machine_registers decode_regs[] =
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@ -369,7 +369,7 @@ static const enum machine_registers decode_regs[] =
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REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
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};
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#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
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#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
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/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
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static const enum machine_registers decode_regs_lo[] =
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@ -380,7 +380,8 @@ static const enum machine_registers decode_regs_lo[] =
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REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
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};
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#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
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#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
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/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
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static const enum machine_registers decode_regs_hi[] =
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{
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@ -390,7 +391,7 @@ static const enum machine_registers decode_regs_hi[] =
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REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
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};
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#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
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#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
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static const enum machine_registers decode_statbits[] =
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{
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@ -443,7 +444,7 @@ static const enum machine_registers decode_allregs[] =
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#define allreg(r,g) (!IS_RESERVEDREG (g, r))
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#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
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#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
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#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
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#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
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#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
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#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
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@ -560,7 +561,7 @@ aligndir (int r0, disassemble_info *outf)
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}
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static int
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decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
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decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
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{
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const char *s0, *s1;
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@ -581,7 +582,7 @@ decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
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}
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static int
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decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
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decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
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{
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const char *a;
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const char *sop = "<unknown op>";
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@ -674,13 +675,13 @@ struct saved_state
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int msize;
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unsigned char *memory;
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unsigned long bfd_mach;
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} saved_state;
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} saved_state;
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#define DREG(x) (saved_state.dpregs[x])
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#define GREG(x,i) DPREG ((x) | (i << 3))
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#define GREG(x, i) DPREG ((x) | ((i) << 3))
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#define DPREG(x) (saved_state.dpregs[x])
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#define DREG(x) (saved_state.dpregs[x])
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#define PREG(x) (saved_state.dpregs[x + 8])
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#define PREG(x) (saved_state.dpregs[(x) + 8])
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#define SPREG PREG (6)
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#define FPREG PREG (7)
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#define IREG(x) (saved_state.iregs[x])
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@ -1379,7 +1380,7 @@ decode_REGMV_0 (TIword iw0, disassemble_info *outf)
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int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
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int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
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/* Reserved slots cannot be a src/dst. */
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/* Reserved slots cannot be a src/dst. */
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if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
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goto invalid_move;
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@ -2086,16 +2087,16 @@ decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
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else
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return 0;
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if (! parallel )
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{
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OUTS (outf, ";\t\t/* ( ");
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if (op == 0 || op == 1)
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OUTS (outf, "2");
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else if (op == 2 || op == 3)
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if (! parallel)
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{
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OUTS (outf, ";\t\t/* ( ");
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if (op == 0 || op == 1)
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OUTS (outf, "2");
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else if (op == 2 || op == 3)
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OUTS (outf, "4");
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OUTS (outf, ") */");
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comment = 1;
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}
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OUTS (outf, ") */");
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comment = 1;
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}
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return 2;
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}
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@ -2739,7 +2740,7 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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OUTS (outf, " (X)");
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}
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else if (H == 0 && S == 1 && Z == 0)
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{
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{
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OUTS (outf, regs (reg, grp));
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OUTS (outf, " = ");
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OUTS (outf, imm16 (hword));
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@ -2796,14 +2797,14 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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}
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if (S == 1 || Z == 1)
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{
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OUTS (outf, ";\t\t/*\t\t");
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OUTS (outf, regs (reg, grp));
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OUTS (outf, "=0x");
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OUTS (outf, huimm32e (*pval));
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OUTS (outf, "(");
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OUTS (outf, imm32 (*pval));
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OUTS (outf, ") */");
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comment = 1;
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OUTS (outf, ";\t\t/*\t\t");
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OUTS (outf, regs (reg, grp));
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OUTS (outf, "=0x");
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OUTS (outf, huimm32e (*pval));
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OUTS (outf, "(");
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OUTS (outf, imm32 (*pval));
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OUTS (outf, ") */");
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comment = 1;
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}
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return 4;
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}
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@ -4364,7 +4365,6 @@ decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
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int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
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if (sop == 0 && sopcde == 0)
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{
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OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
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@ -4692,8 +4692,8 @@ _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
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{
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if (parallel)
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{
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OUTS (outf, "ILLEGAL");
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return 0;
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OUTS (outf, "ILLEGAL");
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return 0;
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}
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OUTS (outf, "MNOP");
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return 4;
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@ -4779,7 +4779,6 @@ _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
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return rv;
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}
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int
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print_insn_bfin (bfd_vma pc, disassemble_info *outf)
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{
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@ -4808,7 +4807,7 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf)
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len = _print_insn_bfin (pc + 4, outf);
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outf->fprintf_func (outf->stream, " || ");
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if (len != 2)
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legal = 0;
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legal = 0;
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len = _print_insn_bfin (pc + 6, outf);
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if (len != 2)
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legal = 0;
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