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x86: ignore high register select bit(s) in 32- and 16-bit modes
While commits9889cbb14e("Check invalid mask registers") andabfcb414b9("X86: Ignore REX_B bit for 32-bit XOP instructions") went a bit into the right direction, this wasn't quite enough: - VEX.vvvv has its high bit ignored - EVEX.vvvv has its high bit ignored together with EVEX.v' - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to allow proper checking of them when the fields has to hold al ones - when the high bits of an immediate specify a register, bit 7 is ignored
This commit is contained in:
Jan Beulich
Jan Beulich
parent
968a13f836
commit
5f847646ee
@ -1,3 +1,9 @@
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2017-11-16 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/noextreg.s: Add tests with register index
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bit 3 set.
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* testsuite/gas/i386/noextreg.d: Adjust expectations.
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2017-11-16 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (process_suffix): Ignore .no_qsuf outside of
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@ -6,13 +6,48 @@
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Disassembly of section .text:
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0+ <ix86>:
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[ ]*[a-f0-9]+: c5 f9 db c0 vpand %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 c1 79 db c0 vpand %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 c1 39 db c0 vpand %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f1 7d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 d1 7d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f1 3d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f1 7d 00 db c0 vpandd %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 79 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 c3 79 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 39 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 79 4c c0 80 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f2 7d 0f 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
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[ ]*[a-f0-9]+: 62 d2 7d 0f 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
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[ ]*[a-f0-9]+: 62 f2 7d 07 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
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[ ]*[a-f0-9]+: c4 e2 78 f2 00 andn \(%eax\),%eax,%eax
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[ ]*[a-f0-9]+: c4 e2 38 f2 00 andn \(%eax\),%eax,%eax
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[ ]*[a-f0-9]+: c4 c2 78 f2 00 andn \(%eax\),%eax,%eax
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[ ]*[a-f0-9]+: c4 e2 f8 f2 00 andn \(%eax\),%eax,%eax
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[ ]*[a-f0-9]+: 8f e9 78 01 20 tzmsk \(%eax\),%eax
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[ ]*[a-f0-9]+: 8f c9 78 01 20 tzmsk \(%eax\),%eax
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[ ]*[a-f0-9]+: 8f e9 38 01 20 tzmsk \(%eax\),%eax
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[ ]*[a-f0-9]+: 8f e9 f8 01 20 tzmsk \(%eax\),%eax
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[ ]*[a-f0-9]+: 8f e9 78 12 c0 llwpcb %eax
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[ ]*[a-f0-9]+: 8f c9 78 12 c0 llwpcb %eax
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[ ]*[a-f0-9]+: 8f e9 f8 12 c0 llwpcb %eax
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[ ]*[a-f0-9]+: 8f e8 78 c0 c0 01 vprotb \$0x1,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f c8 78 c0 c0 01 vprotb \$0x1,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 c0 00 01 vprotb \$0x1,\(%eax\),%xmm0
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[ ]*[a-f0-9]+: 8f c8 78 c0 00 01 vprotb \$0x1,\(%eax\),%xmm0
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[ ]*[a-f0-9]+: 8f e9 78 90 c0 vprotb %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f c9 b8 90 c0 vprotb %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f e9 38 90 c0 vprotb %xmm0,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f e9 78 90 00 vprotb %xmm0,\(%eax\),%xmm0
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[ ]*[a-f0-9]+: 8f c9 78 90 00 vprotb %xmm0,\(%eax\),%xmm0
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[ ]*[a-f0-9]+: 8f e9 f8 90 00 vprotb \(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f c9 f8 90 00 vprotb \(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 79 68 00 00 vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 39 68 00 00 vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 79 68 00 80 vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 79 68 00 0f vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 79 48 00 00 vpermil2ps \$0x0,%xmm0,\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 39 48 00 00 vpermil2ps \$0x0,%xmm0,\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c4 e3 79 48 00 80 vpermil2ps \$0x0,%xmm0,\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: c3 ret[ ]*
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#pass
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@ -1,20 +1,57 @@
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.intel_syntax noprefix
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.text
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ix86:
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vpand xmm0, xmm0, xmm0
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.byte 0xc4, 0xc1, 0x79, 0xdb, 0xc0
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.byte 0xc4, 0xc1, 0x39, 0xdb, 0xc0
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vpandd xmm0, xmm0, xmm0
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.byte 0x62, 0xd1, 0x7d, 0x08, 0xdb, 0xc0
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.byte 0x62, 0xf1, 0x3d, 0x08, 0xdb, 0xc0
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.byte 0x62, 0xf1, 0x7d, 0x00, 0xdb, 0xc0
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vpblendvb xmm0, xmm0, xmm0, xmm0
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.byte 0xc4, 0xc3, 0x79, 0x4c, 0xc0, 0x00
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.byte 0xc4, 0xe3, 0x39, 0x4c, 0xc0, 0x00
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.byte 0xc4, 0xe3, 0x79, 0x4c, 0xc0, 0x80
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vpgatherdd xmm1{k7}, [eax+xmm0]
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.byte 0x62, 0xd2, 0x7d, 0x0f, 0x90, 0x0c, 0x00
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.byte 0x62, 0xf2, 0x7d, 0x07, 0x90, 0x0c, 0x00
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andn eax, eax, [eax]
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# andn rax, rax, [rax]
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.byte 0xc4, 0xe2, 0x38, 0xf2, 0x00
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.byte 0xc4, 0xc2, 0x78, 0xf2, 0x00
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.byte 0xc4, 0xe2, 0xf8, 0xf2, 0x00
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tzmsk eax, [eax]
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# tzmsk rax, [rax]
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.byte 0x8f, 0xc9, 0x78, 0x01, 0x20
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.byte 0x8f, 0xe9, 0x38, 0x01, 0x20
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.byte 0x8f, 0xe9, 0xf8, 0x01, 0x20
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llwpcb eax
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# llwpcb rax
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.byte 0x8f, 0xc9, 0x78, 0x12, 0xc0
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.byte 0x8f, 0xe9, 0xf8, 0x12, 0xc0
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vprotb xmm0, xmm0, 1
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.byte 0x8f, 0xc8, 0x78, 0xc0, 0xc0, 0x01
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vprotb xmm0, [eax], 1
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.byte 0x8f, 0xc8, 0x78, 0xc0, 0x00, 0x01
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vprotb xmm0, xmm0, xmm0
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.byte 0x8f, 0xc9, 0xb8, 0x90, 0xc0
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.byte 0x8f, 0xe9, 0x38, 0x90, 0xc0
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vprotb xmm0, [eax], xmm0
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.byte 0x8f, 0xc9, 0x78, 0x90, 0x00
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vprotb xmm0, xmm0, [eax]
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.byte 0x8f, 0xc9, 0xf8, 0x90, 0x00
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vfmaddps xmm0, xmm0, [eax], xmm0
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# vfmaddps xmm0, xmm0, [eax], xmm0
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.byte 0xc4, 0xe3, 0x39, 0x68, 0x00, 0x00
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.byte 0xc4, 0xe3, 0x79, 0x68, 0x00, 0x80
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.byte 0xc4, 0xe3, 0x79, 0x68, 0x00, 0x0f
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vpermil2ps xmm0, xmm0, [eax], xmm0, 0
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.byte 0xc4, 0xe3, 0x39, 0x48, 0x00, 0x00
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.byte 0xc4, 0xe3, 0x79, 0x48, 0x00, 0x80
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ret
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@ -1,3 +1,14 @@
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2017-11-16 Jan Beulich <jbeulich@suse.com>
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(get_valid_dis386): Never flag bad opcode when
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vex.register_specifier is beyond 7. Always store all four
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bits of it. Move 16-/32-bit override in EVEX handling after
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all to be overridden bits have been set.
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(OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
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Use rex to determine GPR register set.
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(OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
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OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
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2017-11-15 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
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@ -12809,11 +12809,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
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{
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/* In 16/32-bit mode REX_B is silently ignored. */
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rex &= ~REX_B;
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if (vex.register_specifier > 0x7)
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{
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dp = &bad_opcode;
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return dp;
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}
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}
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vex.length = (*codep & 0x4) ? 256 : 128;
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@ -12872,16 +12867,15 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
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{
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if (vex.w)
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rex |= REX_W;
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vex.register_specifier = (~(*codep >> 3)) & 0xf;
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}
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else
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{
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/* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
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is ignored, other REX bits are 0 and the highest bit in
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VEX.vvvv is also ignored. */
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VEX.vvvv is also ignored (but we mustn't clear it here). */
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rex = 0;
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vex.register_specifier = (~(*codep >> 3)) & 0x7;
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}
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vex.register_specifier = (~(*codep >> 3)) & 0xf;
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vex.length = (*codep & 0x4) ? 256 : 128;
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switch ((*codep & 0x3))
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{
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@ -12996,14 +12990,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
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rex |= REX_W;
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vex.register_specifier = (~(*codep >> 3)) & 0xf;
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if (address_mode != mode_64bit)
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{
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/* In 16/32-bit mode silently ignore following bits. */
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rex &= ~REX_B;
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vex.r = 1;
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vex.v = 1;
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vex.register_specifier &= 0x7;
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}
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/* The U bit. */
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if (!(*codep & 0x4))
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@ -13036,6 +13022,14 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
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vex.mask_register_specifier = *codep & 0x7;
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vex.zeroing = *codep & 0x80;
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if (address_mode != mode_64bit)
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{
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/* In 16/32-bit mode silently ignore following bits. */
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rex &= ~REX_B;
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vex.r = 1;
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vex.v = 1;
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}
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need_vex = 1;
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need_vex_reg = 1;
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codep++;
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@ -17098,11 +17092,10 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
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return;
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reg = vex.register_specifier;
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if (vex.evex)
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{
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if (!vex.v)
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reg += 16;
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}
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if (address_mode != mode_64bit)
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reg &= 7;
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else if (vex.evex && !vex.v)
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reg += 16;
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if (bytemode == vex_scalar_mode)
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{
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@ -17287,8 +17280,8 @@ OP_EX_VexReg (int bytemode, int sizeflag, int reg)
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if (rex & REX_B)
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reg += 8;
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}
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else if (reg > 7 && address_mode != mode_64bit)
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BadOp ();
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if (address_mode != mode_64bit)
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reg &= 7;
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}
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switch (vex.length)
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@ -17380,7 +17373,13 @@ OP_Vex_2src_1 (int bytemode, int sizeflag)
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}
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if (vex.w)
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oappend (names_xmm[vex.register_specifier]);
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{
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unsigned int reg = vex.register_specifier;
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if (address_mode != mode_64bit)
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reg &= 7;
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oappend (names_xmm[reg]);
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}
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else
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OP_Vex_2src (bytemode, sizeflag);
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}
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@ -17391,7 +17390,13 @@ OP_Vex_2src_2 (int bytemode, int sizeflag)
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if (vex.w)
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OP_Vex_2src (bytemode, sizeflag);
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else
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oappend (names_xmm[vex.register_specifier]);
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{
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unsigned int reg = vex.register_specifier;
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if (address_mode != mode_64bit)
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reg &= 7;
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oappend (names_xmm[reg]);
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}
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}
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static void
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@ -17434,8 +17439,8 @@ OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
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abort ();
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reg >>= 4;
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if (reg > 7 && address_mode != mode_64bit)
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BadOp ();
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if (address_mode != mode_64bit)
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reg &= 7;
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switch (vex.length)
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{
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@ -17775,13 +17780,16 @@ static void
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OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
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{
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const char **names;
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unsigned int reg = vex.register_specifier;
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if (rex & REX_W)
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names = names64;
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else
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names = names32;
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oappend (names[vex.register_specifier]);
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if (address_mode != mode_64bit)
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reg &= 7;
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oappend (names[reg]);
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}
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static void
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