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2004-11-23 Jan Beulich <jbeulich@novell.com> * config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to indicate the MMX extensions added by both SSE and 3DNow!A. (Cpu3dnowA): Declare. (CpuUnknownFlags): Update. * config/tc-i386.c (cpu_sub_arch_name): Declare. (cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies 3DNow!. Athlon additionally implies 3DNow!A. Several new entries (those starting with a dot are for sub-arch specification). (set_cpu_arch): Handle sub-arch specifications. (parse_insn): Distinguish between instructions not supported because of insufficient CPU features and because of 64-bit mode. * doc/c-i386.texi: Describe enhanced .arch directive. include/opcode/ 2004-11-23 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): paddq and psubq, even in their MMX form, are available only with SSE2. Change the MMX additions introduced by SSE and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A instructions by their now designated identifier (since combining i686 and 3DNow! does not really imply 3DNow!A).
This commit is contained in:
Jan Beulich
parent
871cce518a
commit
5c6af06e4c
@ -1,3 +1,19 @@
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2004-11-23 Jan Beulich <jbeulich@novell.com>
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* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
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indicate the MMX extensions added by both SSE and 3DNow!A.
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(Cpu3dnowA): Declare.
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(CpuUnknownFlags): Update.
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* config/tc-i386.c (cpu_sub_arch_name): Declare.
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(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
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neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
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3DNow!. Athlon additionally implies 3DNow!A. Several new
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entries (those starting with a dot are for sub-arch specification).
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(set_cpu_arch): Handle sub-arch specifications.
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(parse_insn): Distinguish between instructions not supported because
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of insufficient CPU features and because of 64-bit mode.
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* doc/c-i386.texi: Describe enhanced .arch directive.
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2004-11-22 Bob Wilson <bob.wilson@acm.org>
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* config/tc-xtensa.c (xg_add_opcode_fix): Set fx_no_overflow.
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@ -314,6 +314,7 @@ static int quiet_warnings = 0;
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/* CPU name. */
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static const char *cpu_arch_name = NULL;
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static const char *cpu_sub_arch_name = NULL;
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/* CPU feature flags. */
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static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
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@ -416,14 +417,24 @@ static const arch_entry cpu_arch[] = {
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{"i286", Cpu086|Cpu186|Cpu286 },
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{"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
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{"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
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{"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
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{"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
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{"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
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{"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
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{"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
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{"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
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{"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
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{"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
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{"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
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{"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
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{"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
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{"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
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{"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
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{"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
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{"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
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{"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
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{"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
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{"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
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{"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
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{"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
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{".mmx", CpuMMX },
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{".sse", CpuMMX|CpuMMX2|CpuSSE },
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{".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
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{".3dnow", CpuMMX|Cpu3dnow },
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{".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
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{".padlock", CpuPadLock },
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{NULL, 0 }
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};
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@ -836,10 +847,22 @@ set_cpu_arch (dummy)
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{
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if (strcmp (string, cpu_arch[i].name) == 0)
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{
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cpu_arch_name = cpu_arch[i].name;
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cpu_arch_flags = (cpu_arch[i].flags
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| (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
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break;
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if (*string != '.')
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{
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cpu_arch_name = cpu_arch[i].name;
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cpu_sub_arch_name = NULL;
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cpu_arch_flags = (cpu_arch[i].flags
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| (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
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break;
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}
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if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
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{
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cpu_sub_arch_name = cpu_arch[i].name;
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cpu_arch_flags |= cpu_arch[i].flags;
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}
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*input_line_pointer = e;
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demand_empty_rest_of_line ();
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return;
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}
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}
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if (!cpu_arch[i].name)
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@ -1561,6 +1584,8 @@ parse_insn (line, mnemonic)
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char *l = line;
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char *token_start = l;
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char *mnem_p;
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int supported;
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const template *t;
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/* Non-zero if we found a prefix only acceptable with string insns. */
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const char *expecting_string_instruction = NULL;
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@ -1709,11 +1734,29 @@ parse_insn (line, mnemonic)
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}
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/* Check if instruction is supported on specified architecture. */
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if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
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& ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
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supported = 0;
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for (t = current_templates->start; t < current_templates->end; ++t)
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{
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as_warn (_("`%s' is not supported on `%s'"),
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current_templates->start->name, cpu_arch_name);
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if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
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& ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
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supported |= 1;
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if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
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supported |= 2;
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}
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if (!(supported & 2))
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{
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as_bad (flag_code == CODE_64BIT
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? _("`%s' is not supported in 64-bit mode")
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: _("`%s' is only supported in 64-bit mode"),
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current_templates->start->name);
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return NULL;
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}
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if (!(supported & 1))
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{
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as_warn (_("`%s' is not supported on `%s%s'"),
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current_templates->start->name,
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cpu_arch_name,
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cpu_sub_arch_name ? cpu_sub_arch_name : "");
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}
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else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
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{
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@ -174,18 +174,20 @@ typedef struct
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#define CpuAthlon 0x200 /* AMD Athlon or better required*/
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#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
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#define CpuMMX 0x800 /* MMX support required */
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#define CpuSSE 0x1000 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x4000 /* 3dnow! support required */
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#define CpuPNI 0x8000 /* Prescott New Instructions required */
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#define CpuPadLock 0x10000 /* VIA PadLock required */
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#define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */
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#define CpuSSE 0x2000 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x8000 /* 3dnow! support required */
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#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
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#define CpuPNI 0x20000 /* Prescott New Instructions required */
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#define CpuPadLock 0x40000 /* VIA PadLock required */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|CpuK6|CpuAthlon|CpuPadLock)
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -691,15 +691,16 @@ register is @samp{%st(i)}.
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@cindex x86-64 arch directive
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@code{@value{AS}} may be told to assemble for a particular CPU
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architecture with the @code{.arch @var{cpu_type}} directive. This
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(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
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directive enables a warning when gas detects an instruction that is not
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supported on the CPU specified. The choices for @var{cpu_type} are:
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@multitable @columnfractions .20 .20 .20 .20
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@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
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@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
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@item @samp{pentiumpro} @tab @samp{pentium4} @tab @samp{k6} @tab @samp{athlon}
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@item @samp{sledgehammer}
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@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
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@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer}
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@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.3dnow}
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@end multitable
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Apart from the warning, there are only two other effects on
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@ -715,13 +716,14 @@ conditional jumps will be promoted when necessary to a two instruction
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sequence consisting of a conditional jump of the opposite sense around
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an unconditional jump to the target.
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Following the CPU architecture, you may specify @samp{jumps} or
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@samp{nojumps} to control automatic promotion of conditional jumps.
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@samp{jumps} is the default, and enables jump promotion; All external
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jumps will be of the long variety, and file-local jumps will be promoted
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as necessary. (@pxref{i386-Jumps}) @samp{nojumps} leaves external
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conditional jumps as byte offset jumps, and warns about file-local
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conditional jumps that @code{@value{AS}} promotes.
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Following the CPU architecture (but not a sub-architecture, which are those
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starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
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control automatic promotion of conditional jumps. @samp{jumps} is the
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default, and enables jump promotion; All external jumps will be of the long
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variety, and file-local jumps will be promoted as necessary.
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(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
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byte offset jumps, and warns about file-local conditional jumps that
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@code{@value{AS}} promotes.
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Unconditional jumps are treated as for @samp{jumps}.
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For example
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@ -1,3 +1,11 @@
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2004-11-23 Jan Beulich <jbeulich@novell.com>
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* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
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available only with SSE2. Change the MMX additions introduced by SSE
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and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
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instructions by their now designated identifier (since combining i686
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and 3DNow! does not really imply 3DNow!A).
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2004-11-19 Alan Modra <amodra@bigpond.net.au>
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* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
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@ -1020,7 +1020,7 @@ static const template i386_optab[] =
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{"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"paddq", 2, 0x0fd4, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
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{"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
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{"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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@ -1151,7 +1151,7 @@ static const template i386_optab[] =
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{"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
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{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } },
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{"maskmovq", 2, 0x0ff7, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
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{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
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{"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
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{"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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@ -1166,7 +1166,7 @@ static const template i386_optab[] =
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{"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
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{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
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{"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
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{"movntq", 2, 0x0fe7, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } },
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{"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } },
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{"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
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{"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
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{"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
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@ -1175,38 +1175,38 @@ static const template i386_optab[] =
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{"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
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{"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pavgb", 2, 0x0fe0, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
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{"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
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{"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pavgw", 2, 0x0fe3, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
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{"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
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{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
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{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
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{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
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{"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
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{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
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{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
|
||||
{"pmaxsw", 2, 0x0fee, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pmaxub", 2, 0x0fde, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pminsw", 2, 0x0fea, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pminub", 2, 0x0fda, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
|
||||
{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
|
||||
{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
|
||||
{"pmulhuw", 2, 0x0fe4, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"prefetchnta", 1, 0x0f18, 0, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"prefetcht0", 1, 0x0f18, 1, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"prefetcht1", 1, 0x0f18, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"prefetcht2", 1, 0x0f18, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"psadbw", 2, 0x0ff6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
|
||||
{"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
|
||||
{"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pshufw", 3, 0x0f70, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
|
||||
{"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
|
||||
{"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
|
||||
{"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
|
||||
{"sfence", 0, 0x0fae, 0xf8, CpuSSE, NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } },
|
||||
{"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } },
|
||||
{"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
|
||||
{"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
|
||||
@ -1341,7 +1341,7 @@ static const template i386_optab[] =
|
||||
{"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } },
|
||||
{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
@ -1350,8 +1350,8 @@ static const template i386_optab[] =
|
||||
{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
@ -1360,9 +1360,9 @@ static const template i386_optab[] =
|
||||
{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
|
||||
/* AMD extensions. */
|
||||
{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user