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[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
This commit is contained in:
Richard Sandiford
parent
f482d30447
commit
582e12bf76
@ -1,3 +1,18 @@
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
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* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
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to be used with SVE registers.
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(parse_operands): Handle new SVE operands.
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(aarch64_features): Make "sve" require F16 rather than FP. Also
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require COMPNUM.
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* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
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Include compnum tests.
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* testsuite/gas/aarch64/sve.d: Update accordingly.
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* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
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* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
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update expected output for new FMOV and MOV alternatives.
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Add a "compnum" entry.
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@ -837,7 +837,7 @@ elt_size:
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element_size = 64;
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break;
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case 'q':
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if (width == 1)
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if (reg_type == REG_TYPE_ZN || width == 1)
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{
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type = NT_q;
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element_size = 128;
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@ -5431,6 +5431,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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info->qualifier = AARCH64_OPND_QLF_S_D;
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break;
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case AARCH64_OPND_SVE_Zm3_INDEX:
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case AARCH64_OPND_SVE_Zm3_22_INDEX:
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case AARCH64_OPND_SVE_Zm4_INDEX:
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case AARCH64_OPND_SVE_Zn_INDEX:
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reg_type = REG_TYPE_ZN;
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goto vector_reg_index;
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@ -5567,6 +5570,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_IMM_ROT1:
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case AARCH64_OPND_IMM_ROT2:
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case AARCH64_OPND_IMM_ROT3:
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case AARCH64_OPND_SVE_IMM_ROT1:
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case AARCH64_OPND_SVE_IMM_ROT2:
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po_imm_nc_or_fail ();
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info->imm.value = val;
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break;
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@ -6090,6 +6095,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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/* No qualifier. */
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break;
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case AARCH64_OPND_SVE_ADDR_RI_S4x16:
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case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
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case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
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case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
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@ -8436,8 +8442,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
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AARCH64_ARCH_NONE},
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{"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_FP
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| AARCH64_FEATURE_SIMD, 0)},
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AARCH64_FEATURE (AARCH64_FEATURE_F16
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| AARCH64_FEATURE_SIMD
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| AARCH64_FEATURE_COMPNUM, 0)},
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{"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_F16
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| AARCH64_FEATURE_SIMD, 0)},
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@ -158,8 +158,9 @@ automatically cause those extensions to be disabled.
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@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
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@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable Advanced SIMD extensions. This implies @code{fp}.
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@item @code{sve} @tab ARMv8-A @tab No
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@tab Enable the Scalable Vector Extensions. This implies @code{simd}.
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@item @code{sve} @tab ARMv8.2-A @tab No
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@tab Enable the Scalable Vector Extensions. This implies @code{fp16},
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@code{simd} and @code{compnum}.
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@end multitable
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@node AArch64 Syntax
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@ -2,13 +2,15 @@
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.*: Error: operand 2 must be an SVE predicate register -- `fmov z1,z2'
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.*: Error: operand mismatch -- `fmov z1,#1\.0'
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.*: Info: did you mean this\?
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.*: Info: fmov z1\.s, #1\.000000000000000000e\+00
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.*: Info: fmov z1\.h, #1\.000000000000000000e\+00
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.*: Info: other valid variant\(s\):
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.*: Info: fmov z1\.s, #1\.000000000000000000e\+00
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.*: Info: fmov z1\.d, #1\.000000000000000000e\+00
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.*: Error: operand mismatch -- `fmov z1,#0\.0'
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.*: Info: did you mean this\?
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.*: Info: fmov z1\.s, #0\.0
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.*: Info: fmov z1\.h, #0\.0
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.*: Info: other valid variant\(s\):
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.*: Info: fmov z1\.s, #0\.0
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.*: Info: fmov z1\.d, #0\.0
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.*: Error: missing predication type at operand 2 -- `not z0\.s,p1/'
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.*: Error: missing predication type at operand 2 -- `not z0\.s,p1/,z2\.s'
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@ -144,6 +146,7 @@
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.*: Info: mov z0\.h, h0
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.*: Info: mov z0\.s, s0
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.*: Info: mov z0\.d, d0
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.*: Info: mov z0\.q, q0
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.*: Error: operand mismatch -- `mov z0,z1'
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.*: Info: did you mean this\?
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.*: Info: mov z0\.d, z1\.d
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@ -942,3 +945,266 @@
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.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[-1\]'
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.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[8\]'
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.*: Error: constant expression required at operand 2 -- `dup z0\.d,z1\.d\[x0\]'
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.*: Error: operand mismatch -- `fabd z0\.b,p0/m,z0\.b,z0\.b'
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.*: Info: did you mean this\?
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.*: Info: fabd z0\.h, p0/m, z0\.h, z0\.h
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.*: Info: other valid variant\(s\):
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.*: Info: fabd z0\.s, p0/m, z0\.s, z0\.s
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.*: Info: fabd z0\.d, p0/m, z0\.d, z0\.d
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.*: Error: operand mismatch -- `fabd z0\.q,p0/m,z0\.q,z0\.q'
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.*: Info: did you mean this\?
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.*: Info: fabd z0\.h, p0/m, z0\.h, z0\.h
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.*: Info: other valid variant\(s\):
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.*: Info: fabd z0\.s, p0/m, z0\.s, z0\.s
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.*: Info: fabd z0\.d, p0/m, z0\.d, z0\.d
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.*: Error: operand mismatch -- `fcadd z0\.b,p0/m,z0\.b,z0\.b,#90'
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.*: Info: did you mean this\?
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.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
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.*: Info: other valid variant\(s\):
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.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
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.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
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.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#-180'
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.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#-90'
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.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#0'
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.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#89'
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.*: Error: unexpected characters following instruction at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#90\.0'
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.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#180'
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.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#360'
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.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#450'
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.*: Error: operand mismatch -- `fcadd z0\.h,p0/z,z0\.h,z0\.h,#90'
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.*: Info: did you mean this\?
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.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
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.*: Info: other valid variant\(s\):
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.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
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.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
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.*: Error: operand 3 must be the same register as operand 1 -- `fcadd z0\.h,p0/m,z1\.h,z0\.h,#90'
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.*: Error: operand mismatch -- `fcadd z0\.q,p0/m,z0\.q,z0\.q,#90'
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.*: Info: did you mean this\?
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.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
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.*: Info: other valid variant\(s\):
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.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
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.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
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.*: Error: operand mismatch -- `fcmla z0\.b,p0/m,z0\.b,z0\.b,#90'
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.*: Info: did you mean this\?
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.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
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.*: Info: other valid variant\(s\):
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.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
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.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#-180'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#-90'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#89'
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.*: Error: unexpected characters following instruction at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#90\.0'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#360'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#450'
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.*: Error: operand mismatch -- `fcmla z0\.h,p0/z,z0\.h,z0\.h,#90'
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.*: Info: did you mean this\?
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.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
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.*: Info: other valid variant\(s\):
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.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
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.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
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.*: Error: operand mismatch -- `fcmla z0\.q,p0/m,z0\.q,z0\.q,#90'
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.*: Info: did you mean this\?
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.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
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.*: Info: other valid variant\(s\):
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.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
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.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
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.*: Error: operand mismatch -- `fcmla z0\.b,z1\.b,z2\.b\[0\],#0'
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.*: Info: did you mean this\?
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.*: Info: fcmla z0\.h, z1\.h, z2\.h\[0\], #0
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.*: Error: register element index out of range 0 to 3 at operand 3 -- `fcmla z0\.h,z1\.h,z2\.h\[-1\],#0'
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.*: Error: register element index out of range 0 to 3 at operand 3 -- `fcmla z0\.h,z1\.h,z2\.h\[4\],#0'
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.*: Error: z0-z7 expected at operand 3 -- `fcmla z0\.h,z1\.h,z8\.h\[0\],#0'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#-180'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#-90'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#89'
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.*: Error: unexpected characters following instruction at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#90\.0'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#360'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#450'
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.*: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla z0\.s,z1\.s,z2\.s\[-1\],#0'
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.*: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla z0\.s,z1\.s,z2\.s\[2\],#0'
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.*: Error: z0-z15 expected at operand 3 -- `fcmla z0\.s,z1\.s,z16\.s\[0\],#0'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#-180'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#-90'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#89'
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.*: Error: unexpected characters following instruction at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#90\.0'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#360'
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.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#450'
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.*: Error: operand mismatch -- `fcmla z0\.q,z1\.q,z2\.q\[0\],#0'
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.*: Info: did you mean this\?
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.*: Info: fcmla z0\.h, z1\.h, z2\.h\[0\], #0
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.*: Error: operand mismatch -- `fmla z0\.b,z1\.b,z2\.b\[0\]'
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.*: Info: did you mean this\?
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.*: Info: fmla z0\.h, z1\.h, z2\.h\[0\]
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.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmla z0\.h,z1\.h,z2\.h\[-1\]'
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.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmla z0\.h,z1\.h,z2\.h\[8\]'
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.*: Error: z0-z7 expected at operand 3 -- `fmla z0\.h,z1\.h,z8\.h\[0\]'
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.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmla z0\.s,z1\.s,z2\.s\[-1\]'
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.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmla z0\.s,z1\.s,z2\.s\[4\]'
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.*: Error: z0-z7 expected at operand 3 -- `fmla z0\.s,z1\.s,z8\.s\[0\]'
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.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmla z0\.d,z1\.d,z2\.d\[-1\]'
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.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmla z0\.d,z1\.d,z2\.d\[2\]'
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.*: Error: z0-z15 expected at operand 3 -- `fmla z0\.d,z1\.d,z16\.d\[0\]'
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.*: Error: operand mismatch -- `fmla z0\.q,z1\.q,z2\.q\[0\]'
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.*: Info: did you mean this\?
|
||||
.*: Info: fmla z0\.h, z1\.h, z2\.h\[0\]
|
||||
.*: Error: operand mismatch -- `fmls z0\.b,z1\.b,z2\.b\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: fmls z0\.h, z1\.h, z2\.h\[0\]
|
||||
.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmls z0\.h,z1\.h,z2\.h\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmls z0\.h,z1\.h,z2\.h\[8\]'
|
||||
.*: Error: z0-z7 expected at operand 3 -- `fmls z0\.h,z1\.h,z8\.h\[0\]'
|
||||
.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmls z0\.s,z1\.s,z2\.s\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmls z0\.s,z1\.s,z2\.s\[4\]'
|
||||
.*: Error: z0-z7 expected at operand 3 -- `fmls z0\.s,z1\.s,z8\.s\[0\]'
|
||||
.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmls z0\.d,z1\.d,z2\.d\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmls z0\.d,z1\.d,z2\.d\[2\]'
|
||||
.*: Error: z0-z15 expected at operand 3 -- `fmls z0\.d,z1\.d,z16\.d\[0\]'
|
||||
.*: Error: operand mismatch -- `fmls z0\.q,z1\.q,z2\.q\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: fmls z0\.h, z1\.h, z2\.h\[0\]
|
||||
.*: Error: operand mismatch -- `fmul z0\.b,z1\.b,z2\.b\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: fmul z0\.h, z1\.h, z2\.h\[0\]
|
||||
.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmul z0\.h,z1\.h,z2\.h\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmul z0\.h,z1\.h,z2\.h\[8\]'
|
||||
.*: Error: z0-z7 expected at operand 3 -- `fmul z0\.h,z1\.h,z8\.h\[0\]'
|
||||
.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmul z0\.s,z1\.s,z2\.s\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmul z0\.s,z1\.s,z2\.s\[4\]'
|
||||
.*: Error: z0-z7 expected at operand 3 -- `fmul z0\.s,z1\.s,z8\.s\[0\]'
|
||||
.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmul z0\.d,z1\.d,z2\.d\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmul z0\.d,z1\.d,z2\.d\[2\]'
|
||||
.*: Error: z0-z15 expected at operand 3 -- `fmul z0\.d,z1\.d,z16\.d\[0\]'
|
||||
.*: Error: operand mismatch -- `fmul z0\.q,z1\.q,z2\.q\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: fmul z0\.h, z1\.h, z2\.h\[0\]
|
||||
.*: Error: operand mismatch -- `ld1rqb {z0\.b},p0,\[x0,#0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
|
||||
.*: Error: operand mismatch -- `ld1rqb {z0\.b},p0/m,\[x0,#0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
|
||||
.*: Error: p0-p7 expected at operand 2 -- `ld1rqb {z0\.b},p8/z,\[x0,#0\]'
|
||||
.*: Error: immediate offset out of range -128 to 112 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-144\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-15\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-14\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-13\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-12\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-11\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-10\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-9\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-8\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-7\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-6\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-5\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-4\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-3\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-2\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-1\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#1\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#2\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#3\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#4\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#5\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#6\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#7\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#8\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#9\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#10\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#11\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#12\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#13\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#14\]'
|
||||
.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#15\]'
|
||||
.*: Error: immediate offset out of range -128 to 112 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#128\]'
|
||||
.*: Error: operand mismatch -- `ld1rqb {z0\.h},p0/z,\[x0,#0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
|
||||
.*: Error: operand mismatch -- `ld1rqb {z0\.s},p0/z,\[x0,#0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
|
||||
.*: Error: operand mismatch -- `ld1rqb {z0\.d},p0/z,\[x0,#0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
|
||||
.*: Error: operand mismatch -- `ld1rqb {z0\.q},p0/z,\[x0,#0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,xzr\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,xzr,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1,lsl#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,xzr,lsl#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,xzr,lsl#3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl#2\]'
|
||||
.*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: sdot z0\.d, z1\.h, z2\.h
|
||||
.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.d, z1\.h, z2\.h
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b
|
||||
.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: sdot z0\.d, z1\.h, z2\.h
|
||||
.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.d, z1\.h, z2\.h
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b
|
||||
.*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
|
||||
.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
|
||||
.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
|
||||
.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
|
||||
.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: udot z0\.d, z1\.h, z2\.h
|
||||
.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.d, z1\.h, z2\.h
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b
|
||||
.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: udot z0\.d, z1\.h, z2\.h
|
||||
.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.d, z1\.h, z2\.h
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b
|
||||
.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
|
||||
.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
|
||||
.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
|
||||
.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
|
||||
|
||||
@ -1161,3 +1161,166 @@
|
||||
dup z0.d, z1.d[7] // OK
|
||||
dup z0.d, z1.d[8]
|
||||
dup z0.d, z1.d[x0]
|
||||
|
||||
fabd z0.b, p0/m, z0.b, z0.b
|
||||
fabd z0.q, p0/m, z0.q, z0.q
|
||||
|
||||
fcadd z0.b, p0/m, z0.b, z0.b, #90
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #-180
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #-90
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #0
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #89
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #90.0
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #180
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #360
|
||||
fcadd z0.h, p0/m, z0.h, z0.h, #450
|
||||
fcadd z0.h, p0/z, z0.h, z0.h, #90
|
||||
fcadd z0.h, p0/m, z1.h, z0.h, #90
|
||||
fcadd z0.q, p0/m, z0.q, z0.q, #90
|
||||
|
||||
fcmla z0.b, p0/m, z0.b, z0.b, #90
|
||||
fcmla z0.h, p0/m, z0.h, z0.h, #-180
|
||||
fcmla z0.h, p0/m, z0.h, z0.h, #-90
|
||||
fcmla z0.h, p0/m, z0.h, z0.h, #89
|
||||
fcmla z0.h, p0/m, z0.h, z0.h, #90.0
|
||||
fcmla z0.h, p0/m, z0.h, z0.h, #360
|
||||
fcmla z0.h, p0/m, z0.h, z0.h, #450
|
||||
fcmla z0.h, p0/z, z0.h, z0.h, #90
|
||||
fcmla z0.q, p0/m, z0.q, z0.q, #90
|
||||
|
||||
fcmla z0.b, z1.b, z2.b[0], #0
|
||||
fcmla z0.h, z1.h, z2.h[-1], #0
|
||||
fcmla z0.h, z1.h, z2.h[4], #0
|
||||
fcmla z0.h, z1.h, z8.h[0], #0
|
||||
fcmla z0.h, z1.h, z2.h[0], #-180
|
||||
fcmla z0.h, z1.h, z2.h[0], #-90
|
||||
fcmla z0.h, z1.h, z2.h[0], #89
|
||||
fcmla z0.h, z1.h, z2.h[0], #90.0
|
||||
fcmla z0.h, z1.h, z2.h[0], #360
|
||||
fcmla z0.h, z1.h, z2.h[0], #450
|
||||
fcmla z0.s, z1.s, z2.s[-1], #0
|
||||
fcmla z0.s, z1.s, z2.s[2], #0
|
||||
fcmla z0.s, z1.s, z16.s[0], #0
|
||||
fcmla z0.s, z1.s, z2.s[0], #-180
|
||||
fcmla z0.s, z1.s, z2.s[0], #-90
|
||||
fcmla z0.s, z1.s, z2.s[0], #89
|
||||
fcmla z0.s, z1.s, z2.s[0], #90.0
|
||||
fcmla z0.s, z1.s, z2.s[0], #360
|
||||
fcmla z0.s, z1.s, z2.s[0], #450
|
||||
fcmla z0.q, z1.q, z2.q[0], #0
|
||||
|
||||
fmla z0.b, z1.b, z2.b[0]
|
||||
fmla z0.h, z1.h, z2.h[-1]
|
||||
fmla z0.h, z1.h, z2.h[8]
|
||||
fmla z0.h, z1.h, z8.h[0]
|
||||
fmla z0.s, z1.s, z2.s[-1]
|
||||
fmla z0.s, z1.s, z2.s[4]
|
||||
fmla z0.s, z1.s, z8.s[0]
|
||||
fmla z0.d, z1.d, z2.d[-1]
|
||||
fmla z0.d, z1.d, z2.d[2]
|
||||
fmla z0.d, z1.d, z16.d[0]
|
||||
fmla z0.q, z1.q, z2.q[0]
|
||||
|
||||
fmls z0.b, z1.b, z2.b[0]
|
||||
fmls z0.h, z1.h, z2.h[-1]
|
||||
fmls z0.h, z1.h, z2.h[8]
|
||||
fmls z0.h, z1.h, z8.h[0]
|
||||
fmls z0.s, z1.s, z2.s[-1]
|
||||
fmls z0.s, z1.s, z2.s[4]
|
||||
fmls z0.s, z1.s, z8.s[0]
|
||||
fmls z0.d, z1.d, z2.d[-1]
|
||||
fmls z0.d, z1.d, z2.d[2]
|
||||
fmls z0.d, z1.d, z16.d[0]
|
||||
fmls z0.q, z1.q, z2.q[0]
|
||||
|
||||
fmul z0.b, z1.b, z2.b[0]
|
||||
fmul z0.h, z1.h, z2.h[-1]
|
||||
fmul z0.h, z1.h, z2.h[8]
|
||||
fmul z0.h, z1.h, z8.h[0]
|
||||
fmul z0.s, z1.s, z2.s[-1]
|
||||
fmul z0.s, z1.s, z2.s[4]
|
||||
fmul z0.s, z1.s, z8.s[0]
|
||||
fmul z0.d, z1.d, z2.d[-1]
|
||||
fmul z0.d, z1.d, z2.d[2]
|
||||
fmul z0.d, z1.d, z16.d[0]
|
||||
fmul z0.q, z1.q, z2.q[0]
|
||||
|
||||
ld1rqb {z0.b}, p0, [x0, #0]
|
||||
ld1rqb {z0.b}, p0/m, [x0, #0]
|
||||
ld1rqb {z0.b}, p8/z, [x0, #0]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-144]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-15]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-14]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-13]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-12]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-11]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-10]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-9]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-8]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-7]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-6]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-5]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-4]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-3]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-2]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #-1]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #1]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #2]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #3]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #4]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #5]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #6]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #7]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #8]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #9]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #10]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #11]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #12]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #13]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #14]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #15]
|
||||
ld1rqb {z0.b}, p0/z, [x0, #128]
|
||||
ld1rqb {z0.h}, p0/z, [x0, #0]
|
||||
ld1rqb {z0.s}, p0/z, [x0, #0]
|
||||
ld1rqb {z0.d}, p0/z, [x0, #0]
|
||||
ld1rqb {z0.q}, p0/z, [x0, #0]
|
||||
|
||||
ld1rqb {z0.b}, p0/z, [x0, xzr]
|
||||
ld1rqb {z0.b}, p0/z, [x0, x1, lsl #1]
|
||||
ld1rqb {z0.b}, p0/z, [x0, x1, lsl #2]
|
||||
ld1rqb {z0.b}, p0/z, [x0, x1, lsl #3]
|
||||
|
||||
ld1rqh {z0.h}, p0/z, [x0, xzr, lsl #1]
|
||||
ld1rqh {z0.h}, p0/z, [x0, x1]
|
||||
ld1rqh {z0.h}, p0/z, [x0, x1, lsl #2]
|
||||
ld1rqh {z0.h}, p0/z, [x0, x1, lsl #3]
|
||||
|
||||
ld1rqw {z0.s}, p0/z, [x0, xzr, lsl #2]
|
||||
ld1rqw {z0.s}, p0/z, [x0, x1]
|
||||
ld1rqw {z0.s}, p0/z, [x0, x1, lsl #1]
|
||||
ld1rqw {z0.s}, p0/z, [x0, x1, lsl #3]
|
||||
|
||||
ld1rqd {z0.d}, p0/z, [x0, xzr, lsl #3]
|
||||
ld1rqd {z0.d}, p0/z, [x0, x1]
|
||||
ld1rqd {z0.d}, p0/z, [x0, x1, lsl #1]
|
||||
ld1rqd {z0.d}, p0/z, [x0, x1, lsl #2]
|
||||
|
||||
sdot z0.b, z1.b, z2.b
|
||||
sdot z0.h, z1.h, z2.h
|
||||
sdot z0.s, z1.s, z2.s
|
||||
sdot z0.d, z1.d, z2.d
|
||||
|
||||
sdot z0.b, z1.b, z2.b[0]
|
||||
sdot z0.h, z1.h, z2.h[0]
|
||||
sdot z0.s, z1.s, z2.s[0]
|
||||
sdot z0.d, z1.d, z2.d[0]
|
||||
|
||||
udot z0.b, z1.b, z2.b
|
||||
udot z0.h, z1.h, z2.h
|
||||
udot z0.s, z1.s, z2.s
|
||||
udot z0.d, z1.d, z2.d
|
||||
|
||||
udot z0.b, z1.b, z2.b[0]
|
||||
udot z0.h, z1.h, z2.h[0]
|
||||
udot z0.s, z1.s, z2.s[0]
|
||||
udot z0.d, z1.d, z2.d[0]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,10 @@
|
||||
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
|
||||
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
|
||||
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
|
||||
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
|
||||
|
||||
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
|
||||
|
||||
@ -247,6 +247,7 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_PRFOP, /* Prefetch operation. */
|
||||
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
|
||||
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
|
||||
@ -298,6 +299,8 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
|
||||
AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
|
||||
AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
|
||||
AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
|
||||
AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
|
||||
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
|
||||
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
|
||||
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
|
||||
@ -335,6 +338,9 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
|
||||
AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
|
||||
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
|
||||
AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
|
||||
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
|
||||
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
|
||||
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
|
||||
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
|
||||
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
|
||||
|
||||
@ -1,3 +1,51 @@
|
||||
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
|
||||
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
|
||||
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
|
||||
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
|
||||
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
|
||||
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
|
||||
(OP_SVE_V_HSD): New macros.
|
||||
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
|
||||
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
|
||||
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
|
||||
(aarch64_opcode_table): Add new SVE instructions.
|
||||
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
|
||||
for rotation operands. Add new SVE operands.
|
||||
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
|
||||
(ins_sve_quad_index): Likewise.
|
||||
(ins_imm_rotate): Split into...
|
||||
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
|
||||
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
|
||||
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
|
||||
functions.
|
||||
(aarch64_ins_sve_addr_ri_s4): New function.
|
||||
(aarch64_ins_sve_quad_index): Likewise.
|
||||
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
|
||||
* aarch64-asm-2.c: Regenerate.
|
||||
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
|
||||
(ext_sve_quad_index): Likewise.
|
||||
(ext_imm_rotate): Split into...
|
||||
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
|
||||
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
|
||||
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
|
||||
functions.
|
||||
(aarch64_ext_sve_addr_ri_s4): New function.
|
||||
(aarch64_ext_sve_quad_index): Likewise.
|
||||
(aarch64_ext_sve_index): Allow quad indices.
|
||||
(do_misc_decoding): Likewise.
|
||||
* aarch64-dis-2.c: Regenerate.
|
||||
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
|
||||
aarch64_field_kinds.
|
||||
(OPD_F_OD_MASK): Widen by one bit.
|
||||
(OPD_F_NO_ZR): Bump accordingly.
|
||||
(get_operand_field_width): New function.
|
||||
* aarch64-opc.c (fields): Add new SVE fields.
|
||||
(operand_general_constraint_met_p): Handle new SVE operands.
|
||||
(aarch64_print_operand): Likewise.
|
||||
* aarch64-opc-2.c: Regenerate.
|
||||
|
||||
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
|
||||
|
||||
@ -453,7 +453,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1176: /* sys */
|
||||
value = 1176; /* --> sys. */
|
||||
break;
|
||||
case 1934: /* bic */
|
||||
case 1973: /* bic */
|
||||
case 1239: /* and */
|
||||
value = 1239; /* --> and. */
|
||||
break;
|
||||
@ -465,19 +465,19 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1242: /* ands */
|
||||
value = 1242; /* --> ands. */
|
||||
break;
|
||||
case 1935: /* cmple */
|
||||
case 1974: /* cmple */
|
||||
case 1277: /* cmpge */
|
||||
value = 1277; /* --> cmpge. */
|
||||
break;
|
||||
case 1938: /* cmplt */
|
||||
case 1977: /* cmplt */
|
||||
case 1280: /* cmpgt */
|
||||
value = 1280; /* --> cmpgt. */
|
||||
break;
|
||||
case 1936: /* cmplo */
|
||||
case 1975: /* cmplo */
|
||||
case 1282: /* cmphi */
|
||||
value = 1282; /* --> cmphi. */
|
||||
break;
|
||||
case 1937: /* cmpls */
|
||||
case 1976: /* cmpls */
|
||||
case 1285: /* cmphs */
|
||||
value = 1285; /* --> cmphs. */
|
||||
break;
|
||||
@ -489,7 +489,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1308: /* cpy */
|
||||
value = 1308; /* --> cpy. */
|
||||
break;
|
||||
case 1945: /* fmov */
|
||||
case 1984: /* fmov */
|
||||
case 1224: /* mov */
|
||||
case 1309: /* cpy */
|
||||
value = 1309; /* --> cpy. */
|
||||
@ -503,7 +503,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1322: /* dup */
|
||||
value = 1322; /* --> dup. */
|
||||
break;
|
||||
case 1944: /* fmov */
|
||||
case 1983: /* fmov */
|
||||
case 1218: /* mov */
|
||||
case 1323: /* dup */
|
||||
value = 1323; /* --> dup. */
|
||||
@ -512,7 +512,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1324: /* dupm */
|
||||
value = 1324; /* --> dupm. */
|
||||
break;
|
||||
case 1939: /* eon */
|
||||
case 1978: /* eon */
|
||||
case 1326: /* eor */
|
||||
value = 1326; /* --> eor. */
|
||||
break;
|
||||
@ -524,53 +524,53 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1329: /* eors */
|
||||
value = 1329; /* --> eors. */
|
||||
break;
|
||||
case 1940: /* facle */
|
||||
case 1979: /* facle */
|
||||
case 1334: /* facge */
|
||||
value = 1334; /* --> facge. */
|
||||
break;
|
||||
case 1941: /* faclt */
|
||||
case 1980: /* faclt */
|
||||
case 1335: /* facgt */
|
||||
value = 1335; /* --> facgt. */
|
||||
break;
|
||||
case 1942: /* fcmle */
|
||||
case 1344: /* fcmge */
|
||||
value = 1344; /* --> fcmge. */
|
||||
case 1981: /* fcmle */
|
||||
case 1348: /* fcmge */
|
||||
value = 1348; /* --> fcmge. */
|
||||
break;
|
||||
case 1943: /* fcmlt */
|
||||
case 1346: /* fcmgt */
|
||||
value = 1346; /* --> fcmgt. */
|
||||
case 1982: /* fcmlt */
|
||||
case 1350: /* fcmgt */
|
||||
value = 1350; /* --> fcmgt. */
|
||||
break;
|
||||
case 1211: /* fmov */
|
||||
case 1352: /* fcpy */
|
||||
value = 1352; /* --> fcpy. */
|
||||
case 1356: /* fcpy */
|
||||
value = 1356; /* --> fcpy. */
|
||||
break;
|
||||
case 1210: /* fmov */
|
||||
case 1369: /* fdup */
|
||||
value = 1369; /* --> fdup. */
|
||||
case 1379: /* fdup */
|
||||
value = 1379; /* --> fdup. */
|
||||
break;
|
||||
case 1212: /* mov */
|
||||
case 1667: /* orr */
|
||||
value = 1667; /* --> orr. */
|
||||
case 1694: /* orr */
|
||||
value = 1694; /* --> orr. */
|
||||
break;
|
||||
case 1946: /* orn */
|
||||
case 1668: /* orr */
|
||||
value = 1668; /* --> orr. */
|
||||
case 1985: /* orn */
|
||||
case 1695: /* orr */
|
||||
value = 1695; /* --> orr. */
|
||||
break;
|
||||
case 1215: /* mov */
|
||||
case 1670: /* orr */
|
||||
value = 1670; /* --> orr. */
|
||||
case 1697: /* orr */
|
||||
value = 1697; /* --> orr. */
|
||||
break;
|
||||
case 1225: /* movs */
|
||||
case 1671: /* orrs */
|
||||
value = 1671; /* --> orrs. */
|
||||
case 1698: /* orrs */
|
||||
value = 1698; /* --> orrs. */
|
||||
break;
|
||||
case 1220: /* mov */
|
||||
case 1727: /* sel */
|
||||
value = 1727; /* --> sel. */
|
||||
case 1760: /* sel */
|
||||
value = 1760; /* --> sel. */
|
||||
break;
|
||||
case 1223: /* mov */
|
||||
case 1728: /* sel */
|
||||
value = 1728; /* --> sel. */
|
||||
case 1761: /* sel */
|
||||
value = 1761; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
@ -611,9 +611,6 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 26:
|
||||
case 27:
|
||||
case 28:
|
||||
case 144:
|
||||
case 145:
|
||||
case 146:
|
||||
case 147:
|
||||
case 148:
|
||||
case 149:
|
||||
@ -621,9 +618,9 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 151:
|
||||
case 152:
|
||||
case 153:
|
||||
case 166:
|
||||
case 167:
|
||||
case 168:
|
||||
case 154:
|
||||
case 155:
|
||||
case 156:
|
||||
case 169:
|
||||
case 170:
|
||||
case 171:
|
||||
@ -631,7 +628,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 173:
|
||||
case 174:
|
||||
case 175:
|
||||
case 178:
|
||||
case 176:
|
||||
case 177:
|
||||
case 181:
|
||||
case 184:
|
||||
return aarch64_ins_regno (self, info, code, inst);
|
||||
case 13:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst);
|
||||
@ -671,16 +671,16 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 73:
|
||||
case 74:
|
||||
case 75:
|
||||
case 141:
|
||||
case 143:
|
||||
case 158:
|
||||
case 159:
|
||||
case 160:
|
||||
case 144:
|
||||
case 146:
|
||||
case 161:
|
||||
case 162:
|
||||
case 163:
|
||||
case 164:
|
||||
case 165:
|
||||
case 166:
|
||||
case 167:
|
||||
case 168:
|
||||
return aarch64_ins_imm (self, info, code, inst);
|
||||
case 39:
|
||||
case 40:
|
||||
@ -690,10 +690,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 43:
|
||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
|
||||
case 47:
|
||||
case 134:
|
||||
case 135:
|
||||
return aarch64_ins_fpimm (self, info, code, inst);
|
||||
case 61:
|
||||
case 139:
|
||||
case 142:
|
||||
return aarch64_ins_limm (self, info, code, inst);
|
||||
case 62:
|
||||
return aarch64_ins_aimm (self, info, code, inst);
|
||||
@ -703,8 +703,11 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_fbits (self, info, code, inst);
|
||||
case 66:
|
||||
case 67:
|
||||
case 140:
|
||||
return aarch64_ins_imm_rotate2 (self, info, code, inst);
|
||||
case 68:
|
||||
return aarch64_ins_imm_rotate (self, info, code, inst);
|
||||
case 139:
|
||||
return aarch64_ins_imm_rotate1 (self, info, code, inst);
|
||||
case 69:
|
||||
case 70:
|
||||
return aarch64_ins_cond (self, info, code, inst);
|
||||
@ -740,20 +743,21 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 94:
|
||||
return aarch64_ins_hint (self, info, code, inst);
|
||||
case 95:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst);
|
||||
case 96:
|
||||
case 97:
|
||||
case 98:
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
|
||||
case 99:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
|
||||
case 100:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
|
||||
case 101:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
|
||||
case 102:
|
||||
case 103:
|
||||
case 104:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
|
||||
case 105:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
|
||||
case 106:
|
||||
case 107:
|
||||
case 108:
|
||||
@ -765,8 +769,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 114:
|
||||
case 115:
|
||||
case 116:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
|
||||
case 117:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
|
||||
case 118:
|
||||
case 119:
|
||||
case 120:
|
||||
@ -774,44 +778,49 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 122:
|
||||
case 123:
|
||||
case 124:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
|
||||
case 125:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
|
||||
case 126:
|
||||
case 127:
|
||||
case 128:
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
|
||||
case 129:
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
|
||||
case 130:
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
|
||||
case 131:
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
|
||||
case 132:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
|
||||
case 133:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst);
|
||||
case 134:
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst);
|
||||
case 135:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst);
|
||||
case 136:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst);
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst);
|
||||
case 137:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst);
|
||||
case 138:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
|
||||
case 141:
|
||||
return aarch64_ins_inv_limm (self, info, code, inst);
|
||||
case 140:
|
||||
case 143:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst);
|
||||
case 142:
|
||||
case 145:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst);
|
||||
case 154:
|
||||
case 155:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst);
|
||||
case 156:
|
||||
case 157:
|
||||
case 158:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst);
|
||||
case 159:
|
||||
case 160:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst);
|
||||
case 176:
|
||||
return aarch64_ins_sve_index (self, info, code, inst);
|
||||
case 177:
|
||||
case 178:
|
||||
case 179:
|
||||
case 180:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst);
|
||||
case 182:
|
||||
return aarch64_ins_sve_index (self, info, code, inst);
|
||||
case 183:
|
||||
case 185:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
@ -436,38 +436,27 @@ aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Insert field rot for the rotate immediate in
|
||||
FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>. */
|
||||
/* Insert 1-bit rotation immediate (#90 or #270). */
|
||||
const char *
|
||||
aarch64_ins_imm_rotate (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code, const aarch64_inst *inst)
|
||||
aarch64_ins_imm_rotate1 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code, const aarch64_inst *inst)
|
||||
{
|
||||
uint64_t rot = (info->imm.value - 90) / 180;
|
||||
assert (rot < 2U);
|
||||
insert_field (self->fields[0], code, rot, inst->opcode->mask);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Insert 2-bit rotation immediate (#0, #90, #180 or #270). */
|
||||
const char *
|
||||
aarch64_ins_imm_rotate2 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code, const aarch64_inst *inst)
|
||||
{
|
||||
uint64_t rot = info->imm.value / 90;
|
||||
|
||||
switch (info->type)
|
||||
{
|
||||
case AARCH64_OPND_IMM_ROT1:
|
||||
case AARCH64_OPND_IMM_ROT2:
|
||||
/* value rot
|
||||
0 0
|
||||
90 1
|
||||
180 2
|
||||
270 3 */
|
||||
assert (rot < 4U);
|
||||
break;
|
||||
case AARCH64_OPND_IMM_ROT3:
|
||||
/* value rot
|
||||
90 0
|
||||
270 1 */
|
||||
rot = (rot - 1) / 2;
|
||||
assert (rot < 2U);
|
||||
break;
|
||||
default:
|
||||
assert (0);
|
||||
}
|
||||
assert (rot < 4U);
|
||||
insert_field (self->fields[0], code, rot, inst->opcode->mask);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -883,6 +872,20 @@ aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
|
||||
is a 4-bit signed number and where <shift> is SELF's operand-dependent
|
||||
value. fields[0] specifies the base register field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int factor = 1 << get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
|
||||
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
|
||||
value. fields[0] specifies the base register field. */
|
||||
@ -1040,6 +1043,21 @@ aarch64_ins_sve_limm_mov (const aarch64_operand *self,
|
||||
return aarch64_ins_limm (self, info, code, inst);
|
||||
}
|
||||
|
||||
/* Encode Zn[MM], where Zn occupies the least-significant part of the field
|
||||
and where MM occupies the most-significant part. The operand-dependent
|
||||
value specifies the number of bits in Zn. */
|
||||
const char *
|
||||
aarch64_ins_sve_quad_index (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
unsigned int reg_bits = get_operand_specific_data (self);
|
||||
assert (info->reglane.regno < (1U << reg_bits));
|
||||
unsigned int val = (info->reglane.index << reg_bits) + info->reglane.regno;
|
||||
insert_all_fields (self, code, val);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode {Zn.<T> - Zm.<T>}. The fields array specifies which field
|
||||
to use for Zn. */
|
||||
const char *
|
||||
@ -1265,8 +1283,8 @@ do_misc_encoding (aarch64_inst *inst)
|
||||
break;
|
||||
case OP_MOV_Z_V:
|
||||
/* Fill in the zero immediate. */
|
||||
insert_field (FLD_SVE_tsz, &inst->value,
|
||||
1 << aarch64_get_variant (inst), 0);
|
||||
insert_fields (&inst->value, 1 << aarch64_get_variant (inst), 0,
|
||||
2, FLD_imm5, FLD_SVE_tszh);
|
||||
break;
|
||||
case OP_MOV_Z_Z:
|
||||
/* Copy Zn to Zm. */
|
||||
|
||||
@ -71,6 +71,7 @@ AARCH64_DECL_OPD_INSERTER (ins_hint);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_prfop);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
|
||||
@ -88,11 +89,13 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_index);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
|
||||
|
||||
#undef AARCH64_DECL_OPD_INSERTER
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -711,36 +711,26 @@ aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode rotate immediate for FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #rotate. */
|
||||
/* Decode a 1-bit rotate immediate (#90 or #270). */
|
||||
int
|
||||
aarch64_ext_imm_rotate (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
uint64_t rot = extract_field (self->fields[0], code, 0);
|
||||
assert (rot < 2U);
|
||||
info->imm.value = rot * 180 + 90;
|
||||
return 1;
|
||||
}
|
||||
|
||||
switch (info->type)
|
||||
{
|
||||
case AARCH64_OPND_IMM_ROT1:
|
||||
case AARCH64_OPND_IMM_ROT2:
|
||||
/* rot value
|
||||
0 0
|
||||
1 90
|
||||
2 180
|
||||
3 270 */
|
||||
assert (rot < 4U);
|
||||
break;
|
||||
case AARCH64_OPND_IMM_ROT3:
|
||||
/* rot value
|
||||
0 90
|
||||
1 270 */
|
||||
assert (rot < 2U);
|
||||
rot = 2 * rot + 1;
|
||||
break;
|
||||
default:
|
||||
assert (0);
|
||||
return 0;
|
||||
}
|
||||
/* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
|
||||
int
|
||||
aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
uint64_t rot = extract_field (self->fields[0], code, 0);
|
||||
assert (rot < 4U);
|
||||
info->imm.value = rot * 90;
|
||||
return 1;
|
||||
}
|
||||
@ -1364,6 +1354,18 @@ aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
|
||||
is a 4-bit signed number and where <shift> is SELF's operand-dependent
|
||||
value. fields[0] specifies the base register field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3);
|
||||
return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
|
||||
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
|
||||
value. fields[0] specifies the base register field. */
|
||||
@ -1591,7 +1593,7 @@ aarch64_ext_sve_index (const aarch64_operand *self,
|
||||
|
||||
info->reglane.regno = extract_field (self->fields[0], code, 0);
|
||||
val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
|
||||
if ((val & 15) == 0)
|
||||
if ((val & 31) == 0)
|
||||
return 0;
|
||||
while ((val & 1) == 0)
|
||||
val /= 2;
|
||||
@ -1610,6 +1612,21 @@ aarch64_ext_sve_limm_mov (const aarch64_operand *self,
|
||||
&& aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
|
||||
}
|
||||
|
||||
/* Decode Zn[MM], where Zn occupies the least-significant part of the field
|
||||
and where MM occupies the most-significant part. The operand-dependent
|
||||
value specifies the number of bits in Zn. */
|
||||
int
|
||||
aarch64_ext_sve_quad_index (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
unsigned int reg_bits = get_operand_specific_data (self);
|
||||
unsigned int val = extract_all_fields (self, code);
|
||||
info->reglane.regno = val & ((1 << reg_bits) - 1);
|
||||
info->reglane.index = val >> reg_bits;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
|
||||
to use for Zn. The opcode-dependent value specifies the number
|
||||
of registers in the list. */
|
||||
@ -1907,7 +1924,7 @@ do_misc_decoding (aarch64_inst *inst)
|
||||
case OP_MOV_Z_V:
|
||||
/* Index must be zero. */
|
||||
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
|
||||
return value == 1 || value == 2 || value == 4 || value == 8;
|
||||
return value > 0 && value <= 16 && value == (value & -value);
|
||||
|
||||
case OP_MOV_Z_Z:
|
||||
return (extract_field (FLD_SVE_Zn, inst->value, 0)
|
||||
@ -1916,7 +1933,7 @@ do_misc_decoding (aarch64_inst *inst)
|
||||
case OP_MOV_Z_Zi:
|
||||
/* Index must be nonzero. */
|
||||
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
|
||||
return value != 1 && value != 2 && value != 4 && value != 8;
|
||||
return value > 0 && value != (value & -value);
|
||||
|
||||
case OP_MOVM_P_P_P:
|
||||
return (extract_field (FLD_SVE_Pd, inst->value, 0)
|
||||
@ -2573,8 +2590,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
|
||||
break;
|
||||
|
||||
case sve_index:
|
||||
i = extract_field (FLD_SVE_tsz, inst->value, 0);
|
||||
if (i == 0)
|
||||
i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
|
||||
if ((i & 31) == 0)
|
||||
return FALSE;
|
||||
while ((i & 1) == 0)
|
||||
{
|
||||
|
||||
@ -93,6 +93,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s9xvl);
|
||||
@ -110,11 +111,13 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
|
||||
|
||||
#undef AARCH64_DECL_OPD_EXTRACTOR
|
||||
|
||||
|
||||
@ -119,6 +119,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL"},
|
||||
@ -162,6 +163,8 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 1.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 2.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"},
|
||||
@ -199,6 +202,9 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
|
||||
|
||||
@ -290,6 +290,7 @@ const aarch64_field fields[] =
|
||||
{ 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
|
||||
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
|
||||
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
|
||||
{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
|
||||
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
|
||||
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
|
||||
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
|
||||
@ -303,6 +304,8 @@ const aarch64_field fields[] =
|
||||
{ 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
|
||||
{ 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
|
||||
{ 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
|
||||
{ 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
|
||||
{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
|
||||
{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
|
||||
{ 16, 4 }, /* SVE_tsz: triangular size select. */
|
||||
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
|
||||
@ -1474,6 +1477,29 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
case AARCH64_OPND_CLASS_SVE_REG:
|
||||
switch (type)
|
||||
{
|
||||
case AARCH64_OPND_SVE_Zm3_INDEX:
|
||||
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
||||
case AARCH64_OPND_SVE_Zm4_INDEX:
|
||||
size = get_operand_fields_width (get_operand_from_code (type));
|
||||
shift = get_operand_specific_data (&aarch64_operands[type]);
|
||||
mask = (1 << shift) - 1;
|
||||
if (opnd->reg.regno > mask)
|
||||
{
|
||||
assert (mask == 7 || mask == 15);
|
||||
set_other_error (mismatch_detail, idx,
|
||||
mask == 15
|
||||
? _("z0-z15 expected")
|
||||
: _("z0-z7 expected"));
|
||||
return 0;
|
||||
}
|
||||
mask = (1 << (size - shift)) - 1;
|
||||
if (!value_in_range_p (opnd->reglane.index, 0, mask))
|
||||
{
|
||||
set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SVE_Zn_INDEX:
|
||||
size = aarch64_get_qualifier_esize (opnd->qualifier);
|
||||
if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
|
||||
@ -1798,6 +1824,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
|
||||
min_value = -8;
|
||||
max_value = 7;
|
||||
goto sve_imm_offset;
|
||||
|
||||
case AARCH64_OPND_SVE_ADDR_RR:
|
||||
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
|
||||
case AARCH64_OPND_SVE_ADDR_RR_LSL2:
|
||||
@ -2103,6 +2134,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
|
||||
case AARCH64_OPND_IMM_ROT1:
|
||||
case AARCH64_OPND_IMM_ROT2:
|
||||
case AARCH64_OPND_SVE_IMM_ROT2:
|
||||
if (opnd->imm.value != 0
|
||||
&& opnd->imm.value != 90
|
||||
&& opnd->imm.value != 180
|
||||
@ -2115,6 +2147,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_IMM_ROT3:
|
||||
case AARCH64_OPND_SVE_IMM_ROT1:
|
||||
if (opnd->imm.value != 90 && opnd->imm.value != 270)
|
||||
{
|
||||
set_other_error (mismatch_detail, idx,
|
||||
@ -3174,6 +3207,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
print_register_list (buf, size, opnd, "z");
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SVE_Zm3_INDEX:
|
||||
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
||||
case AARCH64_OPND_SVE_Zm4_INDEX:
|
||||
case AARCH64_OPND_SVE_Zn_INDEX:
|
||||
snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
|
||||
aarch64_get_qualifier_name (opnd->qualifier),
|
||||
@ -3214,6 +3250,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_IMM_ROT1:
|
||||
case AARCH64_OPND_IMM_ROT2:
|
||||
case AARCH64_OPND_IMM_ROT3:
|
||||
case AARCH64_OPND_SVE_IMM_ROT1:
|
||||
case AARCH64_OPND_SVE_IMM_ROT2:
|
||||
snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
|
||||
break;
|
||||
|
||||
@ -3461,6 +3499,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_ADDR_SIMM9:
|
||||
case AARCH64_OPND_ADDR_SIMM9_2:
|
||||
case AARCH64_OPND_ADDR_SIMM10:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
|
||||
|
||||
@ -117,6 +117,7 @@ enum aarch64_field_kind
|
||||
FLD_SVE_Zn,
|
||||
FLD_SVE_Zt,
|
||||
FLD_SVE_i1,
|
||||
FLD_SVE_i3h,
|
||||
FLD_SVE_imm3,
|
||||
FLD_SVE_imm4,
|
||||
FLD_SVE_imm5,
|
||||
@ -130,6 +131,8 @@ enum aarch64_field_kind
|
||||
FLD_SVE_msz,
|
||||
FLD_SVE_pattern,
|
||||
FLD_SVE_prfop,
|
||||
FLD_SVE_rot1,
|
||||
FLD_SVE_rot2,
|
||||
FLD_SVE_sz,
|
||||
FLD_SVE_tsz,
|
||||
FLD_SVE_tszh,
|
||||
@ -186,9 +189,9 @@ extern const aarch64_operand aarch64_operands[];
|
||||
value by 2 to get the value
|
||||
of an immediate operand. */
|
||||
#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
|
||||
#define OPD_F_OD_MASK 0x00000060 /* Operand-dependent data. */
|
||||
#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
|
||||
#define OPD_F_OD_LSB 5
|
||||
#define OPD_F_NO_ZR 0x00000080 /* ZR index not allowed. */
|
||||
#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
|
||||
|
||||
static inline bfd_boolean
|
||||
operand_has_inserter (const aarch64_operand *operand)
|
||||
@ -227,6 +230,14 @@ get_operand_specific_data (const aarch64_operand *operand)
|
||||
return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
|
||||
}
|
||||
|
||||
/* Return the width of field number N of operand *OPERAND. */
|
||||
static inline unsigned
|
||||
get_operand_field_width (const aarch64_operand *operand, unsigned n)
|
||||
{
|
||||
assert (operand->fields[n] != FLD_NIL);
|
||||
return fields[operand->fields[n]].width;
|
||||
}
|
||||
|
||||
/* Return the total width of the operand *OPERAND. */
|
||||
static inline unsigned
|
||||
get_operand_fields_width (const aarch64_operand *operand)
|
||||
|
||||
@ -1515,6 +1515,10 @@
|
||||
{ \
|
||||
QLF2(S_H,S_B), \
|
||||
}
|
||||
#define OP_SVE_HMH \
|
||||
{ \
|
||||
QLF3(S_H,P_M,S_H), \
|
||||
}
|
||||
#define OP_SVE_HMD \
|
||||
{ \
|
||||
QLF3(S_H,P_M,S_D), \
|
||||
@ -1605,8 +1609,9 @@
|
||||
QLF3(S_S,P_M,W), \
|
||||
QLF3(S_D,P_M,X), \
|
||||
}
|
||||
#define OP_SVE_VMU_SD \
|
||||
#define OP_SVE_VMU_HSD \
|
||||
{ \
|
||||
QLF3(S_H,P_M,NIL), \
|
||||
QLF3(S_S,P_M,NIL), \
|
||||
QLF3(S_D,P_M,NIL), \
|
||||
}
|
||||
@ -1623,8 +1628,9 @@
|
||||
QLF4(S_S,P_M,S_S,NIL), \
|
||||
QLF4(S_D,P_M,S_D,NIL), \
|
||||
}
|
||||
#define OP_SVE_VMVU_SD \
|
||||
#define OP_SVE_VMVU_HSD \
|
||||
{ \
|
||||
QLF4(S_H,P_M,S_H,NIL), \
|
||||
QLF4(S_S,P_M,S_S,NIL), \
|
||||
QLF4(S_D,P_M,S_D,NIL), \
|
||||
}
|
||||
@ -1635,11 +1641,23 @@
|
||||
QLF4(S_S,P_M,S_S,S_S), \
|
||||
QLF4(S_D,P_M,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VMVV_HSD \
|
||||
{ \
|
||||
QLF4(S_H,P_M,S_H,S_H), \
|
||||
QLF4(S_S,P_M,S_S,S_S), \
|
||||
QLF4(S_D,P_M,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VMVV_SD \
|
||||
{ \
|
||||
QLF4(S_S,P_M,S_S,S_S), \
|
||||
QLF4(S_D,P_M,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VMVVU_HSD \
|
||||
{ \
|
||||
QLF5(S_H,P_M,S_H,S_H,NIL), \
|
||||
QLF5(S_S,P_M,S_S,S_S,NIL), \
|
||||
QLF5(S_D,P_M,S_D,S_D,NIL), \
|
||||
}
|
||||
#define OP_SVE_VMV_BHSD \
|
||||
{ \
|
||||
QLF3(S_B,P_M,S_B), \
|
||||
@ -1658,8 +1676,9 @@
|
||||
QLF3(S_S,P_M,S_S), \
|
||||
QLF3(S_D,P_M,S_D), \
|
||||
}
|
||||
#define OP_SVE_VM_SD \
|
||||
#define OP_SVE_VM_HSD \
|
||||
{ \
|
||||
QLF2(S_H,P_M), \
|
||||
QLF2(S_S,P_M), \
|
||||
QLF2(S_D,P_M), \
|
||||
}
|
||||
@ -1727,8 +1746,9 @@
|
||||
QLF4(S_S,NIL,S_S,S_S), \
|
||||
QLF4(S_D,NIL,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VUVV_SD \
|
||||
#define OP_SVE_VUVV_HSD \
|
||||
{ \
|
||||
QLF4(S_H,NIL,S_H,S_H), \
|
||||
QLF4(S_S,NIL,S_S,S_S), \
|
||||
QLF4(S_D,NIL,S_D,S_D), \
|
||||
}
|
||||
@ -1739,6 +1759,12 @@
|
||||
QLF3(S_S,NIL,S_S), \
|
||||
QLF3(S_D,NIL,S_D), \
|
||||
}
|
||||
#define OP_SVE_VUV_HSD \
|
||||
{ \
|
||||
QLF3(S_H,NIL,S_H), \
|
||||
QLF3(S_S,NIL,S_S), \
|
||||
QLF3(S_D,NIL,S_D), \
|
||||
}
|
||||
#define OP_SVE_VUV_SD \
|
||||
{ \
|
||||
QLF3(S_S,NIL,S_S), \
|
||||
@ -1757,8 +1783,9 @@
|
||||
QLF2(S_S,NIL), \
|
||||
QLF2(S_D,NIL), \
|
||||
}
|
||||
#define OP_SVE_VU_SD \
|
||||
#define OP_SVE_VU_HSD \
|
||||
{ \
|
||||
QLF2(S_H,NIL), \
|
||||
QLF2(S_S,NIL), \
|
||||
QLF2(S_D,NIL), \
|
||||
}
|
||||
@ -1775,8 +1802,17 @@
|
||||
QLF3(S_S,S_S,NIL), \
|
||||
QLF3(S_D,S_D,NIL), \
|
||||
}
|
||||
#define OP_SVE_VVVU_SD \
|
||||
#define OP_SVE_VVVU_H \
|
||||
{ \
|
||||
QLF4(S_H,S_H,S_H,NIL), \
|
||||
}
|
||||
#define OP_SVE_VVVU_S \
|
||||
{ \
|
||||
QLF4(S_S,S_S,S_S,NIL), \
|
||||
}
|
||||
#define OP_SVE_VVVU_HSD \
|
||||
{ \
|
||||
QLF4(S_H,S_H,S_H,NIL), \
|
||||
QLF4(S_S,S_S,S_S,NIL), \
|
||||
QLF4(S_D,S_D,S_D,NIL), \
|
||||
}
|
||||
@ -1787,11 +1823,37 @@
|
||||
QLF3(S_S,S_S,S_S), \
|
||||
QLF3(S_D,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VVV_SD \
|
||||
#define OP_SVE_VVV_D \
|
||||
{ \
|
||||
QLF3(S_D,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VVV_D_H \
|
||||
{ \
|
||||
QLF3(S_D,S_H,S_H), \
|
||||
}
|
||||
#define OP_SVE_VVV_H \
|
||||
{ \
|
||||
QLF3(S_H,S_H,S_H), \
|
||||
}
|
||||
#define OP_SVE_VVV_HSD \
|
||||
{ \
|
||||
QLF3(S_H,S_H,S_H), \
|
||||
QLF3(S_S,S_S,S_S), \
|
||||
QLF3(S_D,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VVV_S \
|
||||
{ \
|
||||
QLF3(S_S,S_S,S_S), \
|
||||
}
|
||||
#define OP_SVE_VVV_S_B \
|
||||
{ \
|
||||
QLF3(S_S,S_B,S_B), \
|
||||
}
|
||||
#define OP_SVE_VVV_SD_BH \
|
||||
{ \
|
||||
QLF3(S_S,S_B,S_B), \
|
||||
QLF3(S_D,S_H,S_H), \
|
||||
}
|
||||
#define OP_SVE_VV_BHSD \
|
||||
{ \
|
||||
QLF2(S_B,S_B), \
|
||||
@ -1799,6 +1861,20 @@
|
||||
QLF2(S_S,S_S), \
|
||||
QLF2(S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VV_BHSDQ \
|
||||
{ \
|
||||
QLF2(S_B,S_B), \
|
||||
QLF2(S_H,S_H), \
|
||||
QLF2(S_S,S_S), \
|
||||
QLF2(S_D,S_D), \
|
||||
QLF2(S_Q,S_Q), \
|
||||
}
|
||||
#define OP_SVE_VV_HSD \
|
||||
{ \
|
||||
QLF2(S_H,S_H), \
|
||||
QLF2(S_S,S_S), \
|
||||
QLF2(S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VV_HSD_BHS \
|
||||
{ \
|
||||
QLF2(S_H,S_B), \
|
||||
@ -1844,18 +1920,21 @@
|
||||
QLF4(S_S,P_Z,S_S,S_S), \
|
||||
QLF4(S_D,P_Z,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VZVV_SD \
|
||||
#define OP_SVE_VZVV_HSD \
|
||||
{ \
|
||||
QLF4(S_H,P_Z,S_H,S_H), \
|
||||
QLF4(S_S,P_Z,S_S,S_S), \
|
||||
QLF4(S_D,P_Z,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VZV_SD \
|
||||
#define OP_SVE_VZV_HSD \
|
||||
{ \
|
||||
QLF3(S_H,P_Z,S_H), \
|
||||
QLF3(S_S,P_Z,S_S), \
|
||||
QLF3(S_D,P_Z,S_D), \
|
||||
}
|
||||
#define OP_SVE_V_SD \
|
||||
#define OP_SVE_V_HSD \
|
||||
{ \
|
||||
QLF1(S_H), \
|
||||
QLF1(S_S), \
|
||||
QLF1(S_D), \
|
||||
}
|
||||
@ -3281,13 +3360,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
CORE_INSN ("bgt", 0x5400000c, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO),
|
||||
CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO),
|
||||
/* SVE instructions. */
|
||||
_SVE_INSN ("fmov", 0x25b9c000, 0xffbfe000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_SD, F_ALIAS, 0),
|
||||
_SVE_INSN ("fmov", 0x0590c000, 0xffb0e000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_SD, F_ALIAS, 0),
|
||||
_SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0),
|
||||
_SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0),
|
||||
_SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSD, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
|
||||
_SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSD, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
|
||||
_SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0),
|
||||
_SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0),
|
||||
_SVE_INSN ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, 0),
|
||||
@ -3393,7 +3472,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
|
||||
_SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
|
||||
_SVE_INSN ("dup", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("dup", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("dupm", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("eor", 0x04a03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0),
|
||||
@ -3403,92 +3482,111 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("eors", 0x25404200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("eorv", 0x04192000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
|
||||
_SVE_INSN ("ext", 0x05200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM8_53), OP_SVE_BBBU, 0, 1),
|
||||
_SVE_INSN ("fabd", 0x65888000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fabs", 0x049ca000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("facge", 0x6580c010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("facgt", 0x6580e010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fadd", 0x65800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
|
||||
_SVE_INSN ("fadd", 0x65808000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fadd", 0x65988000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("fadda", 0x65982000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_SD, 0, 2),
|
||||
_SVE_INSN ("faddv", 0x65802000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmeq", 0x65922000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmeq", 0x65806000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmge", 0x65902000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmge", 0x65804000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fcmgt", 0x65902010, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmgt", 0x65804010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fcmle", 0x65912010, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmlt", 0x65912000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmne", 0x65932000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmne", 0x65806010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0),
|
||||
_SVE_INSN ("fcmuo", 0x6580c000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0),
|
||||
_SVE_INSN ("fcpy", 0x0590c000, 0xffb0e000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_SD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fabd", 0x65088000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fabs", 0x041ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("facge", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("facgt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fadd", 0x65000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fadd", 0x65008000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fadd", 0x65188000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fadda", 0x65182000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_HSD, 0, 2),
|
||||
_SVE_INSN ("faddv", 0x65002000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcadd", 0x64008000, 0xff3ee000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5, SVE_IMM_ROT1), OP_SVE_VMVVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fcmla", 0x64000000, 0xff208000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16, IMM_ROT2), OP_SVE_VMVVU_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmla", 0x64a01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, 0),
|
||||
_SVE_INSN ("fcmla", 0x64e01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, 0),
|
||||
_SVE_INSN ("fcmeq", 0x65122000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmeq", 0x65006000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmge", 0x65102000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmge", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fcmgt", 0x65102010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmgt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fcmle", 0x65112010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmlt", 0x65112000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmne", 0x65132000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmne", 0x65006010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcmuo", 0x6500c000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fcpy", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fcvt", 0x6588a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
|
||||
_SVE_INSN ("fcvt", 0x6589a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
|
||||
_SVE_INSN ("fcvt", 0x65c8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
|
||||
_SVE_INSN ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
|
||||
_SVE_INSN ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
|
||||
_SVE_INSN ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
|
||||
_SVE_INSN ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
|
||||
_SVE_INSN ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
|
||||
_SVE_INSN ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
|
||||
_SVE_INSN ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
|
||||
_SVE_INSN ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
|
||||
_SVE_INSN ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
|
||||
_SVE_INSN ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
|
||||
_SVE_INSN ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
|
||||
_SVE_INSN ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
|
||||
_SVE_INSN ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
|
||||
_SVE_INSN ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
|
||||
_SVE_INSN ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
|
||||
_SVE_INSN ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
|
||||
_SVE_INSN ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
|
||||
_SVE_INSN ("fdiv", 0x658d8000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fdivr", 0x658c8000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fdup", 0x25b9c000, 0xffbfe000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_SD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fexpa", 0x04a0b800, 0xffbffc00, sve_size_sd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_SD, 0, 0),
|
||||
_SVE_INSN ("fmad", 0x65a08000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("fmax", 0x65868000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fmax", 0x659e8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("fmaxnm", 0x65848000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fmaxnm", 0x659c8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("fmaxnmv", 0x65842000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
|
||||
_SVE_INSN ("fmaxv", 0x65862000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
|
||||
_SVE_INSN ("fmin", 0x65878000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fmin", 0x659f8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("fminnm", 0x65858000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fminnm", 0x659d8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("fminnmv", 0x65852000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
|
||||
_SVE_INSN ("fminv", 0x65872000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
|
||||
_SVE_INSN ("fmla", 0x65a00000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("fmls", 0x65a02000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("fmsb", 0x65a0a000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("fmul", 0x65800800, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
|
||||
_SVE_INSN ("fmul", 0x65828000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fmul", 0x659a8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("fmulx", 0x658a8000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fneg", 0x049da000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("fnmad", 0x65a0c000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("fnmla", 0x65a04000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("fnmls", 0x65a06000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("fnmsb", 0x65a0e000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
|
||||
_SVE_INSN ("frecpe", 0x658e3000, 0xffbffc00, sve_size_sd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_SD, 0, 0),
|
||||
_SVE_INSN ("frecps", 0x65801800, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
|
||||
_SVE_INSN ("frecpx", 0x658ca000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frinta", 0x6584a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frinti", 0x6587a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frintm", 0x6582a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frintn", 0x6580a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frintp", 0x6581a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frintx", 0x6586a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frintz", 0x6583a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("frsqrte", 0x658f3000, 0xffbffc00, sve_size_sd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_SD, 0, 0),
|
||||
_SVE_INSN ("frsqrts", 0x65801c00, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
|
||||
_SVE_INSN ("fscale", 0x65898000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fsqrt", 0x658da000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
|
||||
_SVE_INSN ("fsub", 0x65800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
|
||||
_SVE_INSN ("fsub", 0x65818000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fsub", 0x65998000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("fsubr", 0x65838000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("fsubr", 0x659b8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_SD, 0, 2),
|
||||
_SVE_INSN ("ftmad", 0x65908000, 0xffb8fc00, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_SD, 0, 1),
|
||||
_SVE_INSN ("ftsmul", 0x65800c00, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
|
||||
_SVE_INSN ("ftssel", 0x04a0b000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
|
||||
_SVE_INSN ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fmaxnm", 0x65048000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fmaxnm", 0x651c8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fmaxnmv", 0x65042000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmaxv", 0x65062000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmin", 0x65078000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fmin", 0x651f8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fminnm", 0x65058000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fminnm", 0x651d8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fminnmv", 0x65052000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
|
||||
_SVE_INSN ("fminv", 0x65072000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmla", 0x65200000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmla", 0x64200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
|
||||
_SVE_INSN ("fmla", 0x64a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
|
||||
_SVE_INSN ("fmla", 0x64e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
|
||||
_SVE_INSN ("fmls", 0x65202000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmls", 0x64200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
|
||||
_SVE_INSN ("fmls", 0x64a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
|
||||
_SVE_INSN ("fmls", 0x64e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
|
||||
_SVE_INSN ("fmsb", 0x6520a000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmul", 0x65000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fmul", 0x65028000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fmul", 0x651a8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fmul", 0x64202000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
|
||||
_SVE_INSN ("fmul", 0x64a02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
|
||||
_SVE_INSN ("fmul", 0x64e02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
|
||||
_SVE_INSN ("fmulx", 0x650a8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fneg", 0x041da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("fnmad", 0x6520c000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fnmla", 0x65204000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fnmls", 0x65206000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fnmsb", 0x6520e000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
|
||||
_SVE_INSN ("frecpe", 0x650e3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
|
||||
_SVE_INSN ("frecps", 0x65001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
|
||||
_SVE_INSN ("frecpx", 0x650ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frinta", 0x6504a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frinti", 0x6507a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frintm", 0x6502a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frintn", 0x6500a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frintp", 0x6501a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frintx", 0x6506a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frintz", 0x6503a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("frsqrte", 0x650f3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
|
||||
_SVE_INSN ("frsqrts", 0x65001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fscale", 0x65098000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fsqrt", 0x650da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
|
||||
_SVE_INSN ("fsub", 0x65000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
|
||||
_SVE_INSN ("fsub", 0x65018000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fsub", 0x65198000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("fsubr", 0x65038000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
|
||||
_SVE_INSN ("fsubr", 0x651b8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
|
||||
_SVE_INSN ("ftmad", 0x65108000, 0xff38fc00, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_HSD, 0, 1),
|
||||
_SVE_INSN ("ftsmul", 0x65000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
|
||||
_SVE_INSN ("ftssel", 0x0420b000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
|
||||
_SVE_INSN ("incb", 0x0430e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
|
||||
_SVE_INSN ("incd", 0x04f0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
|
||||
_SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
|
||||
@ -3550,6 +3648,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("ld1rh", 0x84c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_HZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rh", 0x84c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rh", 0x84c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqb", 0xa4002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_BZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqb", 0xa4000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqd", 0xa5802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_DZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqd", 0xa5800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqh", 0xa4802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_HZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqh", 0xa4800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqw", 0xa5002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_SZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rqw", 0xa5000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rsb", 0x85c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rsb", 0x85c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0),
|
||||
_SVE_INSN ("ld1rsb", 0x85c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0),
|
||||
@ -3792,12 +3898,18 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
|
||||
_SVE_INSN ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
|
||||
_SVE_INSN ("saddv", 0x04002000, 0xff3fe000, sve_size_bhs, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHS, 0, 0),
|
||||
_SVE_INSN ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
|
||||
_SVE_INSN ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
|
||||
_SVE_INSN ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
|
||||
_SVE_INSN ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
|
||||
_SVE_INSN ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
|
||||
_SVE_INSN ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
|
||||
_SVE_INSN ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
|
||||
_SVE_INSN ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, 0),
|
||||
_SVE_INSN ("sdot", 0x44a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, 0),
|
||||
_SVE_INSN ("sdot", 0x44e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, 0),
|
||||
_SVE_INSN ("sel", 0x0520c000, 0xff20c000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg4_10, SVE_Zn, SVE_Zm_16), OP_SVE_VUVV_BHSD, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("sel", 0x25004210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BUBB, F_HAS_ALIAS, 0),
|
||||
_SVE_INSN ("setffr", 0x252c9000, 0xffffffff, sve_misc, 0, OP0 (), {}, 0, 0),
|
||||
@ -3938,12 +4050,18 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("trn2", 0x05207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
|
||||
_SVE_INSN ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
|
||||
_SVE_INSN ("uaddv", 0x04012000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHSD, 0, 0),
|
||||
_SVE_INSN ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
|
||||
_SVE_INSN ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
|
||||
_SVE_INSN ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
|
||||
_SVE_INSN ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
|
||||
_SVE_INSN ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
|
||||
_SVE_INSN ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
|
||||
_SVE_INSN ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
|
||||
_SVE_INSN ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
|
||||
_SVE_INSN ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, 0),
|
||||
_SVE_INSN ("udot", 0x44a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, 0),
|
||||
_SVE_INSN ("udot", 0x44e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, 0),
|
||||
_SVE_INSN ("umax", 0x2529c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, 1),
|
||||
_SVE_INSN ("umax", 0x04090000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
|
||||
_SVE_INSN ("umaxv", 0x04092000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
|
||||
@ -4011,12 +4129,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_SVE_INSN ("cmpls", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("cmplt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("eon", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
|
||||
_SVE_INSN ("facle", 0x6580c010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("faclt", 0x6580e010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fcmle", 0x65804000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fcmlt", 0x65804010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fmov", 0x25b8c000, 0xffbfffe0, sve_size_sd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_SD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fmov", 0x05904000, 0xffb0ffe0, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_SD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("facle", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("faclt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fcmle", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fcmlt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fmov", 0x2538c000, 0xff3fffe0, sve_size_hsd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_HSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, 0),
|
||||
_SVE_INSN ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
|
||||
|
||||
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, NULL},
|
||||
@ -4147,11 +4265,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
|
||||
"the number of bits after the binary point in the fixed-point value")\
|
||||
X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \
|
||||
Y(IMMEDIATE, imm_rotate, "IMM_ROT1", 0, F(FLD_rotate1), \
|
||||
Y(IMMEDIATE, imm_rotate2, "IMM_ROT1", 0, F(FLD_rotate1), \
|
||||
"a 2-bit rotation specifier for complex arithmetic operations") \
|
||||
Y(IMMEDIATE, imm_rotate, "IMM_ROT2", 0, F(FLD_rotate2), \
|
||||
Y(IMMEDIATE, imm_rotate2, "IMM_ROT2", 0, F(FLD_rotate2), \
|
||||
"a 2-bit rotation specifier for complex arithmetic operations") \
|
||||
Y(IMMEDIATE, imm_rotate, "IMM_ROT3", 0, F(FLD_rotate3), \
|
||||
Y(IMMEDIATE, imm_rotate1, "IMM_ROT3", 0, F(FLD_rotate3), \
|
||||
"a 1-bit rotation specifier for complex arithmetic operations") \
|
||||
Y(COND, cond, "COND", 0, F(), "a condition") \
|
||||
Y(COND, cond, "COND1", 0, F(), \
|
||||
@ -4203,6 +4321,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"a prefetch operation specifier") \
|
||||
Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \
|
||||
"the PSB option name CSYNC") \
|
||||
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
|
||||
4 << OPD_F_OD_LSB, F(FLD_Rn), \
|
||||
"an address with a 4-bit signed offset, multiplied by 16") \
|
||||
Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \
|
||||
0 << OPD_F_OD_LSB, F(FLD_Rn), \
|
||||
"an address with a 4-bit signed offset, multiplied by VL") \
|
||||
@ -4320,6 +4441,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
F(FLD_SVE_i1), "either 0.5 or 2.0") \
|
||||
Y(IMMEDIATE, sve_float_zero_one, "SVE_I1_ZERO_ONE", 0, \
|
||||
F(FLD_SVE_i1), "either 0.0 or 1.0") \
|
||||
Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT1", 0, F(FLD_SVE_rot1), \
|
||||
"a 1-bit rotation specifier for complex arithmetic operations") \
|
||||
Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \
|
||||
"a 2-bit rotation specifier for complex arithmetic operations") \
|
||||
Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \
|
||||
F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \
|
||||
"an inverted 13-bit logical immediate") \
|
||||
@ -4393,6 +4518,15 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"an SVE vector register") \
|
||||
Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \
|
||||
"an SVE vector register") \
|
||||
Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \
|
||||
3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
|
||||
"an indexed SVE vector register") \
|
||||
Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
|
||||
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
|
||||
"an indexed SVE vector register") \
|
||||
Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \
|
||||
4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
|
||||
"an indexed SVE vector register") \
|
||||
Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \
|
||||
"an SVE vector register") \
|
||||
Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user