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gas/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX. Check memory size in Intel mode. (process_suffix): Handle XMMWORD_MNEM_SUFFIX. (intel_e09): Likewise. * config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New. gas/testsuite/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * gas/i386/intel.s: Use QWORD on movq instead of DWORD. * gas/i386/inval.s: Add tests for movq. * gas/i386/x86-64-inval.s: Likewise. * gas/i386/inval.l: Updated. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize, Byte, Word, Dword, QWord and Xmmword. * i386-opc.h (No_xSuf): New. (CheckSize): Likewise. (Byte): Likewise. (Word): Likewise. (Dword): Likewise. (QWord): Likewise. (Xmmword): Likewise. (FWait): Updated. (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word, Dword, QWord and Xmmword. * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is used. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
6c7ac64e17
commit
582d5eddfe
@ -1,3 +1,13 @@
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2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/5534
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* config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX.
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Check memory size in Intel mode.
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(process_suffix): Handle XMMWORD_MNEM_SUFFIX.
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(intel_e09): Likewise.
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* config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New.
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2008-01-02 Catherine Moore <clm@codesourcery.com>
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* config/tc-mips.c (mips_ip): Check operands on jalr instruction.
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@ -3047,6 +3047,8 @@ match_template (void)
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suffix_check.no_qsuf = 1;
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else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
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suffix_check.no_ldsuf = 1;
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else if (i.suffix == XMMWORD_MNEM_SUFFIX)
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suffix_check.no_xsuf = 1;
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for (t = current_templates->start; t < current_templates->end; t++)
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{
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@ -3077,6 +3079,18 @@ match_template (void)
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|| (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
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continue;
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/* Check the memory size in Intel mode when it is provided if
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needed. */
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if (intel_syntax
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&& i.suffix
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&& t->opcode_modifier.checksize
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&& (!t->opcode_modifier.byte || !suffix_check.no_bsuf)
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&& (!t->opcode_modifier.word || !suffix_check.no_wsuf)
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&& (!t->opcode_modifier.dword || !suffix_check.no_lsuf)
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&& (!t->opcode_modifier.qword || !suffix_check.no_qsuf)
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&& (!t->opcode_modifier.xmmword || !suffix_check.no_xsuf))
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continue;
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for (j = 0; j < MAX_OPERANDS; j++)
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operand_types [j] = t->operand_types [j];
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@ -3453,6 +3467,11 @@ process_suffix (void)
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if (!check_word_reg ())
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return 0;
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}
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else if (i.suffix == XMMWORD_MNEM_SUFFIX)
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{
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/* Skip if the instruction has x suffix. match_template
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should check if it is a valid suffix. */
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}
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else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
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/* Do nothing if the instruction is going to ignore the prefix. */
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;
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@ -3535,7 +3554,9 @@ process_suffix (void)
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/* Change the opcode based on the operand size given by i.suffix;
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We don't need to change things for byte insns. */
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if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
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if (i.suffix
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&& i.suffix != BYTE_MNEM_SUFFIX
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&& i.suffix != XMMWORD_MNEM_SUFFIX)
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{
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/* It's not a byte, select word/dword operation. */
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if (i.tm.opcode_modifier.w)
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@ -8166,8 +8187,7 @@ intel_e09 (void)
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else if (prev_token.code == T_XMMWORD)
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{
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/* XXX ignored for now, but accepted since gcc uses it */
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suffix = 0;
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suffix = XMMWORD_MNEM_SUFFIX;
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}
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else
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@ -116,12 +116,14 @@ extern const char *i386_comment_chars;
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#define IMMEDIATE_PREFIX '$'
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#define ABSOLUTE_PREFIX '*'
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/* these are the instruction mnemonic suffixes. */
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/* these are the instruction mnemonic suffixes in AT&T syntax or
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memory operand size in Intel syntax. */
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#define WORD_MNEM_SUFFIX 'w'
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#define BYTE_MNEM_SUFFIX 'b'
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#define SHORT_MNEM_SUFFIX 's'
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#define LONG_MNEM_SUFFIX 'l'
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#define QWORD_MNEM_SUFFIX 'q'
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#define XMMWORD_MNEM_SUFFIX 'x'
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/* Intel Syntax. Use a non-ascii letter since since it never appears
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in instructions. */
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#define LONG_DOUBLE_MNEM_SUFFIX '\1'
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@ -1,3 +1,14 @@
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2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/5534
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* gas/i386/intel.s: Use QWORD on movq instead of DWORD.
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* gas/i386/inval.s: Add tests for movq.
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* gas/i386/x86-64-inval.s: Likewise.
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* gas/i386/inval.l: Updated.
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* gas/i386/x86-64-inval.l: Likewise.
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2008-01-02 Catherine Moore <clm@codesourcery.com>
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* gas/mips/jalr.s: New test.
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@ -601,7 +601,7 @@ rot5:
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1:
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jne 1b
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movq mm6, [DWORD PTR .LC5+40]
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movq mm6, [QWORD PTR .LC5+40]
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add edi, dword ptr [ebx+8*eax]
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movd mm0, dword ptr [ebx+8*eax+4]
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add edi, dword ptr [ebx+8*ecx+((4095+1)*8)]
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@ -53,6 +53,14 @@
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.*:56: Error: .*
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.*:57: Error: .*
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.*:58: Error: .*
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.*:59: Error: .*
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.*:60: Error: .*
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.*:61: Error: .*
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.*:62: Error: .*
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.*:63: Error: .*
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.*:64: Error: .*
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.*:65: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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@ -117,3 +125,11 @@ GAS LISTING .*
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[ ]*58[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
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[ ]*59[ ]+movq xmm1, XMMWORD PTR \[esp\]
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[ ]*60[ ]+movq xmm1, DWORD PTR \[esp\]
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[ ]*61[ ]+movq xmm1, WORD PTR \[esp\]
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[ ]*62[ ]+movq xmm1, BYTE PTR \[esp\]
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[ ]*63[ ]+movq XMMWORD PTR \[esp\],xmm1
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[ ]*64[ ]+movq DWORD PTR \[esp\],xmm1
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[ ]*65[ ]+movq WORD PTR \[esp\],xmm1
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[ ]*66[ ]+movq BYTE PTR \[esp\],xmm1
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@ -56,3 +56,11 @@ foo: jaw foo
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cvtsi2sd xmm1,QWORD PTR [eax]
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cvtsi2ssq xmm1,QWORD PTR [eax]
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cvtsi2sdq xmm1,QWORD PTR [eax]
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movq xmm1, XMMWORD PTR [esp]
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movq xmm1, DWORD PTR [esp]
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movq xmm1, WORD PTR [esp]
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movq xmm1, BYTE PTR [esp]
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movq XMMWORD PTR [esp],xmm1
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movq DWORD PTR [esp],xmm1
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movq WORD PTR [esp],xmm1
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movq BYTE PTR [esp],xmm1
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@ -50,60 +50,79 @@
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.*:51: Error: .*
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.*:52: Error: .*
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.*:54: Error: .*
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.*:55: Error: .*
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.*:56: Error: .*
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.*:57: Error: .*
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.*:58: Error: .*
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.*:59: Error: .*
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.*:60: Error: .*
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.*:61: Error: .*
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.*:62: Error: .*
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GAS LISTING .*
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1 [ ]*.text
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2 [ ]*# All the following should be illegal for x86-64
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3 [ ]*aaa # illegal
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4 [ ]*aad # illegal
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5 [ ]*aam # illegal
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6 [ ]*aas # illegal
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7 [ ]*arpl %ax,%ax # illegal
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8 [ ]*bound %eax,\(%rax\) # illegal
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9 [ ]*calll \*%eax # 32-bit data size not allowed
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10 [ ]*calll \*\(%ax\) # 32-bit data size not allowed
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11 [ ]*calll \*\(%eax\) # 32-bit data size not allowed
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12 [ ]*calll \*\(%r8\) # 32-bit data size not allowed
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13 [ ]*calll \*\(%rax\) # 32-bit data size not allowed
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14 [ ]*callq \*\(%ax\) # 32-bit data size not allowed
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15 [ ]*callw \*\(%ax\) # no 16-bit addressing
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16 [ ]*daa # illegal
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17 [ ]*das # illegal
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18 [ ]*enterl \$0,\$0 # can't have 32-bit stack operands
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19 [ ]*into # illegal
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20 [ ]*foo:[ ]*jcxz foo # No prefix exists to select CX as a counter
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21 [ ]*jmpl \*%eax # 32-bit data size not allowed
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22 [ ]*jmpl \*\(%rax\) # 32-bit data size not allowed
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23 [ ]*lcalll \$0,\$0 # illegal
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24 [ ]*lcallq \$0,\$0 # illegal
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25 [ ]*ldsl %eax,\(%rax\) # illegal
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26 [ ]*ldsq %rax,\(%rax\) # illegal
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27 [ ]*lesl %eax,\(%rax\) # illegal
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28 [ ]*lesq %rax,\(%rax\) # illegal
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29 [ ]*ljmpl \$0,\$0 # illegal
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30 [ ]*ljmpq \$0,\$0 # illegal
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31 [ ]*ljmpq \*\(%rax\) # 64-bit data size not allowed
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32 [ ]*loopw foo # No prefix exists to select CX as a counter
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33 [ ]*loopew foo # No prefix exists to select CX as a counter
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34 [ ]*loopnew foo # No prefix exists to select CX as a counter
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35 [ ]*loopnzw foo # No prefix exists to select CX as a counter
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36 [ ]*loopzw foo # No prefix exists to select CX as a counter
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37 [ ]*leavel # can't have 32-bit stack operands
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38 [ ]*pop %ds # illegal
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39 [ ]*pop %es # illegal
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40 [ ]*pop %ss # illegal
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41 [ ]*popa # illegal
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42 [ ]*popl %eax # can't have 32-bit stack operands
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43 [ ]*push %cs # illegal
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44 [ ]*push %ds # illegal
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45 [ ]*push %es # illegal
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46 [ ]*push %ss # illegal
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47 [ ]*pusha # illegal
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48 [ ]*pushl %eax # can't have 32-bit stack operands
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49 [ ]*pushfl # can't have 32-bit stack operands
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50 [ ]*popfl # can't have 32-bit stack operands
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51 [ ]*retl # can't have 32-bit stack operands
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52 [ ]*insertq \$4,\$2,%xmm2,%ebx # The last operand must be XMM register.
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53 [ ]*.intel_syntax noprefix
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54 [ ]*cmpxchg16b dword ptr \[rax\] # Must be oword
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[ ]*1[ ]+\.text
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[ ]*2[ ]+\# All the following should be illegal for x86-64
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[ ]*3[ ]+aaa \# illegal
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[ ]*4[ ]+aad \# illegal
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[ ]*5[ ]+aam \# illegal
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[ ]*6[ ]+aas \# illegal
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[ ]*7[ ]+arpl %ax,%ax \# illegal
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[ ]*8[ ]+bound %eax,\(%rax\) \# illegal
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[ ]*9[ ]+calll \*%eax \# 32-bit data size not allowed
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[ ]*10[ ]+calll \*\(%ax\) \# 32-bit data size not allowed
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[ ]*11[ ]+calll \*\(%eax\) \# 32-bit data size not allowed
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[ ]*12[ ]+calll \*\(%r8\) \# 32-bit data size not allowed
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[ ]*13[ ]+calll \*\(%rax\) \# 32-bit data size not allowed
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[ ]*14[ ]+callq \*\(%ax\) \# 32-bit data size not allowed
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[ ]*15[ ]+callw \*\(%ax\) \# no 16-bit addressing
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[ ]*16[ ]+daa \# illegal
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[ ]*17[ ]+das \# illegal
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[ ]*18[ ]+enterl \$0,\$0 \# can't have 32-bit stack operands
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[ ]*19[ ]+into \# illegal
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[ ]*20[ ]+foo: jcxz foo \# No prefix exists to select CX as a counter
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[ ]*21[ ]+jmpl \*%eax \# 32-bit data size not allowed
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[ ]*22[ ]+jmpl \*\(%rax\) \# 32-bit data size not allowed
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[ ]*23[ ]+lcalll \$0,\$0 \# illegal
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[ ]*24[ ]+lcallq \$0,\$0 \# illegal
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[ ]*25[ ]+ldsl %eax,\(%rax\) \# illegal
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[ ]*26[ ]+ldsq %rax,\(%rax\) \# illegal
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[ ]*27[ ]+lesl %eax,\(%rax\) \# illegal
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[ ]*28[ ]+lesq %rax,\(%rax\) \# illegal
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[ ]*29[ ]+ljmpl \$0,\$0 \# illegal
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[ ]*30[ ]+ljmpq \$0,\$0 \# illegal
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[ ]*31[ ]+ljmpq \*\(%rax\) \# 64-bit data size not allowed
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[ ]*32[ ]+loopw foo \# No prefix exists to select CX as a counter
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[ ]*33[ ]+loopew foo \# No prefix exists to select CX as a counter
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[ ]*34[ ]+loopnew foo \# No prefix exists to select CX as a counter
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[ ]*35[ ]+loopnzw foo \# No prefix exists to select CX as a counter
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[ ]*36[ ]+loopzw foo \# No prefix exists to select CX as a counter
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[ ]*37[ ]+leavel \# can't have 32-bit stack operands
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[ ]*38[ ]+pop %ds \# illegal
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[ ]*39[ ]+pop %es \# illegal
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[ ]*40[ ]+pop %ss \# illegal
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[ ]*41[ ]+popa \# illegal
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[ ]*42[ ]+popl %eax \# can't have 32-bit stack operands
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[ ]*43[ ]+push %cs \# illegal
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[ ]*44[ ]+push %ds \# illegal
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[ ]*45[ ]+push %es \# illegal
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[ ]*46[ ]+push %ss \# illegal
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[ ]*47[ ]+pusha \# illegal
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[ ]*48[ ]+pushl %eax \# can't have 32-bit stack operands
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[ ]*49[ ]+pushfl \# can't have 32-bit stack operands
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[ ]*50[ ]+popfl \# can't have 32-bit stack operands
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[ ]*51[ ]+retl \# can't have 32-bit stack operands
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[ ]*52[ ]+insertq \$4,\$2,%xmm2,%ebx \# The last operand must be XMM register\.
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[ ]*53[ ]+\.intel_syntax noprefix
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[ ]*54[ ]+cmpxchg16b dword ptr \[rax\] \# Must be oword
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[ ]*55[ ]+movq xmm1, XMMWORD PTR \[rsp\]
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[ ]*56[ ]+movq xmm1, DWORD PTR \[rsp\]
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[ ]*57[ ]+movq xmm1, WORD PTR \[rsp\]
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GAS LISTING .*
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[ ]*58[ ]+movq xmm1, BYTE PTR \[rsp\]
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[ ]*59[ ]+movq XMMWORD PTR \[rsp\],xmm1
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[ ]*60[ ]+movq DWORD PTR \[rsp\],xmm1
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[ ]*61[ ]+movq WORD PTR \[rsp\],xmm1
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[ ]*62[ ]+movq BYTE PTR \[rsp\],xmm1
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@ -52,3 +52,11 @@ foo: jcxz foo # No prefix exists to select CX as a counter
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insertq $4,$2,%xmm2,%ebx # The last operand must be XMM register.
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.intel_syntax noprefix
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cmpxchg16b dword ptr [rax] # Must be oword
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movq xmm1, XMMWORD PTR [rsp]
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movq xmm1, DWORD PTR [rsp]
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movq xmm1, WORD PTR [rsp]
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movq xmm1, BYTE PTR [rsp]
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movq XMMWORD PTR [rsp],xmm1
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movq DWORD PTR [rsp],xmm1
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movq WORD PTR [rsp],xmm1
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movq BYTE PTR [rsp],xmm1
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@ -1,3 +1,24 @@
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2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/5534
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* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
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Byte, Word, Dword, QWord and Xmmword.
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* i386-opc.h (No_xSuf): New.
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(CheckSize): Likewise.
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(Byte): Likewise.
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(Word): Likewise.
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(Dword): Likewise.
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(QWord): Likewise.
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(Xmmword): Likewise.
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(FWait): Updated.
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(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
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Dword, QWord and Xmmword.
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* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
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used.
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* i386-tbl.h: Regenerated.
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2008-01-02 Mark Kettenis <kettenis@gnu.org>
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* m88k-dis.c (instructions): Fix fcvt.* instructions.
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@ -274,6 +274,13 @@ static bitfield opcode_modifiers[] =
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BITFIELD (No_sSuf),
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BITFIELD (No_qSuf),
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BITFIELD (No_ldSuf),
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BITFIELD (No_xSuf),
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BITFIELD (CheckSize),
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BITFIELD (Byte),
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BITFIELD (Word),
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BITFIELD (Dword),
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BITFIELD (QWord),
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BITFIELD (Xmmword),
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BITFIELD (FWait),
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BITFIELD (IsString),
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BITFIELD (RegKludge),
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@ -191,8 +191,22 @@ typedef union i386_cpu_flags
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#define No_qSuf (No_sSuf + 1)
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/* long double suffix on instruction illegal */
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#define No_ldSuf (No_qSuf + 1)
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/* x suffix on instruction illegal */
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#define No_xSuf (No_ldSuf + 1)
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/* check PTR size on instruction */
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#define CheckSize (No_xSuf + 1)
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/* BYTE PTR on instruction */
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#define Byte (CheckSize + 1)
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/* WORD PTR on instruction */
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#define Word (Byte + 1)
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/* DWORD PTR on instruction */
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#define Dword (Word + 1)
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/* QWORD PTR on instruction */
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#define QWord (Dword + 1)
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/* XMMWORD PTR on instruction */
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#define Xmmword (QWord + 1)
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/* instruction needs FWAIT */
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#define FWait (No_ldSuf + 1)
|
||||
#define FWait (Xmmword + 1)
|
||||
/* quick test for string instructions */
|
||||
#define IsString (FWait + 1)
|
||||
/* fake an extra reg operand for clr, imul and special register
|
||||
@ -256,6 +270,13 @@ typedef struct i386_opcode_modifier
|
||||
unsigned int no_ssuf:1;
|
||||
unsigned int no_qsuf:1;
|
||||
unsigned int no_ldsuf:1;
|
||||
unsigned int no_xsuf:1;
|
||||
unsigned int checksize:1;
|
||||
unsigned int byte:1;
|
||||
unsigned int word:1;
|
||||
unsigned int dword:1;
|
||||
unsigned int qword:1;
|
||||
unsigned int xmmword:1;
|
||||
unsigned int fwait:1;
|
||||
unsigned int isstring:1;
|
||||
unsigned int regkludge:1;
|
||||
|
||||
@ -907,14 +907,14 @@ movd, 2, 0x660f6e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No
|
||||
movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
// In the 64bit mode the short form mov immediate is redefined to have
|
||||
// 64bit displacement value.
|
||||
movq, 2, 0xf6f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
|
||||
movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX }
|
||||
movq, 2, 0xf30f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX }
|
||||
movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
|
||||
movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
movq, 2, 0xf6f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
|
||||
movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX }
|
||||
movq, 2, 0xf30f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|CheckSize|QWord|No_ldSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX }
|
||||
movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
|
||||
movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
// We put the 64bit displacement first and we only mark constants
|
||||
// larger than 32bit as Disp64.
|
||||
movq, 2, 0xa0, None, 1, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp64, Acc }
|
||||
|
||||
3946
opcodes/i386-tbl.h
3946
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user